Page 1 SmartTime Static Timing Analyzer User Guide SmartFusion2, IGLOO2, RTG4, and PolarFire NOTE: PDF files are intended to be viewed on the printed page; links and cross-references in this PDF file may point to external files and generate an error when clicked. View the online help included with...
Page 3 Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications.
Page 4: Table Of Contents
About SmartTime (Enhanced Constraint Flow) ................. 7 Design Flows with SmartTime ....................9 Starting and Closing SmartTime - SmartFusion2, IGLOO2, RTG4, and PolarFire ....10 SmartTime Components ......................10 Setting SmartTime Options - SmartFusion2, IGLOO2, RTG4, and PolarFire ......11 SmartTime Toolbar ........................
Page 5 Manage Clock Domains Dialog Box ..................99 Set False Path Constraint Dialog Box..................100 SmartTime Options Dialog Box - SmartFusion2, IGLOO2, RTG4, and PolarFire ....102 Store Filter as Analysis Set Dialog Box ................. 105 Timing Bottleneck Analysis Options Dialog Box ..............106 Timing Datasheet Report Options Dialog Box ...............
Page 7: About Smarttime (Enhanced Constraint Flow)
SmartTime Static Timing Analyzer User Guide About SmartTime (Enhanced Constraint Flow) SmartTime is the Libero SoC gate-level static timing analysis tool. With SmartTime, you can perform complete timing analysis of your design to ensure that you meet all timing constraints and that your design operates at the desired speed with the right amount of margin across all operating conditions.
Page 8 SmartTime Static Timing Analyzer User Guide SmartTime and Cross-Probing into Chip Planner From SmartTime, you can select a design object and cross-probe the same design object in Chip Planner. Design objects that can be cross-probed from SmartTime to Chip Planner include: •...
Page 9: Design Flows With Smarttime
SmartTime Static Timing Analyzer User Guide Design Flows with SmartTime You can access SmartTime in Libero SoC either implicitly or explicitly during the following phases of design implementation: • During Place and Route – When you select timing-driven place-and-route, SmartTime runs in the background to provide accurate timing information.
Page 10: Starting And Closing Smarttime - Smartfusion2, Igloo2, Rtg4, And Polarfire
Starting and Closing SmartTime - SmartFusion2, IGLOO2, RTG4, and PolarFire You must have completed Place and Route for your design before using SmartTime interactively. If your design has not yet been placed-and-routed, Libero SoC will complete that phase prior to starting SmartTime.
Page 11: Setting Smarttime Options - Smartfusion2, Igloo2, Rtg4, And Polarfire
In the General category, select the settings for the operating conditions. SmartTime performs maximum or minimum delay analysis based on the Best, Typical, or Worst case. Check or uncheck whether you want SmartTime to use inter-clock domains in calculations for timing analysis.
Page 12 SmartTime Static Timing Analyzer User Guide Figure 2 · SmartTime Options Dialog Box – Analysis Options Figure 3 · SmartTime Options Dialog Box – Advanced Options See Also SmartTime Options Dialog Box...
Page 13: Smarttime Toolbar
SmartTime Static Timing Analyzer User Guide SmartTime Toolbar The SmartTime toolbar contains commands for constraining or analyzing designs. Tool tips are available for each button. Table 1 · SmartTime Toolbar Icon Description Commits the changes Prints the contents of the...
Page 14: Smarttime Timing Analyzer
SmartTime Static Timing Analyzer User Guide SmartTime Timing Analyzer The SmartTime Timing Analyzer is an interactive Static Timing Analysis tool. Click Open SmartTime in the Design Flow Window to invoke the SmartTime Timing Analyzer (Design Flow Window > Open SmartTime...
Page 15: Smarttime Timing Analyzer
SmartTime Static Timing Analyzer User Guide SmartTime Timing Analyzer...
Page 16: Components Of The Smarttime Timing Analyzer
Components of the SmartTime Timing Analyzer Use the SmartTime Timing Analyzer to visualize and identify timing issues in your design for the selected scenario. In this view, you can evaluate how far you are from meeting your timing requirements, create custom sets to track, set timing exceptions to obtain timing closure, and cross-probe paths with other tools.
Page 17: Analyzing Your Design
• In the Design Flow window, click the Timing Analyzer icon to display the SmartTime Timing Analyzer. • From the SmartTime Tools menu, choose Timing Analyzer > Maximum Delay Analysis or Minimum Delay Analysis. • Click the icon for Maximum Delay Analysis or the icon for Minimum Delay Analysis from the SmartTime window.
Page 18 In cases where the minimum pulse width of one element on the critical path limits the maximum frequency for the clock, SmartTime displays an icon for the clock name in the Summary List. Click on the icon to display the name of the pin that limits the clock frequency.
Page 19: Performing A Bottleneck Analysis
Performing a Bottleneck Analysis To perform a bottleneck analysis From SmartTime’s Max/Min Delay Analysis View, select Tools > Bottleneck Analysis. The Timing Bottleneck Analysis Options dialog box appears. Select the options you wish to display for bottleneck information and click OK.
Page 20 Instance name: refers to the output pin name of the instance. • Bottleneck cost: displays the pin's cost given the chosen cost type. Pin names are listed in decreasing order of their cost type. See Also Timing Bottleneck Analysis Options dialog box (SmartTime)
Page 21: Managing Clock Domains
Move Up or Move Down to change the order in the list. Click OK. SmartTime updates the Domain Browser based on your specifications. If you have added a new clock domain, then it will include at least the three path sets as mentioned above.
Page 22: Managing Path Sets
(as shown below). Tip: You can click the icon in the SmartTime window bar to display the Add Path Analysis Set dialog box. Figure 8 · Add Path Analysis Set Dialog Box Enter a name for the path set.
Page 23 SmartTime Static Timing Analyzer User Guide Figure 9 · Updated Domain Browser with User Sets To remove an existing path set: Select the path set from the User Sets in the Domain Browser. Right-click the set to delete, and then choose Delete Set from the right-click menu.
Page 24: Displaying Path List Timing Information
SmartTime Static Timing Analyzer User Guide Displaying Path List Timing Information The Path List in the Timing Analysis View displays the timing information required to verify the timing requirements and identify violating paths. The Path List is organized in a grid where each row represents a timing path with the corresponding timing information displayed in columns.
Page 25 To remove one or more columns, select the fields to remove from the Show these fields in this order list, and click Remove. Click OK to add or remove the selected columns. SmartTime updates the Timing Analysis View. See Also...
Page 26: Displaying Expanded Path Timing Information
SmartTime Static Timing Analyzer User Guide Displaying Expanded Path Timing Information SmartTime displays the list of paths and the path details for all parallel paths. Figure 11 · Expanded Path View The Path List displays all parallel paths in your design. The Path Details grid displays the path details for all parallel paths.
Page 27 Profile chart displays the percentage of time taken by cells and nets for the selected path. If no parallel path is selected in this view, the Path Profile shows the percentage for all paths. By default, SmartTime only shows one path for each Expanded Path. You can change this default in the SmartTime Options dialog box.
Page 28: Using Filters
Using Filters You can use filters in SmartTime to limit the Path List content (that is, create a filtered list on the source and sink pin names). The filtering options appear on the top of the Timing Analysis View. You can save these filters one level below the set under which it has been created.
Page 29 SmartTime Static Timing Analyzer User Guide Figure 15 · my_filter01 Figure 16 · Updated Maximum Delay Analysis View Repeat the above steps and cascade as many sets as you need using the filtering mechanism.
Page 30 SmartTime Static Timing Analyzer User Guide To remove a set created with filters: Select the set that uses filters. Right-click the set, and choose Delete Set from the shortcut menu. To rename a set created with filters: Select the set that uses filters.
Page 31: Advanced Timing Analysis
SmartTime Static Timing Analyzer User Guide Advanced Timing Analysis...
Page 32: Understanding Inter-Clock Domain Analysis
Generated Clock Constraints for each of the clock domains in order for SmartTime to do execute the calculation and show timing for each of the inter-clock-domain paths.
Page 33: Activating Inter-Clock Domain Analysis
SmartTime Static Timing Analyzer User Guide Activating Inter-Clock Domain Analysis To activate the inter-clock domain checking: In SmartTime, from the Tools menu choose Options. The SmartTime Options Dialog Box dialog box appears (as shown below). In the general category, check the Include inter-clock domains in calculations for timing analysis.
Page 34: Displaying Inter-Clock Domain Paths
CK1, SmartTime automatically detects all other domains CKn with paths ending at CK1. SmartTime creates inter-clock domain sets CKn to CK1 under the domain CK1. Each of these sets enables you to display the inter-clock domain paths between a given clock domain and CK1.
Page 35: Deactivating A Specific Inter-Clock Domain
SmartTime Static Timing Analyzer User Guide Deactivating a Specific Inter-Clock Domain To deactivate the inter-clock domain checking for the specific clock domains clk2->clk1, without disabling this option for the other clock domains: From the Tools menu, choose Constraints Editor to open the Constraints Editor View.
Page 36: Changing Output Port Capacitance
SmartTime automatically uses the modified delay model for delay calculations. To change the output port capacitance and view the effect of this change in SmartTime Timing Analyzer, refer to the following example. The figure below shows the delay from FF3 to output port OUT2. It shows a delay of 6.603 ns based on the default loading of 35 pF.
Page 37: Generating Timing Reports
SmartTime Static Timing Analyzer User Guide Generating Timing Reports...
Page 38: Types Of Reports
SmartTime Static Timing Analyzer User Guide Types of Reports Using SmartTime you can generate the following types of reports: • Timer report – This report displays the timing information organized by clock domain. • Timing Violations report – This flat slack report provides information about constraint violations.
Page 39: Generating A Timing Report
Maximum delays for each clock network • Maximum delays for interactions between clock networks To generate a timing report: From the SmartTime Max/Min Delay Analysis View, choose Reports > Timer. The Timing Report Options Dialog Box appears. Select the options you want to include in the report, and then click OK.
Page 40: Understanding Timing Reports
The summary section reports the timing information for each clock domain. By default, the clock domains reported are the explicit clock domains that are shown in SmartTime. You can filter the domains and get only specific sections in the report (see Timing Report Options Dialog Box).
Page 41 SmartTime Static Timing Analyzer User Guide Inter-clock domain This set reports the paths from the registers clock pins of the specified clock domain to the registers data pins in the current clock domain. Inter-domain paths are not reported by default.
Page 42 SmartTime Static Timing Analyzer User Guide Figure 23 · Timing Report See Also Generating a Timing Report Timing Report Options Dialog Box...
Page 43: Generating A Timing Violation Report
The timing violations report provides a flat slack report centered around constraint violations. To generate a timing violation report From the SmartTime Max/Min Delay Analysis View window, choose Tools > Reports > Timing Violations. The Timing Violations Report Options Dialog Box appears.
Page 44: Understanding Timing Violation Reports
SmartTime Static Timing Analyzer User Guide Understanding Timing Violation Reports The timing violation report contains the following sections: Header The header lists: • The report type • The version of Designer used to generate the report • The date and time the report was generated •...
Page 45 SmartTime Static Timing Analyzer User Guide Figure 24 · Timing Violations Report See Also Generating a Timing Violation Report Timing Violations Report Options Dialog Box...
Page 46: Generating A Constraints Coverage Report
Generating a Constraints Coverage Report The constraints coverage report contains information about the constraints in the design. To generate a constraints coverage report, from the SmartTime Max/Min Delay Analysis View, choose Tools > Reports > Constraints Coverage. The report appears in a separate window.
Page 47: Understanding Constraints Coverage Reports
SmartTime Static Timing Analyzer User Guide Understanding Constraints Coverage Reports The constraint coverage displays the overall coverage of the timing constraints set on the current design. You can generate this report either from within Designer or within SmartTime Analyzer. The report contains three sections: •...
Page 48 SmartTime Static Timing Analyzer User Guide constraint and it is satisfied), Violated (there is a constraint and it is not satisfied), or Untested (no constraint was found). Clock Domain This section provides a coverage summary for each clock domain. Enhancement Suggestions The enhancement suggestion reports, per clock domain, a list of constraints that can be added to the design to improve the coverage.
Page 49: Generating A Bottleneck Report
Generating a Bottleneck Report The bottleneck report provides a list of the bottlenecks in the design. To generate a bottleneck report, from the,SmartTime Max/Min Delay Analysis View, choose Tools > Reports > Bottleneck. The report appears in a separate window.
Page 50: Understanding Bottleneck Reports - Smartfusion2, Igloo2, Rtg4, And Polarfire
SmartTime Static Timing Analyzer User Guide Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire A bottleneck is a point in the design that contributes to multiple timing violations. The purpose of the bottleneck report is to provide a list of the bottlenecks in the design. You can generate this report either from SmartTime Analyzer.
Page 51 SmartTime Static Timing Analyzer User Guide • Instance name: refers to the output pin name of the instance. • Path Count: Displays the number of violating paths which include the instance pin. See Also Timing Bottleneck Analysis Options Dialog Box...
Page 52: Generating A Datasheet Report
Generating a Datasheet Report The datasheet reports information about the external characteristics of the design. To generate a datasheet report, from the SmartTime Max/Min Delay Analysis View, choose Tools > Reports > Datasheet. The report appears in a separate window.
Page 53: Understanding Datasheet Reports
SmartTime Static Timing Analyzer User Guide Understanding Datasheet Reports The datasheet report displays the external characteristics of the design. . You can generate this report from SmartTime Max/Min Delay Analysis View. It contains three tables: • Pin Description • DC Electrical Characteristics •...
Page 54 SmartTime Static Timing Analyzer User Guide AC Electrical Characteristics Provides the timing properties of the ports of the design. For each clock, this section includes the maximum frequency. For each input, it includes the external setup, external hold, external recovery, and external removal for every clock where it applies.
Page 55: Generating A Combinational Loop Report
SmartTime Static Timing Analyzer User Guide Generating a Combinational Loop Report The combinational loop report displays all loops found during initialization and reports pins associated with the loop(s), and the location where the loop is broken. To generate the combinational loop report; from the Tools menu, choose Reports > Combinational Loops ..
Page 56: Understanding Combinational Loop Reports
SmartTime Static Timing Analyzer User Guide Understanding Combinational Loop Reports The combinational loop report displays all loops found during initialization and reports pins associated with the loop(s), and the location where the loop is broken. Figure 28 · Combinational Loop Report...
Page 57: Timing Concepts
SmartTime Static Timing Analyzer User Guide Timing Concepts...
Page 58: Static Timing Analysis Versus Dynamic Simulation
Paths that start at sequential components internal to the design and end at output ports. SmartTime displays this category under the Clock to Out set of each displayed clock domain. • Paths that start at input ports and end at output ports. SmartTime displays this category under the Input to Output set. Maximum Clock Frequency Generally, you set clock constraints on clocks for which you have a specified requirement.
Page 59 SmartTime Static Timing Analyzer User Guide Setup check specifies when data is required to be present at the input of a sequential component in order for the clock to capture this data effectively into the component. Timing analyzers evaluate the setup check as a maximum timing budget allowed between adjacent sequential elements.
Page 60: Timing Exceptions Overview
The clock skew between two different sequential components is the difference between the insertion delays from the clock source to the clock pins of these components. SmartTime calculates the arrival time at the clock pin of each sequential component. Then it subtracts the arrival time at the receiving component from the arrival time at the launching component to obtain an accurate clock skew.
Page 61 Constraint Editor is not open. Add the Constraint in the Add Constraint dialog box. Note that the source/from pin and destination/to pin field are populated with the correct pin names captured from the SmartTime reported path (Source Pin and Sink Pin) you have clicked.
Page 62 Ports • Nets/Paths Note: Cross-probing of design objects is available from SmartTime to Chip Planner but not vice versa. Before you can cross-probe from SmartTime to Chip Planner, you must: Complete the Place and Route step on the design. Open both SmartTime and Chip Planner.
Page 63 Open SmartTime Maximum/Minimum Analysis View. Open Chip Planner. In the SmartTime Maximum Analysis View, right-click the instance Q[2] in the Timing Path Graph and choose Show in Chip Planner. Note that with cross-probing, the Q[2] macro is selected in Chip Planner’s Logical View and highlighted (white) in the Chip Canvas.
Page 64 Open the SmartTime Maximum/Minimum Analysis View. Open Chip Planner. In the SmartTime Maximum/Minimum Analysis View, right-click the Port “CLK” in the Path and choose Show in Chip Planner. Note that the Port “CLK” is selected and highlighted in the Chip Planner Port View.
Page 65 SmartTime Static Timing Analyzer User Guide Figure 35 · Cross-Probing – Port From the Properties View inside Chip Planner, you will find useful information about the Port “CLK” you are cross-probing: • Port Type • Port Placement Location (X-Y coordinates) •...
Page 66 SmartTime Static Timing Analyzer User Guide...
Page 67: Smarttime Tutorials (Enhanced Constraints Flow)
Tutorial 1 - 32-Bit Shift Register with Clock Enable This tutorial section describes how to enter a clock constraint for the 32-bit shift register shown. You will use the SmartTime Constraints Editor and perform post-layout timing analysis using the SmartTime Timing Analyzer.
Page 68 SmartTime Static Timing Analyzer User Guide Figure 38 · New Project Creation - 32 Bit Shift Register Click Next to go to Device Selection page. Make the following selection from the pull-down menu: • Family: SmartFusion2 • Die: M2S090TS •...
Page 69 SmartTime Static Timing Analyzer User Guide In the Add HDL source files page, click Import file to import the source file, Navigate to the location of the source Verilog file for the 32-bit shift register you have downloaded from the Microsemi website.
Page 70 SmartTime Static Timing Analyzer User Guide Figure 40 · HDL File shift_reg32.v in the Libero SoC File Window Confirm that the shift_reg32 design appears in the Design Hierarchy window, as shown in the figure below.
Page 71 SmartTime Static Timing Analyzer User Guide Figure 41 · shift_reg32 in the Design Hierarchy Window In the Design Flow window, double-click Synthesize to run Synplify Pro with default settings. A green check marks appears next to Synthesize when Synthesis is successful (as shown in the figure below).
Page 72 SmartTime Static Timing Analyzer User Guide Figure 42 · Synthesis and Compile Complete - 32-Bit Shift Register with Clock Enable Add a Clock Constraint - 32 Bit Shift Register To add a clock constraint to your design: In the Design Flow window, double-click Manage Constraints. The Constraint Manager appears (as shown in the figure below.)
Page 73 SmartTime Static Timing Analyzer User Guide Click Edit with Constraints Editor > Edit Place and Route Constraints. The Constraints Editor appears. Figure 44 · Constraints Editor – Add clock constraint In the Constraints Editor, right-click Clock under Requirement and select Add Clock Constraint.
Page 74 From the File menu, choose Save to save the constraints. From the SmartTime File menu, choose Exit to exit SmartTime. Libero creates a constraint file to store the clock constraint. This file is listed and displayed in the Constraint Manager. It is named user.sdc and is designated as Target.
Page 75 SmartTime Static Timing Analyzer User Guide Figure 48 · SDC Constraint File and Tool Association Run Place and Route Right-click Place and Route and choose Configure Options. Click the checkbox to enable Timing-Driven layout in Layout Options and leave the other values at the default settings (as shown in the figure below).
Page 76 Right-click Open SmartTime in the Design Flow window and choose Open Interactively to open SmartTime. The Maximum Delay analysis window appears. A green check next to the clock name indicates there are no timing violations for that clock domain. The Summary page displays a summary of the clock domain timing performance.
Page 77 SmartTime Static Timing Analyzer User Guide Figure 51 · SmartTime Register to Register Delay Double-click a path row to open the Expanded Path window. The window shows a calculation of the data arrival and required times along with a schematic of the path (as shown in the figure below).
Page 78 SmartTime Static Timing Analyzer User Guide Figure 53 · SmartTime - Input to Register Path Analysis Select Clock to Output to display the register to output timing. Select Path 1. The maximum clock to output time from Q_int[16]:CLK to Q[16 ] is 9.486ns .
Page 79 Minimum Delay Analysis with Timing Analyzer - 32-Bit Shift Register Example The SmartTime Minimum Delay Analysis window identifies any hold violations that exist in the design. To perform Minimum Delay Analysis: From the SmartTime Analysis window, choose Tools > Minimum Delay Analysis. The Minimum Delay Analysis View appears, as shown in the figure below.
Page 80 SmartTime Static Timing Analyzer User Guide Figure 56 · SmartTime Minimum Delay Analysis Changing Constraints and Observing Results - 32-Bit Shift Register Example You can use the Constraints Editor to change your constraints and view the results in your design. To do so: Open the Constraints Editor (Constraints Manager >...
Page 81 Tutorial 4 - False Path Constraints This section describes how to enter false path constraints in SmartTime. You will import an RTL source file from the design shown below. After routing the design, you will analyze the timing, set false path constraints, and observe the maximum operating frequency in the SmartTime Timing Analysis window.
Page 82 SmartTime Static Timing Analyzer User Guide • Speed: STD • Die Voltage: 1.2 V • Range: COM Click Finish to create the new project. At the pop-up window, click Use Enhanced Constraint Flow in the New Project Information dialog box.
Page 83 SmartTime Static Timing Analyzer User Guide Figure 61 · false_path Design in Design Hierarchy In the Design Flow window, double-click Synthesize to run synthesis. A green check mark appears when the Synthesis step completes successfully. Expand Edit Constraints. Right-click Timing Constraints and choose Open Interactively.
Page 84 SmartTime Static Timing Analyzer User Guide Save your changes (File > Save) and close the Constraints Editor (File > Close). In the Constraint Manager, check the checkbox under Place and Route and the checkbox under Timing Verification to associate the constraint file to both tools. The constraint file is used for both Place and Route and Timing Verification.
Page 85 Expand Verify Post Layout Implementation. Right-click Open SmartTime and choose Open Interactively to open SmartTime. The Maximum Delay Analysis View appears (as shown in the figure below). The Maximum Delay Analysis View displays a summary of design performance and indicates that the design will operate at a maximum frequency of 442.48 MHz.
Page 86 SmartTime Static Timing Analyzer User Guide Figure 66 · Maximum Delay Analysis Summary Expand clk to expand the display and show the Register to Register path sets. Select Register to Register to display the register-to-register paths. Notice that the slack values are positive.
Page 87 "Edit with Constraint Editor" , and choose "Edit Timing Verification Constraints". Leave this running and go back to SmartTime. From the Tools menu select Max Delay Analysis. To set the path from D0_inv_reg:CLK to Q_reg :D as false, select the row containing this path in the Register to Register path set, right-click and choose Add False Path Constraint (as shown in the figure below).
Page 88 Analysis. It is possible to use different constraint files, in which case we would not need to re-run P&R. Right-click on Open SmartTime and choose Update and Open Interactively. You will see that Place and Route is run automatically before SmartTime is re-started.
Page 89 SmartTime Static Timing Analyzer User Guide Note: The maximum operating frequency may vary slightly with a different version of the Libero software. Figure 72 · Maximum Delay Analysis View - Summary Select the Register to Register set for my_clk. Observe that only one path is visible, from D2_reg: CLK to Q_reg:D.
Page 90 SmartTime Static Timing Analyzer User Guide false_path.v ///////////////////////////////////////////////////////// // Company: Microsemi Corp // File history: 0.1 Initial Version // Description: // Simple example design to demonstrate use of timing constraints. // Targeted device: Family::SmartFusion2; Die::M2S050; Package::484 FBGA; // Author: Vishakh Rayapeta //////////////////////////////////////////////////////////// module false_path (D0, D1, D2, RST, CLK, Q);...
Page 91 SmartTime Static Timing Analyzer User Guide Q_reg <= NOT2; not u1 (NOT1, MUX2); not u2 (NOT2, NOT1); endmodule...
Page 92: Dialog Boxes
SmartTime Static Timing Analyzer User Guide Dialog Boxes...
Page 93: Add Path Analysis Set Dialog Box
The Analysis menu is available only in Maximum or Minimum Delay Analysis view. To open the Add Path Analysis Set dialog box (shown below) from the SmartTime Max/Min Delay Analysis View, right-click a path group in the Domain Browser and select Add Set.
Page 94 SmartTime Static Timing Analyzer User Guide Source Pins Displays a list of available and valid source pins. You can select multiple pins. To select all source pins, click the Select All button beneath the Source Pins list. Select All Selects all the pins in the Source Pins list to include in the path analysis set.
Page 95: Analysis Set Properties Dialog Box
SmartTime Static Timing Analyzer User Guide Analysis Set Properties Dialog Box Use this dialog box to view information about the user created set. To open the Analysis Set Properties dialog box (shown below) from the Timing Analysis View, right-click any user-created set in the Domain Browser, and choose Properties from the shortcut menu.
Page 96: Edit Filter Set Dialog Box
Use this dialog box to specify a filter. To open the Edit Filter Set dialog box (shown below) from the SmartTime Max/Min Delay Analysis view, right-click an existing filter set in the clock domain browser, and then choose Edit Set from the shortcut menu.
Page 97: Customize Analysis View Dialog Box
Use this dialog box to customize the timing analysis grid. To open the Customize Analysis View dialog box (shown below) from the SmartTime Max/Min Delay Analysis View, click the Customize table button (circled in red in the figure below) in the Max/Min Delay Analysis View.
Page 98 SmartTime Static Timing Analyzer User Guide Restore Defaults Resets all the options in the General panel to their default values.
Page 99: Manage Clock Domains Dialog Box
Manage Clock Domains Dialog Box Use this dialog box to specify the clock pins you want to see in the Expanded Path view. To open the Manage Clock Domain dialog box (shown below) from the SmartTime Max/Min Delay Analysis view, click the icon.
Page 100: Set False Path Constraint Dialog Box
The false path information always takes precedence over multiple cycle path information and overrides maximum delay constraints. To open the Set False Path Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Constraints > False Path. Figure 80 · Set False Path Constraint Dialog Box From Specifies the starting points for false path.
Page 101 SmartTime Static Timing Analyzer User Guide Specifies the ending points for false path. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell. Comment Enables you to provide comments for this constraint.
Page 102: Smarttime Options Dialog Box - Smartfusion2, Igloo2, Rtg4, And Polarfire
General • Analysis • Advanced To open the SmartTime Options dialog box (shown below) from the SmartTime tool, choose Tools > Options. General Figure 81 · SmartTime Options - General Dialog Box Operating Conditions Allows you to perform maximum or minimum delay analysis based on the Best, Typical, or Worst case. By default, maximum delay analysis is based on WORST case and minimum delay analysis is based on BEST case.
Page 103 Displays the clock network details as well as the data path details in the Expanded Path views. Limit the number of parallel paths in expanded path to: For each expanded path, specify the maximum number of parallel paths that SmartTime displays. The default number of parallel paths is 1. Restore Defaults...
Page 104 SmartTime Static Timing Analyzer User Guide Advanced Figure 83 · SmartTime Options - Advanced Dialog Box Special Situations Enables you to specify if you need to use loopback in bi-directional buffers (bibufs) and/or break paths at asynchronous pins. Scenarios Enables you to select the scenario to use for timing analysis and for timing-driven place-and-route.
Page 105: Store Filter As Analysis Set Dialog Box
Store Filter as Analysis Set Dialog Box Use this dialog box to specify a filter. To open the Store Filter as Analysis Set dialog box (shown below) from the SmartTime Timing Analyzer, select a path and click the Store Filter button in the Analysis View Filter.
Page 106: Timing Bottleneck Analysis Options Dialog Box
• Bottleneck pane • Sets pane To open the Timing Bottleneck Analysis Options dialog box (shown below) from the SmartTime tool, choose Tools > Bottleneck Analysis. General Pane Figure 85 · Timing Bottleneck Report - General Pane Dialog Box Slack Lets you specify whether the reported paths will be filtered by threshold, and if so what will be the maximum slack to report.
Page 107 Figure 86 · Timing Bottleneck Report - Bottleneck Pane Dialog Box Bottleneck Options Cost Type: Select the cost type that SmartTime will include in the bottleneck report. By default, path count is selected. You may select one of the following two items from the drop-down list: •...
Page 108 SmartTime Static Timing Analyzer User Guide Sets Pane Figure 87 · Timing Bottleneck Report - Sets Pane Dialog Box This pane has four mutually exclusive options: • Entire Design • Clock Domain • Use existing user set • Use Input to Output Set Entire Design: Select this option to display the bottleneck information for the entire design.
Page 109 SmartTime Static Timing Analyzer User Guide Filter: Allows you to filter the bottleneck report by the following options: • From: Reports only cells that lie on violating paths that start at locations specified by this option. • To: Reports only cells that lie on violating paths that end at locations specified by this option.
Page 110: Timing Datasheet Report Options Dialog Box
Timing Datasheet Report Options Dialog Box Use this dialog box to select the output format for your timing datasheet report. To open the Timing Datasheet Report Options dialog box (shown below) from the SmartTime Max/Min Delay Analysis view, choose Tools > Reports > Datasheet.
Page 111: Timing Report Options Dialog Box
Paths • Sets • Clock Domains To open the Timing Report Options dialog box (shown below) from the SmartTime Max/Min Delay Analysis View, choose Tools > Reports> Timer. General Figure 89 · Timing Report Options - General Dialog Box Format Specifies whether or not the report will be exported as a Comma Separated Value (CSV) file or a plain text file.
Page 112 SmartTime will include per section in the report. Limit the number of parallel paths in expanded path to: For each expanded path, specify the maximum number of parallel paths that SmartTime will include in the report. The default number of parallel paths is 1. Restore Defaults...
Page 113 SmartTime Static Timing Analyzer User Guide Sets Figure 91 · Timing Report Options - Sets Dialog Box Display of Sets Specifies whether or not the user sets will be included in the timing report. User sets are either filters that you have created and stored on the default paths sets (Register to Register, Inputs to Register, etc.) or Pin to Pin user sets.
Page 114 SmartTime Static Timing Analyzer User Guide Clock Domains Figure 92 · Timing Report Options - Clock Domains Dialog Box Display of Clock Domains Lets you specify what clock domains will be included in the report. By default, the current clock domains used by the timing engine will be reported.
Page 115: Timing Violations Report Options Dialog Box
You can set report violation options for the following categories: • General • Paths To open the Timing Report Options dialog box (shown below) from the SmartTime tool, choose Tools > Reports > Timing Violations. General Figure 93 · Timing Violations Report - General Dialog Box Format Specifies whether or not the report will be exported as a Comma Separated Value (CSV) file or a plain text file.
Page 116 SmartTime will include per section in the report. The default number of expanded paths is 0. Limit the number of parallel paths in expanded path to: For each expanded path, specify the maximum number of parallel paths that SmartTime will include in the report. The default number of parallel paths is 1. Restore Defaults Resets all the options in the Paths panel to their default values.
Page 117: Data Change History - Smarttime
The data change history lists features, enhancements and bug fixes for the current software release that may impact timing data of the current design. To generate a data change history, from the Help menu, choose Data Change History. This opens a data change history in text format. Figure 95 · SmartTime Data Change History Report...
Page 118: Tcl Commands
SmartTime Static Timing Analyzer User Guide Tcl Commands...
Page 119: Create_Set
SmartTime Static Timing Analyzer User Guide create_set Tcl command; creates a set of paths to be analyzed. Use the arguments to specify which paths to include. To create a set that is a subset of a clock domain, specify it with the -clock and -type arguments. To create a set that is a subset of an inter-clock domain set, specify it with the -source_clock and - sink_clock arguments.
Page 120 SmartTime Static Timing Analyzer User Guide Specifies a filter on the source pins of the parent set. If you do not specify a parent set, this option filters all pins in the current design. -sink <port/pin_pattern> Specifies a filter on the sink pins of the parent set. If you do not specify a parent set, this option filters all pins in the current design.
Page 121: Expand_Path
{MYCLOCK} -type {register_to_register}. Path details contain the pin name, type, net name, cell name, operation, delay, total delay, and edge as well as the arrival time, required time, and slack. These details are the same as details available in the SmartTime Expanded Path window. expand_path...
Page 122 SmartTime Static Timing Analyzer User Guide Value Description external_removal Set of paths from inputs to asynchronous pins async_to_reg Path from asynchronous pins to registers -from_clock clock_name Displays a list of timing paths for an inter-clock domain set belonging to the source clock specified. You can only use this option with the -to_clock option, not by itself.
Page 123: List_Paths
SmartTime Static Timing Analyzer User Guide list_paths Tcl command; returns a list of the n worst paths matching the arguments. The number of paths returned can be changed using the set_options -limit_max_paths < > command. value list_paths -analysis < >...
Page 124 SmartTime Static Timing Analyzer User Guide Example The following command displays the list of register to register paths of clock domain clk1: puts [ list_paths -clock clk1 -type reg_to_reg ] See Also create_set expand_path set_options...
Page 125: Remove_Set
SmartTime Static Timing Analyzer User Guide remove_set Tcl command; removes a set of paths from analysis. Only user-created sets can be deleted. remove_set -name name Parameters -name name Specifies the name of the set to delete. Example The following command removes the set named my_set:...
Page 126: Report
SmartTime Static Timing Analyzer User Guide report Tcl command; specifies the type of reports to generate and what to include in the reports. report -type (timing|violations | datasheet|bottleneck | constraints_coverage | combinational_loops) -analysis <max_or_min>\ -format (csv|text) <filename> timing options -max_parallel_paths <number>...
Page 127 SmartTime Static Timing Analyzer User Guide Value Description text Generates a text report (default). Generates the report in a comma-separated value format which you can import into a spreadsheet. -filename Specifies the file name for the generated report. Timing Options and Values...
Page 128 SmartTime Static Timing Analyzer User Guide Parameter/Value Description -include_pin_to_pin Yes to include and no to exclude pin-to-pin paths in the (yes|no) timing report. Bottleneck Options and Values Parameter/Value Description -cost_type Specifies the cost_type as either path_count or path_cost. For <path_count|path_cost>...
Page 129 SmartTime Static Timing Analyzer User Guide Parameter/Value Description Reports only bottleneck instances that lie on violating timing -from_clock <clock paths of the inter-clock domain that starts at the source clock name> specified by this option. This option can only be used in combination with -to_clock.
Page 130: Save
SmartTime Static Timing Analyzer User Guide save Tcl command; saves all changes made prior to this command. This includes changes made on constraints, options and sets. save Arguments None Example The following script sets the maximum number of paths reported by list_paths to 10, reads an SDC file, and...
Page 131: Set_Options (Smartfusion2, Igloo2, Rtg4, And Polarfire)
SmartTime Static Timing Analyzer User Guide set_options (SmartFusion2, IGLOO2, RTG4, and PolarFire) SmartTime-specific Tcl command; sets options for timing analysis. Some options will also affect timing- driven place-and-route. The same parameters can be changed in the SmartTime Options dialog box in the SmartTime GUI. set_options...
Page 132 SmartTime Static Timing Analyzer User Guide Value Description Enables inter-clock domain analysis Disables inter-clock domain analysis -use_bibuf_loopbacks value Instructs the timing analysis whether to consider loopback path in bidirectional buffers (D->Y, E->Y)as false-path {no}. Default is yes; i.e., loopback are false paths.
Page 133 SmartTime Static Timing Analyzer User Guide Value Description Disables expanded clock network information in paths -expand_parallel_paths value Specify the number of parallel paths {paths with the same ends} to include in expand_path. Default is 1. -analysis_scenario value Specify the constraint scenario to be used for timing analysis. Default is Primary, the default scenario.
Page 134: Glossary
SmartTime Static Timing Analyzer User Guide Glossary arrival time Actual time in nanoseconds at which the data arrives at a sink pin when considering the propagation delays across the path. asynchronous Two signals that are not related to each other. Signals not related to the clock are usually asynchronous.
Page 135 SmartTime Static Timing Analyzer User Guide path A sequence of elements in the design that identifies a logical flow starting at a source pin and ending at a sink pin. path details An expansion of the path that shows all the nets and cells between the source pin and the sink pin.
Page 136 Synopsys tools to specify the design intent, including the timing and area constraints for a design. Microsemi SoC tools use a subset of the SDC format to capture supported timing constraints. You can import or export an SDC file from the Designer software. Any timing constraint that you can enter using Designer tools, can also be specified in an SDC file.
Page 137 SmartTime Static Timing Analyzer User Guide virtual clock A virtual clock is a clock with no source associated to it. It is used to describe clocks outside the FPGA that have an impact on the timing analysis inside the FPGA. For example, if the I/Os are synchronous to an external clock.

Microsemi SmartTime User Manual

Smarttime Timing Analyzer

Advanced Timing Analysis

Generating Timing Reports

Timing Concepts

Dialog Boxes

Data Change History - Smarttime

Tcl Commands

Glossary

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Summary of Contents for Microsemi SmartTime

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