Table 10-11 Performance Of The Pdh Electrical Interface; Table 10-12 Clock Features Of The Optix Osn 7500 - Huawei OptiX OSN 7500 Technical Manual

OptiX OSN 7500
Technical Manual - System Description
10.2.1 PDH Electrical Interface
Table 10-11 shows performance of the PDH electrical interface of the OptiX OSN
7500.

Table 10-11 Performance of the PDH electrical interface

Type
Code pattern
Bit rate of signals at
output port
Permitted frequency
deviation at input
port
Input jitter tolerance
10.3
Clock Performance
10.3.1 Clock Interface Type
Table 10-12 shows clock features of the OptiX OSN 7500.

Table 10-12 Clock features of the OptiX OSN 7500

Clock type
External
synchronization
source
Synchron-ization
output
10.3.2 Timing and Synchronization Performance
Table 10-13 lists the timing and synchronization performance of the OptiX OSN 7500.
1544 2048
kbit/s kbit/s
B8ZS, HDB3
AMI
G.703 compliant
Feature
Two inputs: 75Ω 2048 kbit/s (G.703 §6) or 2048 kHz (G.703 §10)
Two inputs: 120Ω 2048 kbit/s (G.703 §6) or 2048kHz (G.703 §10)
Two outputs: 75Ω 2048 kbit/s (G.703 §6) or 2048kHz (G.703 §10)
Two outputs: 120Ω 2048 kbit/s (G.703 §6) or 2048 kHz (G.703
§10)
Huawei Technologies Proprietary
10-8
10 Technical Specifications
34368 44736 139264
kbit/s kbit/s kbit/s
HDB3 B3ZS CMI
G.703 compliant
- - -
155520
kbit/s
CMI
-