Analog Devices AD1849K Manual
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Analog Devices AD1849K Manual

Analog Devices AD1849K Manual

Serial-port 16-bit soundport stereo codec
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FEATURES
Single-Chip Integrated
Multiple Channels of Stereo Input and Output
Digital Signal Mixing
On-Chip Speaker and Headphone Drive Capability
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V and Mixed +5 V/+3.3 V Supplies
Serial Interface Compatible with ADSP-21xx Fixed-
Point DS Ps
Compatible with CS4215 (See Text)
PRODUCT OVERVIEW
The Serial-Port AD1849K SoundPort® Stereo Codec integrates
the key audio data conversion and control functions into a single
integrated circuit. The AD1849K is intended to provide a com-
plete, single-chip audio solution for multimedia applications
requiring operation from a single +5 V supply. External signal
path circuit requirements are limited to three low tolerance
capacitors for line level applications; anti-imaging filters are
incorporated on-chip. The AD1849K includes on-chip monaural
SoundPort is a registered trademark of Analog Devices, Inc.
LINE L
LINE R
ANALOG
OUT
MIC L
MIC R
LINE 0 L
LINE 0 R
ANALOG
IN
LINE 1 L
HEADPHONE RETURN
LINE 1 R
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Digital Audio Stereo Codec
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
ANALOG
SUPPLY
SUPPLY
L
GAIN
20
dB
MUX
R
GAIN
LOOPBACK
L
ANALOG
ATTENUATE
FILTER
MUTE
R
ANALOG
ATTENUATE
FILTER
L
∑
MUTE
MUTE
R
OUT
RETURN
MONO SPEAKER
SoundPort Stereo Codec
speaker and stereo headphone drive circuits that require no
additional external components. Dynamic range exceeds 80 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals, from an external
clock, or from the serial interface bit clock.
The Codec includes a stereo pair of Σ∆ analog-to-digital
converters and a stereo pair of Σ∆ digital-to-analog converters.
Analog signals can be input at line levels or microphone levels.
A software controlled programmable gain stage allows
independent gain for each channel going into the ADC. The
ADCs' output can be digitally mixed with the DACs' input.
The left and right channel 16-bit outputs from the ADCs are
available over a single bidirectional serial interface that also sup-
ports 16-bit digital input to the DACs and control information.
The AD1849K can accept and generate 8-bit µ-law or A-law
companded digital data.
The Σ∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images and shaped quantization noise
are removed from the DACs' analog stereo output by on-chip
switched-capacitor and continuous-time filters. Two independent
stereo pairs of line-level (or one line-level and one headphone)
outputs are generated, as well as drive for a monaural (mono)
speaker.
OSCILLATORS
∑∆ A/D
CONVERTER
∑∆ A/D
CONVERTER
∑∆ D/A
INTERPOL
ATTENUATE
CONVERTER
∑∆ D/A
INTERPOL
ATTENUATE
CONVERTER
AD1849K
REFERENCE
2.25V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Serial-Port 16-Bit
AD1849K
CRYSTALS
POWER DOWN
2
2
µ/A
LAW
S
µ/A
E
L
LAW
R
O
I
O
A
P
MONITOR MIX
L
B
A
P
C
µ/A
∑
O
K
LAW
R
T
µ/A
∑
2
LAW
CHAINING
CHAINING
OUTPUT
INPUT
(Continued on page 8)
DIGITAL
I/O
DATA/CONTROL
MODE
DATA/CONTROL
TRANSMIT
DATA/CONTROL
RECEIVE
PARALLEL I/O
BIT CLOCK
FRAME SYNC
RESET
Fax: 617/326-8703

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Summary of Contents for Analog Devices AD1849K

  • Page 1 Point DS Ps ports 16-bit digital input to the DACs and control information. Compatible with CS4215 (See Text) The AD1849K can accept and generate 8-bit µ-law or A-law PRODUCT OVERVIEW companded digital data. The Serial-Port AD1849K SoundPort® Stereo Codec integrates The Σ∆...
  • Page 2 AD1849K–SPECIFICATIONS ELECTRICAL SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED °C Temperature DAC Input Conditions Digital Supply (V 0 dB Attenuation Analog Supply (V Full-Scale Digital Inputs Clock (SCLK) 16-Bit Linear Mode Master Mode 256 Bits per Frame OLB = 1...

  • Page 3: Digital-To-Analog Converters

    AD1849K ANALOG-TO-DIGITAL CONVERTERS Units Resolution* Bits ADC Dynamic Range, A-Weighted Line and Mic with 0 dB Gain (–60 dB Input, THD+N Referenced to Full Scale) Mic with +20 dB Gain (–60 dB Input, THD+N Referenced to Full Scale) ADC THD+N, (Referenced to Full Scale) Line and Mic with 0 dB Gain 0.013...
  • Page 4 AD1849K MONITOR MIX ATTENUATOR Units Step Size (0.0 dB to –60 dB)* Step Size (–61.5 dB to –94.5 dB)* Output Attenuation* –95 DAC ATTENUATOR Units Step Size (0.0 dB to –60 dB) (Tested at Steps –1.5 dB, –19.5 dB, –39 dB and –60 dB) Step Size (–61.5 dB to –94.5 dB)*...

  • Page 5: Power Supply

    AD1849K DIGITAL TIMING PARAMETERS (Guaranteed over +4.75 V to +5.25 V, 0 C to +70 C) Units SCLK Period (t Slave Mode, MS = 0 × Bits per Frame) Master Mode, MS = 1* 1/(F SCLK HI (t Slave Mode, MS = 0...

  • Page 6: Absolute Maximum Ratings

    WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD1849K features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality.

  • Page 7: Pin Description

    AD1849K PIN DESCRIPTION Digital Signals Pin Name PLCC TQFP Description SDRX Receive Serial Data Pin SDTX Transmit Serial Data Pin SCLK Bidirectional Serial Bit Clock FSYNC Frame Sync Output Signal TSOUT Chaining Word Output TSIN Chaining Word Input Data/Control Select Input...

  • Page 8: Functional Description

    FUNCTIONAL DESCRIPTION digitized analog input with the analog output (prior to digitiza- This section overviews the functionality of the AD1849K and is tion). The digital output from the ADCs going out of the serial intended as a general introduction to the capabilities of the data port is unaffected by the monitor mix.
  • Page 9 An autocalibration sequence is also performed when the Figure 1. A-Law or µ -Law Expansion AD1849K leaves the reset state (i.e., RESET goes HI). The RESET pin should be held LO for 50 ms after power up or after When 8-bit companding is specified, the ADCs’ linear output is leaving power-down mode to delay the onset of the autocalibration compressed to the format specified prior to output.
  • Page 10 AD1849K The loopback modes are shown graphically in Figure 3. Clocks and Sample Rates The AD1849K can operate from external crystals, from a 256 × µ/A-LAW SDTX input clock, from an input clock with a programmable divide LINE, MIC GAIN...

  • Page 11: Control Registers

    Data Mode. (See Figure 8.) Control bits can also be read back for system verification. Operation of the AD1849K is determined by the state of these control bits. The 64-bit serial Control Mode and Data Mode control registers have been arbitrarily broken down into bytes for ease of description.
  • Page 12 6.615 Note that the AD1849K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin (COUT1 or COUT2) should be left unconnected.
  • Page 13 Data 1 Data 0 REVID3 REVID2 REVID1 REVID0 REVID3:0 Silicon revision identification. Reads greater than or equal to 0010 (i.e., 0010, 0011, etc.) for the AD1849K. Control Byte 8, Reserved Register Data 7 Data 6 Data 5 Data 4 Data 3...
  • Page 14 AD1849K Data Mode Data and Control Registers Data Byte 1, Left Audio Data—Most Significant 8 Bits Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 In 16-bit linear PCM mode, this byte contains the upper eight bits of the left audio data sample. In the 8-bit companded and linear modes, this byte contains the left audio data sample.
  • Page 15 AD1849K Data Byte 6, Output Setting Register 2 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 ADC Invalid. This bit is set to “1” during the autocalibration sequence, indicating that the serial data output from the ADCs is meaningless.
  • Page 16 A Control-to-Data Mode transition is no exception. An important consequence of these defaults is that the AD1849K Codec always comes out of reset or power down in slave mode with an externally supplied serial bit clock (SCLK) as the clock source. An external device must supply the serial bit clock and the chaining word input signal (TSIN) initially.

  • Page 17: Serial Interface

    Recommended modes are indicated above by “yes.” Note that SERIAL INTERFACE A single serial interface on the AD1849K provides for the trans- Codec performance is improved with a clean clock source, and fer of both data and control information. This interface is simi- in many systems the lowest jitter clocks available will be those lar to AT&T’s Concentrated Highway Interface (CHI), allowing...
  • Page 18 Figure 7. AD1849K Timing Parameters The AD1849K comes out of reset with the default conditions specified in “Control Register Defaults.” It will be in the mode specified by the D/C pin. If in Control Mode, the SoundPort Codec can be configured by the host for operation.
  • Page 19 CODEC STARTUP, MODES, AND TRANSITIONS Reset and Power Down RESET The AD1849K Stereo Codec can be reset by either of two closely related digital input signals, RESET and Power Down Figure 9. AD1849K Daisy-Chaining (PDN). RESET is active LO and PDN is active HI. Asserting PDN is equivalent to asserting RESET with two exceptions.
  • Page 20 The Codec initializes its Data Mode Control Registers to the input Control Word. defaults identified above, which among other actions, mutes all In the first frame of Control Mode, the AD1849K will output a audio outputs. Control Word that reflects the control register values operative First DCB Interlock during the most recent Data Mode operation.
  • Page 21 SoundPort is a +5 V only powered device. Line level voltage will remain inactive until D/C goes HI or RESET and or PDN swings for the AD1849K are defined to be 1 V rms for ADC are asserted. input and 0.707 V rms for DAC output. Thus, 2 V rms input...
  • Page 22 An external passive antialias filter is required. If line-level inputs A circuit for headphone drive is illustrated in Figure 14. Drive is are already at the 1 V rms levels expected by the AD1849K, the supplied by +5 V operational amps. The circuit shown ac resistors in parallel with the 560 pF capacitors should be couples the headphones to the line output.
  • Page 23 Attention should be paid to providing low jitter external input cost of some distortion. When driving speakers much less than clocks. 48 Ω, a power amp should be used. The AD1849K can drive speakers of 32 Ω or greater. CIN2...
  • Page 24 SDTX be located directly above the digital ground plane for the best isolation. The digital ground and analog grounds should be tied together in the vicinity of the AD1849K. Other schemes may RESET RESET also yield satisfactory results.
  • Page 25 AD1849K • Pin 38 (PLCC) and Pin 32 (TQFP) on the AD1849K is used CS4215 COMPATIBILITY The Analog Devices AD1849K SoundPort Stereo Codec is pin- as a digital power supply. On the CS4215, this pin is a “no compatible with the CS4215. These chips were independently connect.”...
  • Page 26 0.58 0.60 SAMPLE FREQUENCY (F SAMPLE FREQUENCY (F Figure 25. AD1849K Analog-to-Digital Frequency Response Figure 27. AD1849K Digital-to-Analog Frequency Response – – Transition Band (Full-Scale Line-Level Inputs, 0 dB Gain) Transition Band (Full-Scale Inputs, 0 dB Attenuation) –26– REV. 0...
  • Page 27 PIN OUT ........6 AD1849K PIN DESCRIPTION ..... 7 FUNCTIONAL DESCRIPTION .

  • Page 28: Outline Dimensions

    AD1849K OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Leaded Chip Carrier (PLCC) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.048 (1.21) 0.025 (0.63) 0.042 (1.07) 0.020 (0.50) R 0.042 (1.07) 0.015 (0.38) 0.048 (1.21) 0.042 (1.07) PIN 1 IDENTIFIER 0.021 (0.53)

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