Texas Instruments TLV320DAC3203 Reference Manual
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Texas Instruments TLV320DAC3203 Reference Manual

Texas Instruments TLV320DAC3203 Reference Manual

Stereo audio codec
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TLV320DAC3203 Applications
Reference Guide
Literature Number: SLAU434
May 2012

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Summary of Contents for Texas Instruments TLV320DAC3203

  • Page 1 TLV320DAC3203 Applications Reference Guide Literature Number: SLAU434 May 2012...

  • Page 2: Table Of Contents

    2.9.1 System Level Considerations ......................2.10 Reference Voltage ....................2.11 Device Special Functions ......................2.11.1 Interrupts ......................Device Initialization ........................Reset ................... Device Startup Lockout Times Contents SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 3 Page 0 / Register 42: Sticky Flag Register 1 - 0x00 / 0x2A .......... 5.2.40 Page 0 / Register 43: Interrupt Flag Register 1 - 0x00 / 0x2B SLAU434 – May 2012 Contents Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 4 Page 1 / Register 14-15: Reserved Register - 0x01 / 0x0E-0x0F ......5.3.13 Page 1 / Register 16: HPL Driver Gain Setting Register - 0x01 / 0x10 Contents SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 5 Page 44 / Register 0: Page Select Register - 0x2C / 0x00 ....5.10.2 Page 44 / Register 1: DAC Adaptive Filter Configuration Register - 0x2C / 0x01 SLAU434 – May 2012 Contents Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 6 Page 63 / Register 76-127: Reserved - 0x3F / 0x4C-0x7F ....................5.16 ADC Coefficients A+B ..................5.17 ADC Coefficient Default Values ....................5.18 DAC Coefficients A+B ..................5.19 DAC Coefficient Default Values Contents SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 7 2-43. Timing Diagram for DSP Mode with offset = 0 and bit clock inverted ..................2-44. Audio Serial Interface Multiplexing ....................2-45. Clock Distribution Tree SLAU434 – May 2012 List of Figures Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 8 2-48. I C Write ........................2-49. I C Read ................. 2-50. SPI Timing Diagram for Register Write ................. 2-51. SPI Timing Diagram for Register Read List of Figures SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 9 2-18. DAC Interpolation Filter C, Specification ..................2-19. DRC HPF and LPF Coefficients ..................2-20. CODEC CLKIN Clock Dividers ..............2-21. Maximum TLV320DAC3203 Clock Frequencies ..................... 2-22. PLL_CLK Frequency Range ..................... 2-23. PLL Example Configurations ...................... 2-24. SPI Command Word ..............

  • Page 10: Tlv320Dac3203 Overview

    5: Register Map and Descriptions WCSPPackage The TLV320DAC3203 (sometimes referred to as the DAC3203) is a flexible, low-power, low-voltage stereo audio codec with programmable outputs, PowerTune capabilities, fixed predefined and parameterizable signal processing blocks, integrated PLL, integrated LDO and flexible digital interfaces.

  • Page 11: Typical Circuit Configuration

    With PowerTune the TLV320DAC3203 can address both cases. The voltage supply range for the TLV320DAC3203 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, a low-dropout regulator (LDO) is integrated to generate the appropriate analog supply from input voltages ranging from 1.8V to 3.6V.

  • Page 12: Tlv320Dac3203 Application

    E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if GPIO/MFP5 has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time) TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 13 Secondary I S WCLK in Secondary I S DIN Secondary I S DOUT Secondary I S BCLK OUT Secondary I S WCLK OUT Aux Clock Output SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 14: Register Settings For Multifunction Pins

    S ADC word clock input D5-D2=0001 Secondary I S DIN on D2-D1=01 on GPIO/MFP5 Page 0 / Register 31, Bits SCLK/MFP3 Page 0 / Register 31, Bit D2-D1=00 D0=1 TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 15: Analog Audio I/O

    INT1 output on Page 0 / Register 52, Bits GPIO/MFP5 D5-D2=0101 Analog Audio I/O The analog I/O path of the TLV320DAC3203 offers a variety of options for signal conditioning and routing: • 2 headphone amplifier outputs • Analog gain setting •...

  • Page 16: Headphone Output

    If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute. TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 17: Conceptual Circuit For Pop-Free Power-Up

    T, such that at the end of the slow power-on period, the voltage on V is very close to the common-mode voltage. The TLV320DAC3203 allows the time T to be adjusted to allow for a wide range of R and C by programming Page 1, Register 20, Bits D5-D2).
  • Page 18 In the differential load configuration for HPL and HPR, it is recommended to not use the output driver MUTE feature, because a pop may result. TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 19: Low Power Mono Dac To Differential Headphone

    2.2.2.3 Headphone Amplifier Class-D Mode By default the headphone amplifiers in the TLV320DAC3203 work in Class-AB mode. By writing to Page 1, Register 3, Bits D7-D6) for the left headphone amplifier, and Page 1, Register 4, Bits D7-D6) with value 11, the headphone amplifiers enter a Class-D mode of operation.

  • Page 20: Configuration For Using Headphone Amplifier In Class-D Mode

    Class AB mode amplifier must be turned off. For powering down the headphone amplifiers, the DAC should first be muted. Section 4.3 for an example setup script enabling Class-D mode. TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 21: Digital Microphone Input/Decimation Filter

    The digital microphone input path of the TLV320DAC3203 features a large set of options for signal conditioning as well as signal routing: •...

  • Page 22: Digital Volume Control

    2.3.2 Digital Volume Control The TLV320DAC3203 also has a digital volume-control block with a range from -12dB to +20dB in steps of 0.5dB. It is set by programming Page 0, Register 83 and 84 respectively for left and right channels.

  • Page 23: Processing Blocks

    Processing Blocks The TLV320DAC3203 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied.

  • Page 24: Signal Chain For Prb_R1 And Prb_R4

    IIR, Filter B From CIC Order To Audio Filter B ´ Filter Interface From Digital Vol. Ctrl Figure 2-11. Signal Chain for PRB_R7 and PRB_R10 TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 25: Signal Chain For Prb_R8 And Prb_R11

    IIR, Filter C 1 st Order From CIC To Audio Filter C ´ Filter Interface From Digital Vol. Ctrl Figure 2-15. Signal Chain for PRB_R14 and PRB_R17 SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 26: Signal For Prb_R15 And Prb_R18

    IIR, Filter C From CIC Order To Audio Filter C 25-Tap FIR ´ Filter Interface From Digital Vol. Ctrl Figure 2-16. Signal for PRB_R15 and PRB_R18 TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 27: First-Order Iir Filter Coefficients

    C4 (Pg 8,Reg 24,25,26) C36 (Pg 9,Reg 32,33,34) Order IIR C5 (Pg 8,Reg 28,29,30) C37 (Pg 9,Reg 36,37,38) C6 (Pg 8,Reg 32,33,34) C39 (Pg 9,Reg 40,41,42) SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 28: Biquad Filter Coefficients

    C61 (Pg 10, Reg 12,13,14) C30 (Pg 9, Reg 8,9,10) C62 (Pg 10, Reg 16,17,18) C31 (Pg 9, Reg 12,13,14) C63 (Pg 10, Reg 20,21,22) TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 29: Fir Filter Coefficients

    C61 (Pg 10, Reg 12,13,14) Fir23 C30 (Pg 9, Reg 8,9,10) C62 (Pg 10, Reg 16,17,18) Fir24 C31 (Pg 9, Reg 12,13,14) C63 (Pg 10, Reg 20,21,22) SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 30: Decimation Filter A, Frequency Response

    2.3.3.1.3 Decimation Filter The TLV320DAC3203 offers 3 different types of decimation filters. The integrated digital decimation filter removes high-frequency content and down samples the audio data from an initial sampling rate of AOSR*Fs to the final output sampling rate of Fs. The decimation filtering is achieved using a higher-order CIC filter followed by linear-phase FIR filters.

  • Page 31: Decimation Filter B, Frequency Response

    (Red line corresponds to –44 dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 Frequency Normalized to f G014 Figure 2-18. Decimation Filter B, Frequency Response SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 32: Decimation Filter C, Frequency Response

    ) are passed. The audio serial interface rounds the data to the required word length of the interface before converting to serial data as per the different modes for audio serial interface. TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 33: Micbias Voltage Control

    AVdd LDOIN 2.3.3.2.2 Channel-to-Channel Phase Adjustment The TLV320DAC3203 has a built-in feature to fine-adjust the phase between the stereo ADC record signals. The phase compensation is particularly helpful to adjust delays when using dual microphones for noise cancellation etc. This delay can be controlled in fine amounts in the following fashion.
  • Page 34 Step 1 The system clock source (master clock) and the targeted ADC sampling frequency must be identified. The oversampling ratio (OSR) of the TLV320DAC3203 must be configured to match the properties of the digital microphone. Based on the identified filter type and the required signal processing capabilities the appropriate...

  • Page 35: Dac

    Digital volume control with a range of -63.5 to +24dB • Mute function • Dynamic range compression (DRC) In addition to the standard set of DAC features the TLV320DAC3203 also offers the following special features: • Built in sine wave generation (beep generator) •...

  • Page 36: Processing Blocks - Details

    3 Biquads, Interpolation Filter A BiQuad BiQuad BiQuad Interp. ´ Filter A Modulator from Interface Digital Volume Ctrl Figure 2-20. Signal Chain for PRB_P1 and PRB_P4 TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 37: Signal Chain For Prb_P2, Prb_P5, Prb_P10 And Prb_P15

    4 Biquads, Interpolation Filter B BiQuad BiQuad BiQuad BiQuad Interp. ´ Filter B Modulator from Interface Digital Volume Ctrl Figure 2-25. Signal Chain for PRB_P9 and PRB_P14 SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 38: Signal Chain For Prb_P18 And Prb_P21

    Ctrl Biquad Biquad – From – Biquad Biquad Interp. Right- ´ Filter A Channel Modulator Interface Digital Volume Ctrl Figure 2-28. Signal Chain for PRB_P23 TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 39: User Programmable Filters

    Depending on the selected processing block, different types and orders of digital filtering are available. Up to 6 biquad sections are available for specific processing blocks. SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 40: Dac Iir Filter Coefficients

    C15 (Page 44 / Registers 68,69,70) C47 (Page 45 / Registers 76,77,78) BIQUAD D C16 (Page 44 / Registers 72,73,74) C48 (Page 45 / Registers 80,81,82) TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 41 -1.0 to +1.0. A value of -1.0 corresponds to 0x7FFFFF in DAC coefficient C32 (Page 45 / Register 16,17 and 18). A value of 1.0 corresponds to 0x800000 in coefficient C32. SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 42: Interpolation Filters

    Table 2-17. DAC Interpolation Filter B, Specification Parameter Condition Value (Typical) Units Filter Gain Pass Band 0 … 0.45Fs ±0.015 Filter Gain Stop Band 0.55Fs… 3.45Fs –58 Filter Group Delay 18/Fs TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 43: Channel Interpolation Filter B, Frequency Response

    Table 2-18. DAC Interpolation Filter C, Specification Parameter Condition Value (Typical) Units Filter Gain Pass Band 0 … 0.35Fs ±0.03 Filter Gain Stop Band 0.60Fs… 1.4Fs –43 Filter Group Delay 13/Fs SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 44: Dac Gain Setting

    During soft-stepping the value of the actual applied gain would differ from the programmed gain in register. The TLV320DAC3203 gives a feedback to the user in form of register readable flag to indicate that soft-stepping is currently in progress. The flags for left and right channels can be read back by reading Page 0, Reg 38, Bits D4) and D(0) respectively.
  • Page 45 To minimize audible artifacts, it is recommended to set the DRC Hold time to 0 through programming Page 0, Register 69, Bits D6-D3) = 0000. SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 46 30 34 7F AB 00 00 80 55 00 00 7F 56 00 00 #DRC HPF w 30 40 00 11 00 00 00 11 00 00 7F DE 00 00 #DRC LPF TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 47: Dac Special Functions

    When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed for either read or write. However the TLV320DAC3203 offers an adaptive filter mode as well. Setting Register Page 44,Reg 1, Bit D2=1 will turn on double buffering of the coefficients. In this mode, filter coefficients can be updated through the host, and activated without stopping and restarting the DAC.

  • Page 48: Dac Setup

    PRB_Px, DOSR, NDAC, MDAC, input and output common-mode values If the PLL is used, the PLL parameters P, J, D and R are determined as well. TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 49: Powertune

    Unmute digital volume control PowerTune The TLV320DAC3203 features PowerTune, a mechanism to balance power-versus-performance trade- offs at the time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application.
  • Page 50 In fact, the numerous processing blocks have been implemented to offer a choice between power-optimization and configurations with more signal-processing resources. TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 51: Dac Power Consumption

    Alternative processing blocks: Processing Block Filter Est. Power Change (mW) PRB_P1 PRB_P2 +3.1 PRB_P3 +1.6 PRB_P7 –1.6 PRB_P9 PRB_P10 +1.6 PRB_P11 –0.8 PRB_P23 PRB_P24 +3.1 PRB_P25 +3.1 SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 52 Reduced 0dB full-scale swing can be compensated by applying appropriate gain in the output drivers see . Measured data using PRB_P13. Calculated data for PRB_P12. Alternative processing blocks: TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 53 Reduced 0dB full-scale swing can be compensated by applying appropriate gain in the output drivers see . Alternative processing blocks: Processing Block Filter Est. Power Change (mW) PRB_P1 +0.3 PRB_P2 +0.8 PRB_P3 +0.5 SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 54 Reduced 0dB full-scale swing can be compensated by applying appropriate gain in the output drivers see . Alternative processing blocks: Processing Block Filter Est. Power Change (mW) PRB_P5 +0.3 PRB_P6 +0.3 PRB_P12 –0.1 TLV320DAC3203 Application SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 55 Reduced 0dB full-scale swing can be compensated by applying appropriate gain in the output drivers see . Alternative processing blocks: Processing Block Filter Est. Power Change (mW) PRB_P18 +9.3 PRB_P19 +3.1 SLAU434 – May 2012 TLV320DAC3203 Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 56: Audio Digital I/O Interface

    TLV320DAC3203s may share the same audio bus. The TLV320DAC3203 also includes a feature to offset the position of start of data transfer with respect to the word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0, Register 28.

  • Page 57: Right Justified Mode

    2.6.1 Right Justified Mode The Audio Interface of the TLV320DAC3203 can be put into Right Justified Mode by programming Page 0, Register 27, D(7:6) = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock.

  • Page 58: Left Justified Mode

    2.6.2 Left Justified Mode The Audio Interface of the TLV320DAC3203 can be put into Left Justified Mode by programming Page 0, Register 27, D(7:6) = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock.

  • Page 59: S Mode

    2.6.3 I S Mode The Audio Interface of the TLV320DAC3203 can be put into I S Mode by programming Page 0, Register 27, D(7:6) = to 00. In I S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock.

  • Page 60: Dsp Mode

    2.6.4 DSP Mode The Audio Interface of the TLV320DAC3203 can be put into DSP Mode by programming Page 0, Register 27, D(7:6) = 01. In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data.

  • Page 61: Secondary I

    2.6.5 Secondary I The audio serial interface on the TLV320DAC3203 has an extensive IO control to allow communication with two independent processors for audio data. Each processor can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections.

  • Page 62: Clock Generation And Pll

    Clock Generation and PLL The TLV320DAC3203 supports a wide range of options for generating clocks for the DAC as well as interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can be provided on a variety of device pins such as MCLK, BCLK, or GPIO pins.

  • Page 63: Bclk Output Options

    In general, all the root clock dividers should be powered down only after the child clock dividers have been powered down for proper operation. The TLV320DAC3203 also has options for routing some of the internal clocks to the output pins of the device to be used as general purpose clocks in the system. The feature is shown in Figure 2-46.

  • Page 64: General Purpose Clock Output Options

    Clock Generation and PLL www.ti.com In the mode when TLV320DAC3203 is configured to drive the BCLK pin (Page 0, Register 27, D3=’1’) it can be driven as divided value of BDIV_CLKIN. The division value can be programmed in Page 0, Register 30, D(6:0) from 1 to 128.

  • Page 65: Pll

    Clock Generation and PLL 2.7.1 PLL The TLV320DAC3203 has an on-chip PLL to generate the clock frequency for the audio ADC, DAC, and Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system.

  • Page 66: Control Interfaces

    Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I C devices can act as masters or slaves, but the TLV320DAC3203 can only act as a slave device.
  • Page 67 START condition is issued while the bus is active, it is called a repeated START condition. The TLV320DAC3203 can also respond to and acknowledge a General Call, which consists of the master issuing a command with a slave address byte of 00H. This feature is disabled by default, but can be enabled via Page 0, Register 34, Bit D(5).

  • Page 68: Spi Digital Interface

    8 clocks the data of the next incremental register. 2.8.2 SPI Digital Interface In the SPI control mode, the TLV320DAC3203 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO, SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0).

  • Page 69: Power Supply

    In order to retain settings in the device, the DVdd voltage and either internally or externally the AVdd voltage also must be maintained. In this case the TLV320DAC3203 exhibits shutdown currents of below 1.5μA. 2.9.1.1 Supply from single voltage rail (1.8V).

  • Page 70: Reference Voltage

    To put the device in standby mode, both external voltages (AVdd and DVdd) and the reference block inside the TLV320DAC3203 must stay on (Page 1 / Register 123, D(2:0) = 101), all other blocks should be powered down. This results in standby current of approximately 100μA from the AVdd supply.

  • Page 71: Device Special Functions

    2.11 Device Special Functions 2.11.1 Interrupts Some specific events in the TLV320DAC3203 which may require host processor intervention, can be used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TLV320DAC3203 has two defined interrupts; INT1 and INT2 that can be configured by programming Page 0, Register 48 and 49.

  • Page 72: Device Initialization

    ........................... Topic Page ....................... Reset ................Device Startup Lockout Times ................Analog and Reference Startup ...................... PLL Startup ..............Setting Device Common Mode Voltage Device Initialization SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 73: Reset

    Setting Device Common Mode Voltage The TLV320DAC3203 allows the user to set the common mode voltage for analog inputs to 0.75V or 0.9V by programming Page 1, Register 10, D(6). The input common-mode voltage of 0.9V works best when the analog supply voltage is centered around 1.8V or above, and offers the highest possible performance.

  • Page 74: Write

    Chapter 4 SLAU434 – May 2012 Example Setups The following example setups can be taken directly for the TLV320DAC3203 EVM setup. The # marks a comment line, w marks an I C write command followed by the device address, the I register address and the value.

  • Page 75: Stereo Dac Playback With 48Ksps Sample Rate And Low Power Mode

    #----------- Unmute the DAC digital volume control w 30 40 00 DAC Playback with 48ksps Sample Rate through Class-D Headphone Amplifiers Assumption: MCLK = 24.576MHz, Slave I2S SLAU434 – May 2012 Example Setups Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 76 #----------- Select page 0 w 30 00 00 #----------- Mute the DAC digital volume control w 30 40 0d #----------- Power down the DAC w 30 3f c0 Example Setups SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 77: Adc Record Through Digital Microphone With 44.1Ksps Sample Rate

    #----------- Power up and set MDAC divider = 2 w 30 0c 82 #----------- Select page 1 w 30 00 01 #----------- Disable internal crude AVdd in presence of external AVdd supply SLAU434 – May 2012 Example Setups Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 78 #----------- If not polling wait for 8ms #----------- Select page 0 w 30 00 00 #----------- Unmute left DAC digital volume control w 30 40 04 Example Setups SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 79: Summary Of Register Map

    SLAU434 – May 2012 Register Map The TLV320DAC3203 contains 108 pages of 8-bit registers, each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device. Page 0 is the default home page after hardware reset.

  • Page 80: Page 0 / Register 3: Reserved Register - 0X00 / 0X03

    Page 0 / Register 7: Clock Setting Register 4, PLL D Values (MSB) - 0x00 / 0x07 READ/ RESET DESCRIPTION WRITE VALUE D7-D6 Reserved. Write only default values any value other than default Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 81: Page 0 / Register 8: Clock Setting Register 5, Pll D Values (Lsb) - 0X00 / 0X08

    000 0000: MDAC=128 000 0001: MDAC=1 000 0010: MDAC=2 … 111 1110: MDAC=126 111 1111: MDAC=127 Note: Please check the clock frequency requirements in the Overview section SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 82: Page 0 / Register 13: Dac Osr Setting Register 1, Msb Value - 0X00 / 0X0D

    Reserved. Write only default values 5.2.19 Page 0 / Register 19: Reserved Register - 0x00 / 0x13 READ/ RESET DESCRIPTION WRITE VALUE D7-D0 0000 0001 Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 83: Page 0 / Register 20: Adc Oversampling (Aosr) Register - 0X00 / 0X14

    111 1110: CLKOUT M divider = 126 111 1111: CLKOUT M divider = 127 Note: Please check the clock frequency requirements in the application overview section SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 84: Page 0 / Register 27: Audio Interface Setting Register 1 - 0X00 / 0X1B

    5.2.30 Page 0 / Register 30: Clock Setting Register 10, BCLK N Divider - 0x00 / 0x1E READ/ RESET DESCRIPTION WRITE VALUE BCLK N Divider Power Control 0: BCLK N divider powered down 1: BCLK N divider powered up Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 85: Page 0 / Register 32: Audio Interface Setting Register 5 - 0X00 / 0X20

    1: BCLK Output = Secondary Bit Clock Input Secondary Bit Clock Output Control 0: Secondary Bit Clock = BCLK input 1: Secondary Bit Clock = Generated Primary Bit Clock SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 86: Page 0 / Register 34: Digital Interface Misc. Setting Register - 0X00 / 0X22

    1: HPR Powered Up Reserved. 5.2.37 Page 0 / Register 38: DAC Flag Register 2 - 0x00 / 0x26 READ/ RESET DESCRIPTION WRITE VALUE D7-D5 Reserved. Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 87: Page 0 / Register 39-41: Reserved Register - 0X00 / 0X27-0X29

    1: Button Press detected (will be cleared when the register is read) Headset Insertion/Removal Detect Flag 0: Insertion/Removal event not detected 1: Insertion/Removal event detected (will be cleared when the register is read) SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 88: Page 0 / Register 45: Reserved Register - 0X00 / 0X2D

    1: DAC DRC Signal Power exceeding Signal Threshold for either of Left or Right Channel will generate a INT1 interrupt. Read Page-0, Register-44 to distinguish between Left or Right Channel Reserved. Write only default value Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 89: Page 0 / Register 49: Int2 Interrupt Control Register - 0X00 / 0X31

    5.2.48 Page 0 / Register 52: GPIO/MFP5 Control Register (** Availble only for WCSP Package) - 0x00 / 0x34 READ/ RESET DESCRIPTION WRITE VALUE D7-D6 Reserved. Write only default values SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 90: Page 0 / Register 53: Mfp2 Function Control Register - 0X00 / 0X35

    5.2.51 Page 0 / Register 55: MISO/MFP4 Function Control Register - 0x00 / 0x37 READ/ RESET DESCRIPTION WRITE VALUE D7-D5 Reserved. Write only default values Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 91: Page 0 / Register 56: Sclk/Mfp3 Function Control Register - 0X00 / 0X38

    Note; Please check the overview section for description of the Signal Processing Blocks 5.2.55 Page 0 / Register 61: Reserved Register - 0x00 / 0x3D READ/ RESET DESCRIPTION WRITE VALUE D7-D5 Reserved. Write only default values SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 92: Page 0 / Register 62: Reserved Register - 0X00 / 0X3E

    111: DAC is auto muted if input data is DC for more than 6400 consecutive inputs Left DAC Channel Mute Control 0: Left DAC Channel not muted 1: Left DAC Channel muted Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 93: Page 0 / Register 65: Left Dac Channel Digital Volume Control Register - 0X00 / 0X41

    011: Debounce Time = 128ms 100: Debounce Time = 256ms 101: Debounce Time = 512ms 110-111: Reserved. Do not use Note: All times are typical values SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 94: Page 0 / Register 68: Drc Control Register 1 - 0X00 / 0X44

    0010: DRC Attack Rae = 1.0dB per DAC Word Clock … 1110: DRC Attack Rate = 2.4414e-4dB per DAC Word Clock 1111: DRC Attack Rate = 1.2207e-4dB per DAC Word Clock Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 95: Page 0 / Register 71: Beep Generator Register 1 - 0X00 / 0X47

    5.2.69 Page 0 / Register 75: Beep Generator Register 5 - 0x00 / 0x4B READ/ RESET DESCRIPTION WRITE VALUE D7-D0 1110 1110 Programmed value is Beep Sample Length(7:0) SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 96: Page 0 / Register 76: Beep Generator Register 6 - 0X00 / 0X4C

    01: ADC Volume Control changes by 1 gain step per two ADC Word Clocks 10: ADC Volume Control Soft-Stepping disabled 11: Reserved. Do not use Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 97: Page 0 / Register 82: Reserved Register - 0X00 / 0X52

    010 0110: Left ADC Channel Volume = 19.0dB 010 0111: Left ADC Channel Volume = 19.5dB 010 1000: Left ADC Channel Volume = 20.0dB 010 1001-111 1111: Reserved. Do not use SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 98: Page 0 / Register 85: Adc Phase Adjust Register - 0X00 / 0X55

    0: Over Current not detected for AVDD LDO 1: Over Current detected for AVDD LDO AVDD LDO Power Control 0: AVDD LDO Powered down 1: AVDD LDO Powered up Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 99: Page 1 / Register 3: Playback Configuration Register 1 - 0X01 / 0X03

    0: When Page-1, Reg-10, D1=1, then LDOIN input range is 1.5V to 1.95V 1: When Page-1, Reg-10, D1=1, then LDOIN input range is 1.8V to 3.6V SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 100: Page 1 / Register 11: Over Current Protection Configuration Register - 0X01 / 0X0B

    5.3.13 Page 1 / Register 16: HPL Driver Gain Setting Register - 0x01 / 0x10 READ/ RESET DESCRIPTION WRITE VALUE Reserved. Write only default value. 0: HPL driver is not muted 1: HPL driver is muted Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 101: Page 1 / Register 17: Hpr Driver Gain Setting Register - 0X01 / 0X11

    00: Soft routing step time is 0ms 01: Soft routing step time is 50ms 10: Soft routing step time is 100ms 11: Soft routing step time is 200ms SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 102: Page 1 / Register 21: Reserved Register - 0X01 / 0X15

    5.3.18 Page 1 / Register 22: INL to HPL Volume Control Register - 0x01 / 0x16 READ/ RESET DESCRIPTION WRITE VALUE Reserved. Write only default value. Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 103 011 1101: Volume Control = -32.1dB 011 1110: Volume Control = -32.6dB 011 1111: Volume Control = -33.1dB 100 0000: Volume Control = -33.6dB 100 0001: Volume Control = -34.1dB SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 104: Page 1 / Register 23: Inr To Hpr Volume Control Register - 0X01 / 0X17

    5.3.19 Page 1 / Register 23: INR to HPR Volume Control Register - 0x01 / 0x17 READ/ RESET DESCRIPTION WRITE VALUE Reserved. Write only default value Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 105 011 1101: Volume Control = -32.1dB 011 1110: Volume Control = -32.6dB 011 1111: Volume Control = -33.1dB 100 0000: Volume Control = -33.6dB 100 0001: Volume Control = -34.1dB SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 106: Page 1 / Register 24-50: Reserved Register - 0X01 / 0X18-0X32

    5.3.21 Page 1 / Register 51: MICBIAS Configuration Register - 0x01 / 0x33 READ/ RESET DESCRIPTION WRITE VALUE Reserved. Write only default value. 0: MICBIAS powered down 1: MICBIAS powered up Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 107: Page 1 / Register 52-57: Reserved Register - 0X01 / 0X34-0X39

    5.3.26 Page 1 / Register 64-70: Reserved Register - 0x01 / 0x40-0x46 READ/ RESET DESCRIPTION WRITE VALUE D7-D0 0000 0000 Reserved. Write only default values SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 108: Page 1 / Register 71: Analog Input Quick Charging Configuration Register - 0X01 / 0X47

    5.3.32 Page 1 / Register 126-127: Reserved Register - 0x01 / 0x7E-0x7F READ/ RESET DESCRIPTION WRITE VALUE D7-D0 0000 0000 Reserved. Write only default values Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 109: Page 8 Registers

    Refer Table "Summary of Memory Map" for details. 5.5.2 Page 9 / Register 1-7: Reserved - 0x09 / 0x01-0x07 READ/ RESET DESCRIPTION WRITE VALUE D7-D0 0000 0000 Reserved. Write only default values SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 110: Page 9 / Register 8-15: Adc Coefficients Buffer-A C(30:31) - 0X09 / 0X08-0X0F

    D7-D0 0000 0000 Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 111: Page 26 / Register 1-7: Reserved. - 0X1A / 0X01-0X07

    D7-D0 0000 0000 Page Select Register 0-255: Selects the Register Page for next read or write command. Refer Table "Summary of Memory Map" for details. SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 112: Page 28 / Register 1-7: Reserved. - 0X1C / 0X01-0X07

    Buffer A Map" for details When Page-44, Reg-01d, D2='0' (Adaptive filtering disabled) the read write access to these registers is allowed only when DAC channel is powered down Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 113: Page 45 Registers

    24-bit coefficients DAC Coefficient Buffer-A. Refer to Table "DAC Coefficient Buffer A Map" for details When Page-44, Reg-01d, D2='0' (Adaptive filtering disabled) the read write access to these registers is allowed only when DAC channel is powered down SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 114: Page 46 / Register 20-27: Reserved - 0X2E / 0X14-0X1B

    Refer Table "Summary of Memory Map" for details. 5.14.2 Page 63 / Register 1-7: Reserved. - 0x3F / 0x01-0x07 READ/ RESET DESCRIPTION WRITE VALUE D7-D0 0000 0000 Reserved. Write only default values Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 115: Page 63 / Register 8-11: Dac Coefficients Buffer-B C(30) - 0X3F / 0X08-0X0B

    24-bit coefficients of DAC Coefficient Buffer-B. Refer Table "DAC Coefficient Buffer B Map" for details When Page-44, Reg-01d, D2='0' (Adaptive filtering disabled) the read write access to these registers is allowed only when DAC channel is powered down SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 116: Adc Coefficient Buffer-A Map

    Table 5-4. Default values of ADC Coefficients in Buffers A and B ADC Buffer- Default Value at reset Coefficients 00000000H 01170000H 01170000H 7DD30000H 7FFFFF00H C5,C6 00000000H 7FFFFF00H C8,..,C11 00000000H Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 117: Dac Coefficient Buffer-A Map

    Base Register Base Register + 0 Base Register + 1 Base Register + 2 Base Register + 3 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Coef(23:16) Coef(15:8) Coef(7:0) Reserved. SLAU434 – May 2012 Register Map Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...

  • Page 118: Default Values Of Dac Coefficients In Buffers A And B

    00000000H 7FFFFF00H C44,..,C47 00000000H 7FFFFF00H C49,..,C52 00000000H 7FFFFF00H C54,..,C57 00000000H 7FFFFF00H C59,..,C64 00000000H 7FFFFF00H C66,C67 00000000H 7FFFFF00H C69,C70 00000000H 7FF70000H 10090000H 7FEF0000H C74,C75 00110000H 7FDE0000H Register Map SLAU434 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
  • Page 119 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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