Commodore Computers 1581 Service Manual page 9

1581 SERVICE MANUAL
^ 6502 SIGNAL DESCRIPTION
Clocks (O19 02) - The 651X requires a two phase non-overlapping clock that runs at the Vcc voltage level.
The 650X clocks are supplied with an internal clock generator. The frequency of these clocks is externally
controlled.
Address Bus (A0-A15) — These outputs are TTL compatible, capable of driving one standard TTL load and 130 pf.
Data Bus (D0-D7) — Eight pins are used for the data bus. This is a bi-directional bus, transferring data to and
from the device and peripherals. The outputs are tri-state buffers capable of driving one standard TTL load and
130 pf.
Data Bus Enable (DBE) — This TTL compatible input allows external control of the tri-state data output buffers
and will enable the microprocessor bus driver when in the high state. In normal operation, DBE would be driven
by the phase two (02) clock, thus allowing data output from microprocessor only during 02. During the read
cycle, the data bus drivers are internally disabled, becoming essentially an open circuit. To disable data bus
drivers externally, DBE should be held low.
Ready (RDY) — This input signal allows the user to single cycle the microprocessor on all cycles except write
cycles. A negative transition to the low state during, or coincident with, phase one (O1) and up to 100ns after
phase two (02) will halt the microprocessor with the output address lines reflecting the current address being
fetched. This condition will remain through a subsequent phase two (02) in which the Ready signal is low. This
feature allows microprocessor interfacing with low speed PROMS as well as fast (max. 2 cycle) Direct Memory
Access (DMA). If Ready is low during a write cycle, it is ignored until the following read operation.
Interrupt Request (IRQ) — This TTL level input requests that an interrupt sequence begin within the
microprocessor. The microprocessor will complete the current instruction being executed before recognizing
the request. At that time, the interrupt mask bit in the Status Code Register will be examined. If the interrupt
mask flag is not set, the microprocessor will begin an interrupt sequence. The Program Counter and Processor
Status Register are stored in the stack. The microprocessor will then set the interrupt mask flag high so that
[) no further interrupts may occur. At the end of this cycle, the program counter low will be loaded from address
FFFE, and program counter high from location FFFF, therefore, transferring program control to the memory vec
tor located at these addresses. The RDY signal must be in high state for any interrupt to be recognized. A 3KQ
external resistor should be used for proper wire-OR operation.
Non-Maskable Interrupt (NMI) — A negative going edge on this input requests that a non-maskable interrupt
sequence be generated within the microprocessor. NMI is an unconditional interrupt. Following completion of
the current instruction, the sequence of operations defined for IRQ will be performed, regardless of the interrupt
mask flag status. The vector address loaded into the program counter, low and high, are locations FFFA and
FFFB respectively, thereby transferring program control to the memory vector located at these addresses. The
instructions loaded at these locations cause the microprocessor to branch to a non-maskable interrupt routine
in memory. NMI also requires an external 3KQ resistor to Vcc for proper wire-OR operations. Inputs IRQ and NMI
are hardware interrupt lines that are sampled during 02 (phase 2) and will begin the appropriate interrupt routine
on the O1 (phase 1) following the completion of the current instruction.
Set Overflow Flag (S.O.) — A NEGATIVE going edge on this input sets the overflow bit in the Status Code
Register. This signal is sampled on the trailing edge of d.
SYNC — This output line is provided to identify those cycles in which the microprocessor is doing an OP CODE
fetch. The SYNC line goes high during O1 of an OP CODE fetch and stays high for the remainder of that cycle.
If the RDY line is pulled low during the O1 clock pulse in which SYNC went high, the processor will stop in its
current state and will remain in the state until the RDY line goes high. In this manner, the SYNC signal can
be used to control RDY to cause single instruction execution.
Reset — This input is used to reset or start the microprocessor from a power down condition. During the time
that this line is held low, writing to or from the microprocessor is inhibited. When a positive edge is detected
on the input, the microprocessor will immediately begin the reset sequence. After a system initialization time
of six clock cycles, the mask interrupt flag will be set and the microprocessor will load the program counter
from the memory vector locations FFFC and FFFD. This is the start location for program control. After Vcc reaches
4.75 volts in a power up routine, reset must be held low for at least two clock cycles. At this time the R/W
/""""^ and (SYNC) signal will become valid. When the reset signal goes high following these two clock cycles, the
microprocessor will proceed with the normal reset procedure detailed above.