Kenwood KDS-100 Service Manual page 7

■ Address control circuit
The CPU operates in the single-chip mode using an inter-
nal ROM and RAM.
It communicates with the DSP through an external data
bus.
Since the CPU operates on 5V and the DSP and flash
ROM (IC13) operate on 3V, the address data bus is con-
nected through a 5V-3V level conversion IC (IC11, 11, 36,
37). (Figure 6)
IC10
Data bus
5V← →3V
IC11
5V→3V
IC6
CPU
IC36
5V→3V
IC37
5V→3V
Fig. 6
■ Real-time clock
The message transmission/reception time is controlled
by the dedicated real-time clock IC (IC2).
When the power supply is OFF, it is backed up by an in-
ternal secondary lithium battery (BA1).
■ System reset, RAM, real-time clock backup
The power supply voltage monitor IC (IC1) monitors
power supply voltage (8V). If the voltage falls, the PFO port
goes "LOW" level, the CPU PFint (INT0) port also goes
"LOW" level, and the CPU stops. If the 5V power supply
voltage (for the CPU, S-RAM, and real-time clock IC) drops,
the backup power supply for the S-RAM (IC12) and real-time
clock IC (IC2) is switched to the secondary lithium battery
(BA1).
When the power supply restores to its normal voltage,
the IC1 PF0 port goes "H" level and the CPU PFint (INT0)
port also goes "H" level. In addition, the RESET signal from
IC1 is sent to the CPU RESET port to initialize and start the
CPU.
CE is obtained by gating CE
OUT
(S-RAM CE) output. When the VCC is equal to or higher
than the threshold, CE tracks CE
OUT
VCC is lower than the threshold, CE
ure 7)
Note:
The backup lithium battery (BA1) is fully charged from the
empty state when the KDS-100 is turned on for about
150 hours.
CIRCUIT DESCRIPTION
S-RAM
IC23
DPS
IC13
Flash
ROM
(S-RAM CE) with CE
IN IN
(S-RAM CS1). If the
IN
goes "High". (Fig-
OUT
V
BATT
+
BA1
–
R250
V
CC
5V
CE
IN
CS1
+
–
4.65V
OSC IN
Reset &
watchdog
time base
OSC SEL
Watchdog
WATCHDOG
transition detector
INPUT (WDI)
POWER FAIL
1.3V
–
INPUT (PFI)
+
8V
R31 R32
■ Serial ports
The KDS-100 CPU has three serial ports. Two RS232C
level lines with two-channel RS232C driver (IC3) and two 5V
logic level serial control lines with two types of analog
switches (IC40, IC5) are controlled, selected and used.
TX0
33
PORT0
RX0
34
TX1
29
PORT1
RX1
30
IC6
1
2
IC40 (2/2)
Analog SW
TX2
28
PORT2
6
RX2 5
27
IC40 (2/2)
Analog SW
KDS-100
BATT ON
V
OUT
CE
OUT
LOW LINE
RESET
RESET
Reset
IC6 pin10
generator
RESET
WATCHDOG
Watchdog
OUTPUT (WDO)
timer
POWER FAIL
OUTPUT (PFO)
IC6 pin18
PFint (INT0)
Fig. 7
IC5
2
Y0
15
X0
TX0 or TX1
Y
12
RX0 or RX1
1
X
Y1
14
X1
2
Analog SW
IC3
11
14
ch1
12
13
10 7
ch2 9
8
RS232C Driver
Fig. 8
7