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4.3.9
Memory
The page memory is actually a 2048 byte memory.
Each byte consists of 9 bits: 7 for data, one for
protect, and one for blink. Of these 2048 bytes,
1920 are displayable. The program does not have
the capability of displaying or writing Into the
remaining 128. In order to write data into the
page memory from the receiver, the memory
address is muxed over to the cursor location
registers and the signal WRITE is generated. The
UART Is then reset and is capable of receiving
the next character. The page memory output
is sent to the character generator input buffer
at the proper time to generate the displayable
characters. The program has the capability of
shutting down the screen refresh for any given
operation to increase the program operating
time.
4.3.10
Character Generator
The Character Generator is a read-only memory
(ROM) that is addressed by the character (in
ASCII). The scan configuration and the charac
ter indicates the pattern desired on that scan,
-ive-bit dot patterns are generated which form
portion of a character. The output of the
character generator is applied to the parallel-
to-serial video shift register.
4.3.11
Video Shift Register
The paraliel-to-serial Video Shift Register is
^
loaded with data by the low-active signal, DPC8,
and is clocked by the main oscillator output. The
dots are shifted out, mixed with cursor Informa
tion, and blanking signals, and applied to the
monitor through the CONTRAST control as
video information^
4.3.12
Input/Output Operations UART (Receiver)
Data can be received by the B100 from one of
three sources; from the I/O interface into the
receive side of the UART or from the keyboard
through the transmit side of the UART to the
receive side of the UART.
The UART is driven by a clock generated inter
nally off the main counter chain. No separate
oscillator is required. A rotary switch located
4-11
on the back panel switches the clock rate for
operation from 75 to 19200 baud. The times 16
clock is then applied to the transmitter and re
ceiver of the UART.
The El A line receiver receives data at RS 232C
levels and gates them into the UART when the
B100 is on-line. Through the same gating, data
is brought.in from the transmit side of the UART.
The data is brought into the UART where it is
converted to parallel (seven bits) data.
4.3.13
UART (Transmit)
The keyboard data lines for bits 1 through 7 are
applied to the transmit input data lines along with
the seven BUS lines. Also coming from the key
board circuit is a load signal which triggers the
UART to initiate the transmission. As the UART
receives the character for transmission, it performs
the appropriate parity generation, provides one or
two stop bits, divides the XI6 clock to get the baud
rate, and transmits the character. The character is
applied through an EIA RS 232C interface to the
computer or modem. Also coming from the UART
is output data at a TTL level which is applied to
the receiver side of the UART through the previously
mentioned logic. The EIA interface includes a Data
Terminal Ready signal which indicates the status
of the B100 to the computer and a Request to Send
signal which indicates that the terminal has data to
send to the computer. The Clear-to-Send line coming
from the computer is monitored at the EIA RS 232C
interface levels. It is received by a line receiver which
converts it to TTL levels and applies it to the UART
clock control circuit to control transmission. An
optional times 8 clock (TTL levels) is available as
part of the interface. The BREAK key is on the key
board and enables a timer which holds the transmit
data line in a spacing condition for a predetermined
length of time.
4.3.14
Block Send Circuit
The Block Send feature allows the operator to com
pose a message on the terminal screen and then,
by depressing the SEND key, cause the terminal to
send the entire message to the computer at the selec
ted baud rate.
The sequence of operations is described in Figure 4-1.
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