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5 SERVICE SOFTWARE
5.1 THE LOW LEVEL MMC TEST
Scope
This test i s standard implemented in the boot software of
CD-RTOS. It doesn' t need a lot of hardware to run. When
debugging or servicing an MMC panel this test i s very use-
ful .
General
This test i s developed for service and low level hardware
debugging purposes only. It i s meant to be used with the
service pcb as described in TOOLS (please refer to section
3.5 SERVICE TOOLS). The test executed with the service
pcb i s called the "pcb low level test".
The test executed with the VT100 terminal i s called the
"terminal low level test". Since this service pcb display
has just 8 digits, only the most important information will
be displayed to the user. For the VT100 terminal this is
never a problem.
This test consists out of the following items:
a. Display header and release number.
b. VSC
c. ROM
d. NVRAM
e. DRAM
f. CDIC
g. SLAVE processor (68HC05)
5.1.1 Tools
In this test the service pcb acts as some kind of a ' m icro
terminal' . This means that the service pcb i s able to display
some alphabetical and numerical characters. Some charac-
ters because it uses 7-segment displays
The three keys available are:
TEST ; test all display !eds.
Yes ; Send an ASCII ' Y ' .
No
; Send an ASCII ' N ' .
The communication parameters are fixed at: 9600 baud
8 data bits
1 stopbit
no parity
The microcontroller is programmed with software available
at IMS CDI software group.
The circuit diagram i s on section 3.5.1.1
5.1.2 Testsquence
Tabl e 1 below shows all the steps of the testprogram and
what kind of tests are performed.
STEP
ACTION/TEST PERFORMED
00
VSC master/slave init
01
ROM
05
NVRAM
06
DRAM BANKO & BANK1
07
DRAM BANKO
08
DRAM BANK1
09
CDIC
10
SLAVE
11
CLOCK CALIBRATION
Table 1 : teststeps low level test
5.1.3 Low level test implementation
The low level test (short: lltest) i s implemented in the boot
part of the CD-RTOS software. The whole test occupies
about 10k of ROM memory and i s written in assembler.
PCS 61856
The test runs without the use of any external RAM. It only
uses internal CPU registers. As communication channel the
68070' s UART i s used. Before starting the normal player
boot the following sequence i s executed:
1.
Initialize the 68070' s UART : 9600 baud
1 startbit
8 databits
1 stopbit
no parity
no handshake
1
2. Clear the RXD buffer.
3. Wait 5 ms.
4. Read the RXD buffer.
5. If the character received was an ACK ($06) the start the
pcb lltest
The UART i s connected
to
1/0 port 2
5.1.4 How to start up the low level test
With service pcb
To startup the pcb low level testsoftware the next
sequence should be followed:
- Switch off the player.
- Connect service pcb to port 2 at the rear of the player.
- Switch on the player.
- The service pcb display should now show ' C Oi RLxx' .
(with xx the release number)
- The pcb lltest i s now ready to go.
With VT100 terminal
To startup the terminal low level testsoftware one should
follow the next sequence:
- Switch off the player.
- Connect the terminal to the 68070' s UART of the player.
- Switch on the player while pressing the SPACE-bar of
the terminal.
- The terminal should now show the title of the terminal
lltest.
5.1.5 PCB low level test
If the service pcb i s connected to port 2 the pcb low level
test i s executed after power on. In table 1 a survey i s given
for al l tests executed.
Display lltest release number:
When this lltest i s entered, first the release number of the
pcb lltest will be displayed.
Example: COi RLxx
(RL stands for RELEASE, xx stands for release x.x).
The lltest is now waiting for an action from the user. The
user should now press either the' Y ' or ' N ' button to con-
tinue the test.
STEP 0: VSC
STEP OA: VSC MASTER
display: OA
In this step some registers of the VSC MASTER are
initialized. These registers are :
DCR2 register(set to independant
DCR register (disable display)
CSR register (set DTACK delay and DRAM type)
STEP OB: VSC SLAVE
display: OB
In this step some registers of the VSC SLAVE are initialized.
These registers are:
DCR2 register(set to independant DCA)
DCR register (disable display)
CSR register (set DTACK delay and DRAM type)
STEP 1: ROM
In this step the contents of the ROM i s checked.
Following tests are done on the ROM:
1. Display release number of this ROM. (test A)
3. Check if the parity of the ROM i s OK. (test C)
Address range:
- The ROM chips used for this memory map are :
1 X 4Mbit.
On the MINI MMC the clock and calendar chip used i s
the SGS-Thomson MK48T08B. It is visible i n the
memory map.
Nr.of
UPPER
Bytes
- --
MAPPED ADDRESS
Words
LOWER
SPACE
512kB
UP&LO
00 0000 -07 FFFF
512kB
UP&LO
08 0000 -OF FFFF
512kB
UNDEF
10
0000 -
17
FFFF
512kB
UP&LO
18 0000 -
1F
FBFF
16B
LO
1F FC00-1F FFBF
16B*
UP&LO
1 F FFCO -1 F FFDF
16B*
UP&LO
1 F FFEO -1 F FFFF
4B
LO
20 0000 -20 7FFF
500kB
UNDEF
20 8000 -27 FFFF
64kB
LO
28 0000 -28 FFFF
460kB
UNDEF
28 0000 -2F FFFF
8kW
UP&LO
30 0000 -30 FFFF
910kB
UNDEF
31 0000 -3E FFFF
2B
LO
3F 0000 -3F 7FFF
8kB-8
UP
3F 8000 -3F FBFF
8B
UP
3F BFFO -3F FBFF
1kB
UNDEF
3F FCOO -3F FFFF
13MB
UNDEF
40 0000 -FF FFFF
UNMAPPED ADDRESS
SPACE
00 0000 -07 FFFF
08 0000 -OF FFFF
10 0000 -17 FFFF
18 0000 -1F FBFF
1F FC01 -1F FC1F
1 F FFCO -1 F FFDF
1 F FFEO -1 F FFFF
20 0001 -20 0007
20 8000 -27 FFFF
28 0001 -28 FFFF
28 0000 -2F FFFF
30 0000 -30 3FFE
31 0000 -3E FFFF
3F 0001 -3F 0003
3F 8000 -3F BFEE
3F BFFO -3F BFFE
3F FCOO -3F FFFF
40 0000 -FF FFFF
Tabl e of the memory map
(1)
The effective memory space for SYSTEM ROM is 512kB-1 k.
(2) The maximum available NVRAM space in this configuration i s 31 kByte.
(3) This part of the memory map should not be accessed. The VSC registers are mapped here.
(4) When used.
I..
Explanation of items in tables
Nbr. of Bytes/Words :
The total available bytes or words. Words in this case
means the part of the memory map is only accessable as a
word.
kB
B
B*
kW
= kilobytes
= bytes
=
bytes, but some addresses are only accessible
as words.
=
kilowords, only accessible as a word!
FUNCTION
DRAM BANK1
DRAM BANK2
RESERVED
SYSTEM ROM
DUART (4)
VCS REGS SLAVE
VSC REGS MASTER
SLAVE
FREE SPACE
FLOPPY (4)
FREE SPACE
COi
FREE SPACE
KILLME/DMAMEM
NVRAM (2)
CLOCK&CAL REGS
DO NOT ACCESS(3)
EXTENSION SPACE
UPPER -LOWER:
This column gives an indication of how the device i s ac-
cessible.
UP
=
only accessible as byte via the UPPER byte of
the databus.
(DATA8-DATA 15)
LO
=
only accessible as byte via the LOWER byte of
the databus.
(DATAO-DATA7)
UP&LO
=
accessible via LOWER as well as UPPER byte of
the databus.
(the device uses the complete databus.
UNDEF
=
not defined.
MAPPED ADDRESS SPACE:
This column gives the total address range where the device
described in FUNCTION i s accessible. In this range the
device can occu.r several times.
UNMAPPED ADDRESS SPACE:
Analogous as mapped address space, only the device can
occur only ONE time.
FUNCTION: This column describes the device or register
STEP 1: ROM 10
STEP 1A: ID AND RELEASE NUMBER DISPLAY
display: 1A
IDxxRLyy
In this step the release number of this ROM is displayed
for a moment.
(ID stands for IDentification, xx i s the id number.
RL stands for RELEASE, yy stands for y.y)
STEP 1 C: CHECKSUM
display: 1C
In this step the checksum of this ROM i s calculated as
described in" how is the checksum calculated ". If the
checksum is not ok an error will be displayed.
display: 1 C Er05
STEP
5: NVRAM
The nvram test i s a non destructive test. This means that
the original nvram contents i s restored again.
Address range: Full nvram address range (see product
spec)
display: 5
The following actions take place in the nvram test:
1. read byte from nvram and save it in a register
2. write a pattern (from ROM) to nvram
3. read byte from nvram and compare with pattern
4. if byte read i s ok then continue with action 5 else give
error message and stop testing
If error,
display: 5 Er09
5. write inverted pattern to nvram
6. read byte from nvram and compare with pattern
7. if byte read i s ok then restore original byte else give
error message and stop testing
If error,
display: 5 Er10
8. repeat this for every possible nvram address
STEP
6-8 : DRAM
The dram test is always a destructive test. The test i s
performed for both ram bankO and bank1 as one large
memory followed by a test for each bank separately.
On the displays following, the 'x' i s a memory counter.
The counter i s incremented every 128k. So for the full
range it counts from 1 to 8.
Address range: full address range (see table)
BankO = lower RAM bank
Bank1 = upper RAM bank
STEP 6A : TEST THE FULL DRAM MEMORY
The following actions take place i n this test:
1.
fill the memory with the long word address as data.
display: 6Afx
2. read the memory contents and compare with the
address.
display: 6Arx
3. if the long word read i s ok then continue else give error
message and stop testing.
If error,
display: 6ArxEr11
STEP 6B : TEST THE FULL DRAM MEMORY WITH
INVERTED DATA
The following actions take place i n this test:
1. fill the memory with the inverted long word address as
data.
display: 6Bfx
2. read the memory contents and compare with the
inverted address.
display: 6Brx
3. if the long word read i s ok then continue else give error
message and stop testing.
If error,
display: 6BrxEr12
STEP 7A : TEST DRAM BANKO
The following actions take place in this test:
1.
fill the memory with the long word address as data.
display: 7Afx
2. read the memory contents and compare with the
address.
display: 7Arx
3. if the long word read i s ok then continue else give error
message and stop testing.
If error,
display: 7ArxEr13
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