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Aaeon VPC-5600S User Manual

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VPC-5600S
Mobile NVR
User's Manual 4
Ed
th
Last Updated: July 10, 2018

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Summary of Contents for Aaeon VPC-5600S

  • Page 1 VPC-5600S Mobile NVR User’s Manual 4 Last Updated: July 10, 2018...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel Corporation  Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity VPC-5600S  Product DVD with drivers  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document. Preface...
  • Page 6 All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale. Do not use any cables or adapters not supplied by AAEON to prevent system malfunction or fires.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Embedded Box PC/ Industrial System 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Embedded Box PC/ Industrial System Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 Jumpers and Connectors ..................9 List of Jumpers ......................11 2.3.1 COM1 Ring/+5V/+12V Selection (CN15) ..........12 2.3.2 Clear CMOS (CN10) .................
  • Page 12 Setup submenu: Main ..................36 Setup submenu: Advanced ................. 37 3.4.1 Advanced: CPU Configuration ..............38 3.4.2 Advanced: PCH-FW Configuration ............. 39 3.4.3 Advanced: SATA Drives ................40 3.4.4 Advanced: Trusted Computing ..............41 3.4.5 Advanced: Hardware Monitor .............. 43 3.4.6 Advanced: SIO Configuration ...............
  • Page 13 I/O Address Map ....................70 IRQ Mapping Chart ....................71 Appendix C – Digital I/O Ports ..................... 72 DI/O Programming ....................73 Digital I/O Register ....................74 Digital I/O Sample Program ................75 Preface XIII...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor In-Vehicle NVR  Processor Intel® 7th Gen. Core™ i3/i5/i7 Processor  (Default: i3-7100U) Chipset —  Main Memory Up to 32GB, DDR4 260-pin SODIMM  Display HDMI x 1, DP x 1  Ethernet 10/100/1000Base-TX x 6 (Max. 10) ...
  • Page 16 HDMI x 1 CanBus connector x 1 Audio Line-out x 1, Mic-In x 1 SIM slot x 2 Storage HDD Tray 2.5” HDD Bay x 2  CF/CFast/mSATA Slot mSATA Slot x 1 (If mSATA x 1 used, then only ...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions Chassis Chapter 2 – Hardware Information...
  • Page 19 Chapter 2 – Hardware Information...
  • Page 20 Board Component side 164.4 163.12 162.14 146.19 160.6 153.75 106.9 98.85 74.25 65.85 41.25 18.7 11.87 6.01 10.8 7.16 Chapter 2 – Hardware Information...
  • Page 21 Solder side 140.5 140.5 132.5 132.5 107.58 106.9 77.58 74.65 41.65 47.58 37.5 37.5 29.5 29.5 Chapter 2 – Hardware Information...

  • Page 22: Jumpers And Connectors

    Jumpers and Connectors Component side SATA1 SATA2 CN10 SLOT1 DIMM1 SLOT2 CN11 CN16 CN18 Chapter 2 – Hardware Information...
  • Page 23 Solder side MSATA1 DIMM2 SLOT3 CN23 Chapter 2 – Hardware Information...

  • Page 24: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function CN10 Clear CMOS CN14 ATX/AT Selection CN15 COM1 Ring/+5V/+12V Selection CN16 Can Bus UART/USB Selection CN18 Can Bus Program Firmware Chapter 2 –...

  • Page 25: Com1 Ring/+5V/+12V Selection (Cn15)

    2.3.1 COM1 Ring/+5V/+12V Selection (CN15) Function +5 V Ring (Default) +12 V 2.3.2 Clear CMOS (CN10) Function Clear Protected (Default) 2.3.3 ATX/AT Selection (CN14) Function AT (Default) 2.3.4 Can Bus UART/USB Selection (CN16) Function UART USB (Default) Chapter 2 – Hardware Information...

  • Page 26: Can Bus Program Firmware (Cn18)

    2.3.5 Can Bus Program Firmware (CN18) Function Protected (Default) Program Chapter 2 – Hardware Information...

  • Page 27: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function Power Button Software Reset Power on/off delay selection VGA1 CRT Port Power Button Front Panel Connector Board to Board Connector Display Port LAN3~LAN6(With POE Function)
  • Page 28 CN22 CAN Bus 2.0B Connector AUDIO1 Audio Connector CN11 Fuse Connector Power on/off delay select DIMM1 DIMM2 Slot DIMM2 DIMM1 Slot SLOT1 Mini Card Connector(only USB) half size SLOT2 Mini Card Connector(PCIE+USB) full size SLOT3 Mini Card Connector(only USB) full size MSATA1 mini-SATA Connector SATA1...

  • Page 29: Front Plane Connector (Cn5)

    2.4.1 Front Plane Connector (CN5) Signal Signal PWR_SW# FPANSWH# HWRST# FPANSWH# 2.4.2 COM4 RS-232 Serial Port Connector (COM1) Signal Signal 2.4.3 COM3 RS-232 Serial Port Connector (COM2) Signal Signal Chapter 2 – Hardware Information...

  • Page 30: Com1 & Com2 Rs-232/422/485 Serial Port Connector (Com3)

    2.4.4 COM1 & COM2 RS-232/422/485 Serial Port Connector (COM3) Signal Signal (RS485 (RS422 RX-) Data-/RS422 TX-) (RS485 (RS422 RX+) Data+/RS422 TX+) 2.4.5 Digital I/O Connector (CN20) Signal Signal +GP_V GPI0 GPO0 GPI1 GPO1 GPI2 GPO2 GPI3 GPO3 Chapter 2 – Hardware Information...

  • Page 31: Power In & Remote Button (Cn19)

    2.4.6 Power In & Remote Button (CN19) Signal Signal GND_PRI PWR_IN REMOTE_SW PS_ON# 2.4.7 CAN Bus 2.0B Connector (CN22) Signal Signal CAN DATA + CAN DATA- Chapter 2 – Hardware Information...

  • Page 32: Power On/Off Delay Select (Sw3)

    2.4.8 Power on/off delay select (Sw3) Power On Delay Power Off Remarks Time Time Delay (Sec) (Sec) Switch Pin Number 1800 Control Table Null 2 Day Null Null Null Null Null Null Chapter 2 – Hardware Information...

  • Page 33: Hdd Installation

    2.5” HDD Installation Loosen the screws and remove the bottom cover Attach the brackets to the HDD. Chapter 2 – Hardware Information...
  • Page 34 Install the HDD onto the bottom cover Attach the cables to the motherboard Replace the bottom cover and tighten the screws. Chapter 2 – Hardware Information...

  • Page 35: Msata Drive Installation

    mSATA Drive Installation Loosen the screws and remove the bottom cover Chapter 2 – Hardware Information...
  • Page 36 Remove the screws from 6 locations Chapter 2 – Hardware Information...
  • Page 37 Remove the top cover Chapter 2 – Hardware Information...
  • Page 38 Install the mSATA drive onto the motherboard and tighten the screw Replace the top cover and tighten the screws Replace the bottom cover and tighten the screws Chapter 2 – Hardware Information...

  • Page 39: Gps & Ram Installation

    2.7 GPS & RAM Installation 1. Unscrew the bottom cover. Chapter 2 – Hardware Information...
  • Page 40 2. Remove the bottom cover. Chapter 2 – Hardware Information...
  • Page 41 3. Remove these six screws. Chapter 2 – Hardware Information...
  • Page 42 4. Lift up the case. Chapter 2 – Hardware Information...
  • Page 43 5. Pick up the case. Chapter 2 – Hardware Information...
  • Page 44 6. Install the GPS cable and WiFi Screw. Chapter 2 – Hardware Information...
  • Page 45 7. Install the RAM and thermal pad. Chapter 2 – Hardware Information...

  • Page 46: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 47: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.

  • Page 48: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 49: Setup Submenu: Main

    Setup submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 50: Setup Submenu: Advanced

    Setup submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 51: Advanced: Cpu Configuration

    3.4.1 Advanced: CPU Configuration Options summary: Active Processor Cores Number of cores to enable in each processor package. Hyper-Threading Disabled Enabled Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). Chapter 3 –...

  • Page 52: Advanced: Pch-Fw Configuration

    3.4.2 Advanced: PCH-FW Configuration Options summary: ME FW Image Re-Flash Disabled Enabled Enable/Disable Me FW Image Re-Flash function. Chapter 3 – AMI BIOS Setup...

  • Page 53: Advanced: Sata Drives

    3.4.3 Advanced: SATA Drives Options summary: SATA Controller(s) Disabled Enabled Enable/Disable SATA Device. Hot Plug Disabled Enabled Designates this port as Hot Pluggable. Chapter 3 – AMI BIOS Setup...

  • Page 54: Advanced: Trusted Computing

    3.4.4 Advanced: Trusted Computing Options summary: Security Device Support Disabled Enabled Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. TPM State Disabled Enabled Enable/Disable Security Device. NOTE: Your Computer will reboot during restart in order to change State of the Device.
  • Page 55 TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated Chapter 3 – AMI BIOS Setup...

  • Page 56: Advanced: Hardware Monitor

    3.4.5 Advanced: Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 57: Advanced: Sio Configuration

    3.4.6 Advanced: SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 58: Sio Configuration: Serial Port Configuration

    3.4.6.1 SIO Configuration: Serial Port Configuration Chapter 3 – AMI BIOS Setup...

  • Page 59: Sio Configuration: Serial Port 1 Configuration

    3.4.6.2 SIO Configuration: Serial Port 1 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 60: Sio Configuration: Serial Port 2 Configuration

    3.4.6.3 SIO Configuration: Serial Port 2 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 61: Sio Configuration: Serial Port 3 Configuration

    3.4.6.4 SIO Configuration: Serial Port 3 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 62: Sio Configuration: Serial Port 4 Configuration

    3.4.6.5 SIO Configuration: Serial Port 4 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 63: Sio Configuration: Serial Port 5 Configuration

    3.4.6.6 SIO Configuration: Serial Port 5 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 64: Sio Configuration: Serial Port 6 Configuration

    3.4.6.7 SIO Configuration: Serial Port 6 Configuration Options summary: Use This Device Disabled Enabled Enable or Disable this Logical Device. Possible: Use Automatic Settings IO=2F8h; IRQ=3; IO=3F8h; IRQ=4; Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 65: Advanced: Digital Io Port Configuration

    3.4.7 Advanced: Digital IO Port Configuration Options summary: DIO Port5~8 Output Input Set DIO as Input or Output. Output Level High Set output level when DIO pin is output. Chapter 3 – AMI BIOS Setup...

  • Page 66: Advanced: Power Management

    3.4.8 Advanced: Power Management Options summary: Power Mode ATX Type AT Type Select Power Supply Mode. Restore AC Power Loss Power Off Power On Last State Select AC power state when power is re-applied after a power failure. Chapter 3 – AMI BIOS Setup...

  • Page 67: Setup Submenu: Chipset

    Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 68: Chipset: System Agent (Sa) Configuration

    3.5.1 Chipset: System Agent (SA) Configuration Chapter 3 – AMI BIOS Setup...

  • Page 69: System Agent (Sa) Configuration: Graphics Configuration

    3.5.1.1 System Agent (SA) Configuration: Graphics Configuration Options summary: VT-d Enabled Disabled VT-d capability. Primary Display Auto IGFX Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx. Primary IGFX Boot Display VBIOS Default HDMI Select the Video Device which will be activated during POST.

  • Page 70: Setup Submenu: Security

    Setup submenu: Security Change User/Supervisor Password You can set a User Password once an Administrator Password is set. The password will be required during boot up, or when the user enters the Setup utility. Please Note that a User Password does not provide access to many of the features in the Setup utility. Select the password you wish to set, press Enter to open a dialog box to enter your password (you can enter no more than six letters or numbers).

  • Page 71: Setup Submenu: Boot

    Setup submenu: Boot Options summary: Quite Boot Disabled Enabled Enables or disables Quiet Boot option. Launch PXE ROM Disabled Enabled Controls the execution of UEFI and Legacy PXE OpROM Chapter 3 – AMI BIOS Setup...

  • Page 72: Setup Submenu: Save & Exit

    Setup submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 73: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 74: Product Cd/Dvd

    Product CD/DVD The VPC-5600S comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers.
  • Page 75 Follow the instructions Drivers will be installed automatically Step 5 – Install USB 3.0 Driver Open the Step 5 – USB3.0 folder and select your OS Open the .exe file in the folder Follow the instructions Drivers will be installed automatically Step 6 –...

  • Page 76: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 77: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 78 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 79 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 80 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 81 ************************************************************************************ VOID SIOEnterMBPnPMode(){ Switch(SIOIndex){ Case 0x2E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0x55); Break; Case 0x4E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0xAA); Break; VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0x02); IOWriteByte(SIOData, 0x02); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN);...

  • Page 82: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 83: I/O Address Map

    I/O Address Map Appendix B – I/O Information...

  • Page 84: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...

  • Page 85: Appendix C - Digital I/O Ports

    Appendix C Appendix C – Digital I/O Ports...

  • Page 86: Di/O Programming

    DI/O Programming VPC-5600S utilizes FINTEK F81866 chipset as its Digital I/O controller. Below are the procedures to complete its configuration. AAEON initial DI/O program is also attached for developing customized program for your application. There are three steps to complete the configuration setup:...

  • Page 87: Digital I/O Register

    Digital I/O Register Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Digital Input relative register table Register BitNum Value...

  • Page 88: Digital I/O Sample Program

    Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4...
  • Page 89 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
  • Page 90 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 91 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix C – Digital I/O Ports...
  • Page 92 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 93 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

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