Permanent Protection; Selective Protection; Storage Protection Switch Descriptions - Control Data 3300 Reference Manual

During Executive mode, a protected address remains unaltered (Write is changed
to a Read) during all write operations, except those occuring in Monitor State
and during Block Control operations. The condition is not recorded on the status
line. Refer to the illegal Write
int~rrupt
discussion in Section 4 for additional
information.
Permanent Protection
The upper 32 memory locations of the existing MCS are reserved for Auto Load
and Auto Dump programs when operating in the non-Executive mode. These
addresses are always protected against alteration by a special storage protec-
tion circuit. The actual protected addresses depend upon the number of MCS
locations in a system but always utilize the upper 32 locations in any system.
Logic circuits sense the total storage capacity of the system and check each
storage address as it appears on the S (address) Bus to see if it is among the
protected addresses. If it is one of those to be protected, reading, but no writ-
ing, is allowed at that address. The only time that this protection is disabled
is when an operator presses the ENTER AUTO PROGRAM switch on the console
to enter a new Auto Load or Auto Dump program.
When operating in Executive mode, the Auto Load and Auto Dump storage areas
encompass addresses 003700 8 through 0037778 and a.re protected when refe,:::-enced
through Page Index Zero. Refer to Section 3 for additi onal information on the
Auto. Load and Auto Dump features. '
Selective Protection
3304-A Central Processor
Two different selective protect schemes are available with the 3304- A; one being
standard and the other available by option. In the standard protect scheme, 15
three-position toggle switches, corresponding to the basic 15-bit storage address,
are set to selectively protect individual addresses or a block of addresses. The
switches are located on the power control panel as shown in Section 7.
Table 2-1 describes the three switch positions and Table 2- 2 lists examples of
switch settings. The switches are automatically disabled during execution of the
BDP instructions (64-70). In Executive mode, the switches apply to an address
range of which the upper 3 address bits (ISR) or (OSR) are equal to zero.
TABLE 2-1. STORAGE PROTECTION SWITCH DESCRIPTIONS
Switch
Output
Position Description
"1" Up Each address protected will have a "1" in this bit position.
"N"
Center
Each address protected may have either a "1" or a
"a"
in
this position. For example, when all switches are set to
the' neutral position, all storage is protected, provided
i
that the protect feature is enabled.
"a"
Down
Each address protected will have a
"a"
in this bit position.
Rev. H 2-6