1. Manuals
  2. Brands
  3. Freescale Semiconductor Manuals
  4. Gateway
  5. QorIQ LS1021A-IOT
  6. Reference manual

Freescale Semiconductor QorIQ LS1021A-IOT Reference Manual

Reference design board
Hide thumbs Also See for QorIQ LS1021A-IOT:
Table of Contents

Advertisement

Quick Links

Download this manual
QorIQ LS1021A-IOT Gateway
Reference Design Board Reference
Manual
Document Number: LS1021A-IOTRM
Rev. 0, 03/2015

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the QorIQ LS1021A-IOT and is the answer not in the manual?

Questions and answers

Related Manuals for Freescale Semiconductor QorIQ LS1021A-IOT

Summary of Contents for Freescale Semiconductor QorIQ LS1021A-IOT

  • Page 1 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual Document Number: LS1021A-IOTRM Rev. 0, 03/2015...
  • Page 2 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 3: Table Of Contents

    Device configuration...............................22 Clocks..................................... 23 2.6.1 SYSCLK................................24 2.6.1.1 Single-Source SYSCLK........................24 2.6.2 DDRCLK................................24 2.6.3 SerDes clocks..............................25 2.6.4 Ethernet clocks..............................25 2.6.5 Codec SYS MCLK.............................25 Memory controllers.................................25 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 4 2.23 Monitoring LEDs................................44 2.24 MBED..................................... 45 Chapter 3 Expansion Headers and Ports K22 expansion (internal)..............................47 Audio expansion (internal)............................. 48 Arduino expansion (internal)............................48 Rear panel expansion ports (external)..........................50 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 5 LCD FDI translator................................. 57 Chapter 5 Board Configuration and Debug Support Kit contents..................................59 Case and PCB description...............................60 Configuring switches and jumpers..........................63 Memory map ..................................65 CMSIS-DAP debug support............................66 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 6 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 7 The LS1021A-IOT board is lead-free and RoHS-compliant. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 8: Related Documentation

    AMBA4 MPCORE™ Virtualization, each with separate ECC protected L1 32 KB I cache and 32 KB D cache and a shared 512 KB L2 cache with ECC protection QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 9: Board Features

    The features of the LS1021A-IOT reference board are as follows: • Four lanes of SerDes connections supporting: • Two PCI Express buses that support Gen 1 and Gen 2 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 10 • ISL8201MIRZ - 3.3 V board supply including CPLD • MC34VR500 Power Management IC (PMIC) supplying VDD and VDDC and GVDD, VTT, VREF, O1VDD, OVDD, L1VDD, and LVDD • 2x MAX8869 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 11: Block Diagram

    This section provides a high-level overview of the LS1021A processor, as well as the LS1021A-IOT/LS1020A platform. The figure below shows the major functional units within the LS1021A device. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 12 Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements Figure 1-1. LS1021A block diagram The figure below shows the overall architecture of the LS1021A-IOT/LS1020A platform. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 13 Quad USB 3.0 ARDUINO USB 3.0 UART UART NAND UART 4-wire 2-wire 3L/4 USB 3.0 GPIO QuadSPI DDR3L CPLD MMA8451Q Figure 1-2. LS1021A-IOT System block diagram QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 14 Block diagram QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 15: Architecture

    The 12 V can either be supplied from the barrel connector or alternatively from a Power Over Ethernet (PoE) source plugged into the ETH3 RJ45 port. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 16 Description Voltage generated Supplies MAX8869EU25 +1V5_MPCIE MiniPCIe Slots P1 and P2 U502 MAX8869EU25 +1V25 USB HUB - USB5534B (U503) USB Port 1 and 2 SATA connector QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 17 MAX8869EU25 (P1 & P2) USB HUB +1V25 USB5534B MAX8869EU25 (U503) USB 3.0 Port 1 USB 3.0 Port 2 SATA Connector +3V3 Figure 2-2. LS1021A-IOT power tree QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 18: Mc34Vr500

    Jumpers J19 and J20 should be populated with shunts to connect them to the 1.8 V supply. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 19: Power Sequence

    Rise time of EN Turn-on delay of first regulator 2.5 Rise time of regulators [2] Delay between regulators Turn-on delay of PORB Rise time of PORB QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 20: Deep Sleep Control

    Reset signals to and from the LS1021A board and other devices on LS1021A-IOT are managed by CPLD. The figure below shows an overview of the reset architecture. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 21 The CPLD implements a reset sequencer, which manages the assertion and release of the reset signals to the system. It also manages the POR configuration and timing to the LS1021A board. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 22: System Reset

    IFC TE signal enable Driven high during POR by CPLD cfg_gpinput[0:7] IFC_AD[0:7] CPLD Version MAJOR - AD[0:3] MINOR - AD[4:7] Table continues on the next page... QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 23: Clocks

    DIFF_SYSCLK DIFF_SYSCLK 125M_CLK EC3_125GTX_CLK DDRCLK 6V49205BNLGI DDRCLK 25MHz_SGMII1_CLK SGMII PHY1 25MHz_SGMII2_CLK SGMII PHY2 25MHz_RGMII_CLK ETH SWITCH MPCIE1_CLK MPCIE SLOT1 MPCIE2_CLK MPCIE SLOT2 Figure 2-6. Clock architecture QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 24: Sysclk

    DIFF_SYSCLK_P/DIFF_SYSCLK_N inputs on the processor. This will then supply all clocks to the core, platform (SYSCLK), DDR controller (DDRCLK), and USB controller (USBCLK). QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 25: Serdes Clocks

    SGMII PHYs and RGMII PHY. 2.6.5 Codec SYS MCLK The SGTL5000 audio codec requires a master audio frequency. The IDT5P49V5901A031NLGI is pre-programmed to source 24.576 MHz to it. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 26: Memory Controllers

    DDR3_CLK_N LS1021A DDR3L DDR3_DQS[3:2]_P DDR3_DQS[3:2]_N DDR3_DQ[31:16] DDR3_DM[3:2] DDR3_CLK_P DDR3_CLK _N DDR3L (ECC) DDR3_DQS 8_P DDR3_DQS 8_N DDR3_ECC [3:0] DDR3_DM 8 DDR3_CLK_P DDR3_CLK_N Figure 2-7. Memory controllers QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 27: Serdes Port

    Table 2-8. LS1021A-IOT SerDes Lane B selection Switch Setting Option Description 0 : SerDes Lane 2 - SATA S2.5 SGMII2_SATA MUX 1 : SerDes Lane 2 - SGMII2 (default) QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 28: Pci Express Support

    PETn0 SMB_DATA SMB_CLK +1.5V_MPCIE PERp0 PERn0 +3.3Vaux PERST# Reserved Reserved Reserved Mechanical Key Reserved REFCLK+ Reserved REFCLK- Reserved Reserved CLKREQ# Reserved Reserved 1.5V_MPCIE Reserved WAKE# 3.3V QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 29: Sgmii Support

    SGMII mode. The two SGMII ports connect to Atheros AR8033 PHYs whilst the RGMII is routed to a Realtek RTL8365MB-CG 4 port lightly managed layer 2 Gigabit Ethernet switch. The Ethernet connectivity is shown in the following figure. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 30 Blink - activity L2 Switch Ethernet Port3 (via LVDD(2.5V) ETH4 Green/Orange On - link No link eTSEC3) Blink - activity Table continues on the next page... QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 31: Ethernet Management Interfaces

    The SGMII PHYs are controlled via the LS1021A Ethernet management interface. The Realtek switch is controlled over the SPI interface. The routing architecture for the both is shown in the following figure. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 32: Usb Interface

    AR8033 MDIO AR8033 LS1021A SPI1_PCS1 SPI1_SCK RTL8365MB-CG SPI1_OUT SPI1_SIN Figure 2-9. Ethernet Management routing NOTE IEEE-1588™ is not supported on the LS1021A-IOT board. 2.11 USB interface QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 33 PORT3 DM/DP Mini PCIe Slot 1 PORT4 DM/DP Mini PCIe Slot 2 Figure 2-10. USB architecture NOTE The USB block requires no board-specific setup or programming. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 34: Local Bus

    No dedicated address lines are available in the multiplexed mode. The following figure gives an overview of the IFC bus. IFC_AD[0:7] IFC_CS0_B CPLD IFC_WE0_B IFC_OE0_B LS1021A QSPI_CS_A0 QSPI_CS_A1 QSPI QSPI_DIO_A[3:0] Figure 2-11. IFC architecture QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 35: Ace - Display Controller Port

    2.13.1 Programming display control unit The display control unit (2D-ACE) should be programmed to generate the pixel data/ clock/enables in order to properly drive the selected encoder. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 36: I2C

    The second I2C1 bus device map is given below. Table 2-13. Second I2C1 bus device map 7b Addr Description Device Notes 0x08 PMIC MC34VR500V1ES(U13) 0x1C Accelerometer MMA8451Q (U18) Table continues on the next page... QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 37: Spi Interface

    SPI2 is not available due to pin multiplexing. The figure below shows the overall connections of the SPI. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 38: Sdhc Interface

    SDHC_WP and SDHC_CD_N are multiplexed with I2C2 signals. Therefore, by default, they are not supported. The following figure shows the overall connections of the SDHC portion. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 39: Interrupt Controller

    CPLD so that the various board interrupt sources can be consolidated to individual interrupt pins as well as provided with appropriate voltage level conversion. The figure below shows the interrupt architecture. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 40 Table 2-14. Interrupt connections Signal names Connected CPLD O/D Note devices IRQ0_B HDMI Interrupt +1.8V O1VDD, Pull-up on board Table continues on the next page... QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 41: Event Pins

    UART using a program such as Teraterm on a host PC. The second UART on the LS1021A-IOT board is the 4-wire LPUART1, which is routed to QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 42: Audio Port

    Port0 LPUART1_CTS_B J500 LPUART1_RTS_B Figure 2-16. Serial architecture 2.20 Audio port The Synchronous Audio Interface (SAI) architecture can be illustrated as shown in the figure below. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 43: Jtag Port

    Codewarrior TAP for ARM. The CMSIS-DAP provides an alternative via a USB cable. The COP/JTAG architecture is shown in the figure below. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 44: Gpio Pins

    Controlled via I2C. Available on back panel Port 1 (J501). CPLD_EXPAND[5:0] Connected to CPLD. Available on back panel Port 1 (J501) Functionality reserved for future use. 2.23 Monitoring LEDs QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 45: Mbed

    It bridges serial and debug communications between a USB host and an embedded target processor as shown in the figure below. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 46 MBED features a mass storage device (MSD) bootloader, which provides a quick and easy mechanism for loading different MBED applications, such as flash programmers, run-control debug interfaces, serial-to-USB converters, and more. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 47: Expansion Headers And Ports

    SDA_PTB0 SDA_PTB2 SDA_PTB2 SDA_PTA13 PTA13 +3V3 SDA_PTC0 PTC0 SDA_PTB3 SDA_PTB3 SDA_PTC8 PTC8 SDA_PTB16 SDA_PTB16 SDA_PTB17 SDA_PTB17 SDA_PTC9 PTC9 SDA_PTC10 PTC10 SDA_PTB18 SDA_PTB18 SDA_PTC11 PTC11 SDA_PTB19 SDA_PTB19 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 48: Audio Expansion (Internal)

    The LS1021A-IOT board implements an Arduino Uno pinout to allow connection of SPI/ UART and I2C shields. Typically, this slot will be used for low power radios such as ZigBee or 6LoPan. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 49 (U10) (U10) Table 3-7. J16 Pinout Net name Source Net name Source SPI1_SIN LS1021A SPI1 +5V0 Power SPI1_SCK LS1021A SPI1 SPI1_OUT LS1021A SPI1 RST_ARD_SHIELD CPLD Power QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 50: Rear Panel Expansion Ports (External)

    Table 3-10. Port 1 (J501) Pinout Net name Source Net name Source +3V3 Power CPLD_EXPAND0 CPLD GPIO_EXPAND0 GPIO EXPANDER +5V0 Power PCA9555BS (U2) Table continues on the next page... QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 51 GPIO3_19 LS1021A Power GPIO3_20 LS1021A GPIO3_18 LS1021A GPIO3_21 LS1021A GPIO3_17 Power Power GPIO3_26 LS1021A GPIO3_27 LS1021A Power GPIO3_16 LS1021A GPIO3_22 LS1021A GPIO3_23 LS1021A GPIO3_15 LS1021A Power QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 52 Rear panel expansion ports (external) QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 53: Cpld System Controller Architecture

    Chapter 4 CPLD System Controller Architecture This chapter explains the CPLD system controller architecture. The figure below illustrates the detailed block diagram of the CPLD. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 54: Key Features Of Cpld

    Figure 4-1. CPLD overview 4.1 Key features of CPLD This CPLD includes the following features: • Control power on sequence • Power on CPU VDD, GVDD, and others powers. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 55: Reset

    (PORESET_b), which causes the CPLD to drive configuration values onto the pin- sampled nets. The following figure illustrates the reset sequences. PORESET_B HRESET_B (high impedance) RESET_REQ_B (high impedance) ASLEEP SYSCLK POR Configs Figure 4-2. Reset power sequencing QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 56: Cpld Register Map

    The following table shows a detailed address map description. Table 4-2. CPLD write register details Access Description Options Default value LED0 Control 0 LED OFF 1 LED ON Table continues on the next page... QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 57: Lcd Fdi Translator

    RGB interface, 8-bit R, 8-bit G, and 8-bit B. This is needed to translate LCD signals from FDI 2-bits to 1-bit. The following figure shows the timing for LCD FDI translation. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 58 24 latches pos Data out EVEN1 EVEN2 VSYNC out 1 latch pos 1 latch pos HSYNC out 1 latch pos Figure 4-3. Timing of FDI translation QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 59: Board Configuration And Debug Support

    • 1x LS1021A-IOT Gateway • 1x 12 V at 5 A PSU • 1x Micro-B USB cable • 1x HDMI cable • 1x 8 GB SDHC card QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 60: Case And Pcb Description

    5.2 Case and PCB description The LS1021A-IOT is contained within an enclosure. The following figures of the front and rear panels are annotated to describe the I/O functions and indicators. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 61 Chapter 5 Board Configuration and Debug Support Figure 5-2. LS1021A-IOT Chassis - Front Figure 5-3. LS1021A-IOT Chassis - Rear The features of the board are shown in the following figures. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 62 CPLD JTAG HDMI SERIAL 2xRJ45 Gigabit 4xRJ45 Gigabit /JTAG L2 SWITCH PORTS SGMII PORTS 2x USB 3.0 TYPE A Figure 5-4. LS1021A-IOT PCB - top side QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 63: Configuring Switches And Jumpers

    Chapter 5 Board Configuration and Debug Support SD CARD SLOT Figure 5-5. LS1021A-IOT PCB - bottom side 5.3 Configuring switches and jumpers QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 64 Table 5-2. Jumper settings Jumpers Default settings on LS1021A-IOT Description VDD_LP Source Select OFF – Battery ON - +1V0_VDDC Reserved Reserved Reserved The following figure shows the jumper locations. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 65: Memory Map

    Size 0x0100_0000 0x0FFF_FFFF CCSR Space 240MB 0x4000_0000 0x43FF_FFFF QSPI (Chip select 0) 64GB 0x4400_0000 0x47FF_FFFF QSPI (Chip select 1) 64GB 0x7FB0_0000 0x7FB0_0004 CPLD register 0x8000_0000 0xBFFF_FFFF QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 66: Cmsis-Dap Debug Support

    For further information, see the Debugger User Manual. JTAG Header 1. Ensure the board is not switched on. 2. Open the case. 3. Set SW2.8 in OFF position to select JTAG header operation. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 67 5. Switch on the power supply to the board. 6. Check for completion of the reset sequence. NOTE For further information, see the Debugger User Manual. QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 68 CMSIS-DAP debug support QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.

  • Page 69: Revision History

    Appendix A Revision History The table below provides revision history of this document. Table A-1. Revision history Revision Date Description Rev 0 03/2015 Initial public release QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 70 QorIQ LS1021A-IOT Gateway Reference Design Board Reference Manual, Rev. 0, 03/2015 Freescale Semiconductor, Inc.
  • Page 71 Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SafeAssure logo, SMARTMOS, Tower, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc.
  • Page 72 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: LS1021A-IOT LS1021A-IOT-B...

Table of Contents