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Force SPARC/CPCI-520G Technical Reference Manual

Sparc/cpci-52x(g) series
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SPARC/CPCI-52x(G)
Technical Reference Manual
P/N 208914 Edition 2.0
November 2000
Force Computers GmbH
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless written permission has been granted.
Copyright by Force Computers

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  • Page 1 SPARC/CPCI-52x(G) Technical Reference Manual P/N 208914 Edition 2.0 November 2000 Force Computers GmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless written permission has been granted. Copyright by Force Computers...
  • Page 2 Email smiyagawa@fci.com The information in this document has been carefully checked and is believed to be entirely reliable. Force Computers makes no warranty of any kind with regard to the material in this document, and assumes no responsibility for any errors which may appear in this document. Force Computers reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance, or design.

  • Page 3: Table Of Contents

    4.2.1 FORCE COMPUTERS UPA64S Card Installation ..... 25 Powering Up ............26 Switch Settings .
  • Page 4 Contents SCSI #1 Configuration ..........38 Ethernet Address and Host ID .
  • Page 5 FORCE OpenBoot Enhancements ........
  • Page 6 Contents Page iv SPARC/CPCI-52x(G)
  • Page 7 Excerpt from the product’s ordering information ......9 Tab. SPARC/CPCI-520G (schematic view) ....... . . 11 Fig.
  • Page 8 Tables and Figures Page Tab./Fig. Diagnostic routines ..........47 Tab.

  • Page 9: Using This Manual

    • a detailed hardware description : see section 6 “Hardware Descrip- tion” on page 65. • a detailed description of OpenBoot which controls the CPU board operations: see section 7 “FORCE OpenBoot Enhancements” on page 101. SPARC/CPCI-52x(G) Page vii...
  • Page 10 Using This Manual The Sun OpenBoot 3.x manuals are available on the following web site: http://docs.sun.com. The following data sheets of board components are relevant to the SPARC/CPCI-52x(G). They contain appropriate information on config- uring and integrating the board in systems and can be found on the re- spective company’s webpage.
  • Page 11 Using This Manual Publication History of the Manual Table a History of manual publication Date Description Feb/1998 First print Jan/1999 Thoroughly revised, corrected SCSI-related OpenBoot command description, added descriptions for Miscellaneous Control Register, Miscellaneous Control and Status Register as well as ENUM Inter- rupt Control Register, extended temperature sensor description Added descriptions for installing Solaris, added description for OpenBoot plcc2tsop command (version 3.10.4 or greater)

  • Page 12: Fonts, Notations And Conventions

    Using This Manual Fonts, Notations and Conventions Table b Fonts, notations and conventions Notation Description All numbers are decimal numbers except when used with the following notations: Typical notation for hexadecimal numbers (digits are 0000.0000 0 through F), e.g. used for addresses and offsets. Note the dot marking the 4th (to its right) and 5th (to its left) digit.
  • Page 13 Using This Manual Icons for Ease of Use: Safety Notes and Tips & Tricks The following 3 types of safety notes appear in this manual. Be sure to al- ways read and follow the safety notes of a section first – before acting as documented in the other parts of the section.
  • Page 14 Using This Manual Page xii SPARC/CPCI-52x(G)

  • Page 15: Safety Notes

    It must not be used except in its spe- cific area of office telecommunication industry and industrial con- trol. Only personnel trained by Force Computers or qualified persons in electronics or electrical engineering are authorized to install, unin- stall or maintain the SPARC/CPCI-52x(G). The information given in this manual is meant to complete the knowledge of a specialist and must not be taken as replacement for qualified personnel.
  • Page 16 • Only replace components or system parts with those recom- mended by Force Computers. In case you use components other than those recommended by Force Computers, you are fully responsible for the impact on EMI and the eventually changed functionality of the product.
  • Page 17 Safety Notes RJ-45 An RJ-45 connector is available on the board. Take into account that the RJ-45 connector type is used for telephone connectors and for connector twisted pair Ethernet (TPE) connectors. Note that mismatching these 2 connectors may destroy your telephone as well as your SPARC/CPCI-52x(G).
  • Page 18 Page 4 SPARC/CPCI-52x(G)

  • Page 19: Introduction

    Introduction Introduction The SPARC/CPCI-52x(G) is a high performance CompactPCI board computer providing a CompactPCI system controller interface including DMA. It is based on • the UltraSPARC-IIi processor • the Advanced PCI Bridge (APB) with interfaces to the CompactPCI An UPA64S card can be connected for high performance graphics sup- port.
  • Page 20 Introduction Page 6 SPARC/CPCI-52x(G)

  • Page 21: Specifications Of The Sparc/Cpci-52X(G)

    Introduction Table 1 Specifications of the SPARC/CPCI-52x(G) Processor UltraSPARC-IIi with 300 MHz Shared main memory 32 MByte to 1 GByte EDO DRAM with ECC L2 cache 256 KByte or 1 MByte late write SRAM with parity PMC slots 2 for 32 bit with 33 MHz PMC modules CompactPCI interface 32 bit with 33 MHz SCSI...

  • Page 22: Product Nomenclature

    Product Nomenclature Introduction Product Nomenclature The SPARC/CPCI-52x(G) is available in several variants, with or with- out I/O-52x(G) as well as several memory and speed options. Consult your local sales representative to confirm availability of specific combi- nations. The table below explains the general product nomenclature. Table 2 Nomenclature of the SPARC/CPCI-52x(G) SPARC/CPCI-52xG/mmm-sss-c-uu-ggg...

  • Page 23: Ordering Information

    Introduction Ordering Information Ordering Information The following table is an excerpt from the SPARC/CPCI-52x(G) order- ing information at the time of print. Contact your local FORCE COM- PUTERS representative for current information. Table 3 Excerpt from the product’s ordering information...
  • Page 24 Ordering Information Introduction Page 10 SPARC/CPCI-52x(G)

  • Page 25: Installation

    Installation This section describes the SPARC/CPCI-52x(G) variants you may pur- chase from FORCE COMPUTERS. It is intended to get an overview over all possible configurations with named components which will help to find the information necessary for your configuration in this manual.

  • Page 26: Sparc/Cpci-522G (Schematic View)

    Installation • a SPARC/CPCI-522G obtaining the 2 slot base board with UPA64S card option (Base-520G) and with the peripheral slot I/O-522G. Figure 3 SPARC/CPCI-522G (schematic view) 1 CompactPCI segments UPA 64S UPA 64S I/O-522G local PCI local PCI PMC # 2 PMC # 1 Ethernet UPA 64S...

  • Page 27: Schematic Exploded Mechanical Construction View

    The Lithium battery of the RTC/NVRAM provides a data retention of at least 7 years summing up all periods of actual battery use. Therefore FORCE COMPUTERS assumes that there usually is no need to exchange the Lithium battery except for example in the case of long-term spare part handling.

  • Page 28: Installation Prerequisites And Requirements

    Installation Prerequisites and Requirements Installation • Use appropriate tools to remove the battery. • When installing the new battery ensure that the marked dot on top of the battery covers the dot marked on the chip. • Used batteries have to be disposed according to your country’s legislation.

  • Page 29: Maximum Power Supply Values Without Upa64S Card And Pmc Modules

    Maximum power supply values without UPA64S card and PMC modules CPU board +5 V +3.3 V +/-12 V V I/O SPARC/CPCI-520 6.5 A 4.6 A not required 200 mA SPARC/CPCI-520G 6.5 A 4.6 A not required 200 mA SPARC/CPCI-522 7.8 A 5.6 A not required 200 mA SPARC/CPCI-522G 7.8 A...

  • Page 30: Audio Interfaces Requirements

    Installation Prerequisites and Requirements Installation Table 6 Audio interfaces requirements Interface Description Stereo Micro In • Signal level: single-ended condensator microphones with signal (op-amp pre-amp level with 18 dB gain) –up to 12 mV with 20 dB gain inside Codec enabled –and up to 120 mV with 20 dB gain inside Codec disabled •...

  • Page 31: Memory Modules

    Installation Installation Prerequisites and Requirements 3.1.2 Memory Modules The main memory capacity is adjustable via installation of the appropri- ate memory modules. The qualified memory modules depend on the SPARC/CPCI-52x(G) pro- cessor frequency. They are given in the following table. Table 7 Qualified memory modules Processor frequency...

  • Page 32: Solaris Installation

    Installation Prerequisites and Requirements Installation The memory configuration is adjustable to the application’s needs via se- lection of the appropriate memory modules. The memory configuration must fulfill the following requirements: • The lowest memory module (#1) must be a SPARC/MEM-50L – which is a lower memory module.

  • Page 33: Required Solaris Packages

    Installation Installation Prerequisites and Requirements General Installation Guidelines Note: Solaris versions and hardware updates prior to 2.5.1 11/97 and 2.6 03/98 are not supported. Required In case of Solaris 2.5.1 and Solaris 2.6 the following Solaris software software packages must be installed, otherwise Solaris fails to boot. packages Table 9 Required Solaris Packages...

  • Page 34: Terminal Connection

    Installation Prerequisites and Requirements Installation SCSI The Solaris SCSI driver may revert Wide-SCSI devices, which are con- nected to the front-panel SCSI connector, to asynchronous mode. How- ever, it is possible to operate such a configuration in synchronous mode also by inserting the following line into /kernel/drv/glm.conf: target n -scsi-options=0x5f8 where n is the SCSI ID of the Wide-SCSI device under consideration.

  • Page 35: Base-520(G) Installation

    Base-520(G) Installation Location Overview Base-520(G) Installation Location Overview The Base-520(G) contains the following main components: • a UltraSPARC-IIi processor, • a second level cache (L2 cache), • a CompactPCI interface, • a boot PROM (PLCC), • a boot flash EPROM (TSOP) and an user flash EPROM (TSOP), •...

  • Page 36: Location Diagram Of The Base-520(G) (Schematic)

    Location Overview Base-520(G) Installation Figure 7 Location diagram of the Base-520(G) (schematic) UPA64S connector P7 XCVR Ethernet #1 SCSI #1 Connector for I/O board P6 MEM-50L connectors P8, P9, P10 Audio Temperature UltraSPARC-IIi Super I/O sensor #1 Temperature sensor #2 L2 cache PHYceiver Serial I/O...

  • Page 37: Mechanical Construction

    3 memory module connectors for up to 4 memory modules. With an installed UPA64S card only 2 memory modules are possible. The following figures show the Base-520(G) in possible configurations: Figure 8 Mechanical construction of a Base-520G FORCE COMPUTERS UPA64S card CPU and cache with MEM-50U...

  • Page 38: Mechanical Construction Of A Base-520

    Mechanical Construction Base-520(G) Installation Figure 10 Mechanical construction of a Base-520 CPU and cache with MEM-50U heatsink MEM-50L Base-520 in 1st slot The Base-520 is only available as a 2-slot solution with an I/O-522. Figure 11 Components of a 2-slot configuration with UPA64S card (schematic) UPA64S card Up to 2 memory modules I/O-52xG...

  • Page 39: Force Computers Upa64S Card Installation

    4.2.1 FORCE COMPUTERS UPA64S Card Installation You can only install a FORCE COMPUTERS UPA64S card if you pur- chased a SPARC/CPCI-52xG version. It is connected to the Base-520G via the UPA64S connector P7 (see figure 7 “Location diagram of the Base-520(G) (schematic)”...

  • Page 40: Powering Up

    Powering Up Base-520(G) Installation 4. If you do not install the UPA64S card again, fix the blind panel. 5. To install the I/O-52xG again refer to the installation section of the I/O-52x(G). Figure 12 Installing/Deinstalling an UPA64S card UPA64S card Base-520G I/O-52xG I/O-52xG connector...

  • Page 41: Switch Settings

    Base-520(G) Installation Switch Settings User application The SPARC/CPCI-52x(G) provides 1 user flash EPROM devices (2M*8) to store user applications. As factory option 2 user flash EPROM devices (2M*8) are possible. For write-protection of the user flash EPROM see SW4-4 in section 4.4 “Switch Settings” on page 27. Switch Settings The following table lists the functions and the default settings of all switches shown in figure 7 “Location diagram of the Base-520(G) (sche-...

  • Page 42: Front Panel And Connectors

    Front Panel and Connectors Base-520(G) Installation Table 11 Default switch settings (cont.) Name and default setting Function SW5-1 SCSI termination for SCSI #1 on front panel OFF = front panel termination automatic ON = front panel termination disabled SW5-2 SCSI termination for SCSI #1 on backplane OFF = backplane termination disabled ON = backplane termination enabled SW5-3...

  • Page 43: Front Panel Features

    Base-520(G) Installation Front Panel and Connectors Table 12 Front panel features Device Description RESET Mechanical reset key: When enabled and toggled it instantaneously affects the SPARC/CPCI-52x(G) by generating a push-but- ton Power On Reset (POR) to the UltraSPARC-IIi. Push-button Power On Reset has the same effect as a Power On Reset from the power supply, with the only difference, that the corresponding status bit (B_POR) in the UltraSPARC-IIi Reset_Control Register is...

  • Page 44: On-Board Connectors

    Front Panel and Connectors Base-520(G) Installation Table 12 Front panel features (cont.) Device Description 0, 1 2 software programmable user LEDs. Possible status: off, red, yellow, or green, all colors either permanent or with a blinking frequency of ap- proximately 0.5, 1, or 2 Hz. Standard 3.5 mm microphone jack HDPH Standard 3.5 mm headphone jack...

  • Page 45: Audio Interface

    Base-520(G) Installation Front Panel and Connectors • Floppy interface • Parallel interface • Serial interface A and B • Keyboard and mouse • Audio In: Stereo Line In, Stereo Aux#1 In, Stereo Aux#2 In (or Microphone In as factory option) •...

  • Page 46: Ethernet Interfaces

    Front Panel and Connectors Base-520(G) Installation 4.5.2 Ethernet Interfaces The full duplex Ethernet interface is available at the front panel via a 10BaseT/100BaseTx Twisted-Pair-Ethernet connector. Table 15 Twisted-Pair-Ethernet #1 connector pinout Connector Signal TX– RJ-45 TPE RX– The Ethernet #1 interface is also accessible at the J5 back panel connector via an MII #1 interface.

  • Page 47: Scsi #1 Connector Pinout

    Base-520(G) Installation Front Panel and Connectors 4.5.3 SCSI #1 Connector Pinout TERMPWR The SCSI #1 interface is single-ended and supports TERMPWR. AUTOTERM Automatic termination mode means the respective termination is disabled when you connect a standard SCSI cable to the front panel connector. Table 16 50-pin SCSI connector pinout Signal...

  • Page 48: Serial I/O Interface Connector Pinout

    Front Panel and Connectors Base-520(G) Installation 4.5.4 Serial I/O Interface Connector Pinout Both serial I/O interfaces of the Base-520(G) are independent full-duplex channels. For each of them the 4 signals RXD, TXD, RTS, and CTS are also provided via the respective CompactPCI J5 connector (for interface A and B see figure 13 “CompactPCI J5 connector pinout”...

  • Page 49: Keyboard/Mouse Connector

    Base-520(G) Installation Front Panel and Connectors Table 18 26-pin serial A+B connector pinout RS422 (factory option) Signal Connector Signal n.c. CTS+_B (Input)) CTS+_A (Input)) RTS–_A (Output) RTS–_B (Output) RTS+_A (Output) CTS–_A (Input) RTS+_B (Output) RxD–_A (Input) RxD+_A (Input) TxD–_A (Output) n.c.

  • Page 50: Compactpci Backplane Connector Pinout

    Front Panel and Connectors Base-520(G) Installation 4.5.6 CompactPCI Backplane Connector Pinout J1 and J2 The J1 and J2 connectors implement the CompactPCI 64-bit connector pinout as specified by the CompactPCI Specification. Therefore, this sec- tion only documents the pinout of the J5 connector. J3 is reserved.
  • Page 51 Base-520(G) Installation Front Panel and Connectors I/O panel As a separate price list item an I/O panel is available for the Base-520(G), the SPARC/IOBP-520/CPU. An extended variant is the SPARC/CPCI- 520/AccKit/CPU which contains additionally to the I/O panel the follow- ing cables: –a serial splitter cable for the front panel and the I/O panel –a flat ribbon SCSI cable for the I/O panel...

  • Page 52: Scsi #1 Configuration

    SCSI #1 Configuration Base-520(G) Installation SCSI #1 Configuration Note: Correct SCSI bus selection: The Base-520(G) provides 1 SCSI bus, SCSI #1. A further SCSI controller, SCSI #2, is available with the I/O-52x(G). Its termination is described in the I/O-52x(G) installation section. SCSI #1 The Base-520(G)’s SCSI #1 bus is accessible via the Base-520(G)’s termination...
  • Page 53 Base-520(G) Installation SCSI #1 Configuration Default • The default configuration 1 is covered by the default switch setting: configuration 1 The Base-520(G) is located at an endpoint of the SCSI #1 bus, the for 8 bit SCSI SCSI #1 bus is extended via the CompactPCI backplane (J5 connec- tor), but no SCSI cable is plugged into the front-panel SCSI connec- tor: Front...
  • Page 54 SCSI #1 Configuration Base-520(G) Installation Alternative • Alternative configuration: the Base-520(G) is located at an endpoint configuration for of the SCSI #1 bus and the CompactPCI backplane is not used for 8 bit SCSI SCSI #1 bus signalling, but the SCSI #1 bus is extended via the front panel connector: Front CompactPCI...

  • Page 55: Ethernet Address And Host Id

    Base-520(G) Installation Ethernet Address and Host ID Ethernet Address and Host ID In order to see the Ethernet address and host ID, type the following com- mand at the prompt: ok banner The information below explains how the SPARC/CPCI-52x(G) Ethernet address and the host ID are determined.

  • Page 56: Openboot Firmware

    For more information on the OpenBoot firmware see the Open Boot 3.x Manual Set. The OpenBoot firmware is subject to changes. For newest version and how to upgrade refer to the SMART service accessible via the FORCE COMPUTERS World Wide Web site. 4.8.1...
  • Page 57 Base-520(G) Installation OpenBoot Firmware Optional Boot Parameters Note: These options are specific to the operating system and may differ from system to system. [device-specifier] The name (full path or alias) of the boot device. Typical values are cdrom, disk, floppy, net, or tape. The name of the program to be booted.
  • Page 58 OpenBoot Firmware Base-520(G) Installation Page 44 SPARC/CPCI-52x(G)

  • Page 59: Device Alias Definitions

    Base-520(G) Installation OpenBoot Firmware Table 20 Device alias definitions Alias Description Defined for SCSI SCSI scsi Default disk SCSI-target-ID 0 disk disk SCSI-target-ID 6 disk6 disk SCSI-target-ID 5 disk5 disk SCSI-target-ID 4 disk4 disk SCSI-target-ID 3 disk3 disk SCSI-target-ID 2 disk2 disk SCSI-target-ID 1 disk1...

  • Page 60: Nvram Boot Parameters

    OpenBoot Firmware Base-520(G) Installation 4.8.2 NVRAM Boot Parameters The OpenBoot firmware holds its configuration parameters in NVRAM. At the Forth monitor prompt enter printenv to see a list of all available configuration parameters. Note: Per default the SPARC/CPCI-52x(G) boots the OS automatically.

  • Page 61: Diagnostic Routines

    Base-520(G) Installation OpenBoot Firmware figuration parameter diag-switch? is true for each test, a message is displayed on a terminal connected to the serial I/O interface A. If the system does not work correctly, error messages are displayed which indi- cate the problem. After POST the OpenBoot firmware boots an operating system or enters the Forth monitor, if the NVRAM configuration parame- ter auto-boot? is false.
  • Page 62 OpenBoot Firmware Base-520(G) Installation All SCSI buses To check all the SCSI buses installed in the system enter the following (The actual response depends on the devices on the SCSI buses).: ok probe-scsi-all /pci@1f,0/scsi@2 Target 6 Unit 0 Disk Removable Read Only Device SONY CD-ROM CDU-8012 3.1a /pci@1f/pci@4,1/scsi@2 Target 3 Unit 0 Disk FUJITSU M2952ESP SUN2.1G2545...

  • Page 63: Display System Information

    Base-520(G) Installation OpenBoot Firmware The system responds by incrementing a number once a second. Press any key to stop the test. Network To monitor the network connection enter: ok watch-net Internal loopback test -- succeeded. Transceiver check -- Using Onboard transceiver -- Link Up. passed Using Onboard transceiver -- Link Up.

  • Page 64: Reset The System

    OpenBoot Firmware Base-520(G) Installation 4.8.5 Reset the System If your system needs to be reset, you either press the reset button on the front panel or, if you are in the Forth Monitor, type reset on the command line. ok reset The system immediately begins executing the initialization procedures and executes the POST if having pressed the reset button.
  • Page 65 Base-520(G) Installation OpenBoot Firmware Example: How to get help for special Forth words or subcategories: ok help power reset-all reset-machine, (simulates power cycling ) power-off Power Off ok help memory dump ( addr length -- ) display memory at addr for length bytes fill ( addr length byte -- ) fill memory starting at addr with byte move ( src dest length -- ) copy length bytes from src to dest address map? ( vaddr -- ) show memory map information for the virtual address...
  • Page 66 OpenBoot Firmware Base-520(G) Installation Page 52 SPARC/CPCI-52x(G)

  • Page 67: O-52X(G) Installation

    I/O-52x(G) Installation Location Overview I/O-52x(G) Installation Location Overview The I/O-52x(G) contains the following main I/O interfaces: • SCSI #2, • Ethernet #2, • PMC #1 and PMC #2. SPARC/CPCI-52x(G) Page 53...

  • Page 68: Location Diagram Of The I/O-52X(G) (Schematic)

    Location Overview I/O-52x(G) Installation Figure 16 Location diagram of the I/O-52x(G) (schematic) PN 22 PN 24 PN 12 PN 14 PMC #1 connectors PMC #2 connectors PN 21 PN 11 SCSI #2 Ethernet #2 CPU and cache heatsink PHYceiver Front panel (1 slot high) PMC #2 PMC #1 CPU and cache...

  • Page 69: Mechanical Constructions

    I/O-52x(G) Installation Mechanical Constructions Mechanical Constructions The I/O-52x(G) is an extension to the Base-520(G). It occupies 1 CompactPCI slot and consists of the following major components: • 2 PMC connectors, • 1 SCSI #2 interface, • and 1 Ethernet #2 interface. The following figures show the SPARC/CPCI-52x(G) in 2-slot and 3-slot configurations.

  • Page 70: Installation/Deinstallation Of The I/O-52X(G)

    Mechanical Constructions I/O-52x(G) Installation Figure 19 Mechanical construction of the SPARC/CPCI-52xG (option) 2 PMC modules I/O-52xG in the 3rd slot MEM-50U MEM-50M CPU and cache with MEM-50M heatsink MEM-50L Base-520G in 1st slot 5.2.1 Installation/Deinstallation of the I/O-52x(G) This section describes the installation and deinstallation procedure for the I/O-52x(G) with the mentioned location shown in the figure below.

  • Page 71: Powering Up

    I/O-52x(G) Installation Powering Up Figure 20 Installation/Deinstallation of the I/O-52x(G) Base- I/O-52x(G) 520(G) I/O-52x(G) PMC#2 connectors PMC#1 connectors Standoff SCSI Ethernet CPU and cache heatsink PHYceiver Front panel Side view Top view Powering Up For powering up see the respective installation section of the Base-520(G).

  • Page 72: Ethernet #2 Interfaces

    Front Panel and Connectors I/O-52x(G) Installation On-board In addition to the front-panel connectors, the I/O-52x(G) provides on- connectors board connectors for connection to the Base-520(G), to the CompactPCI bus and for 2 PMC modules. An overview is shown in the following ta- ble.

  • Page 73: Pmc Slots

    I/O-52x(G) Installation Front Panel and Connectors Installation Guide. For the J5 connector pinout see figure 22 “CompactP- CI J5 connector pinout” on page 60. 5.4.2 PMC Slots The I/O-52x(G) provides 2 PMC slots compliant with IEEE P1386 ("Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards: PMC").

  • Page 74: Compactpci J4 Connector Pinout

    Front Panel and Connectors I/O-52x(G) Installation Figure 21 CompactPCI J4 connector pinout PMC #1 I/O 61 PMC #1 I/O 62 PMC #1 I/O 63 PMC #1 I/O 64 n.c. PMC #1 I/O 56 PMC #1 I/O 57 PMC #1 I/O 58 PMC #1 I/O 59 PMC #1 I/O 60 PMC #1 I/O 51...
  • Page 75 I/O-52x(G) Installation Front Panel and Connectors – and a Twisted-Pair-Ethernet cable for the front panel or the I/O panel. The I/O panel supports the following interfaces: • Fast/Wide SCSI #2, • MII #2 Ethernet, • and PMC user I/O. Danger The SPARC/IOBP-520/IO and the SPARC/CPCI-520/AccKit/IO is especially designed for the I/O-52x(G).

  • Page 76: Scsi #2 Configuration

    SCSI #2 Configuration I/O-52x(G) Installation SCSI #2 Configuration Note: Correct SCSI bus selection: The I/O-52x(G) provides a second SCSI bus, SCSI #2. Its configuration is described as follows. The I/O-52x(G)’s SCSI #2 bus is only available at the I/O-52x(G)’s CompactPCI J5 connector. Valid There is only 1 valid I/O-52x(G) SCSI #2 bus configuration: configuration...

  • Page 77: Openboot Firmware Alias Definitions For I/O-52X(G)

    I/O-52x(G) Installation OpenBoot Firmware Alias Definitions for I/O-52x(G) OpenBoot Firmware Alias Definitions for I/O-52x(G) This chapter describes additional features used with reference to the I/O-52x(G) enhancements. Table 27 Device alias definitions Alias Description Defined for SCSI #2: SCSI #2 scsi-2 disk SCSI #2-target-ID 6 disk26 disk SCSI #2-target-ID 5...
  • Page 78 OpenBoot Firmware Alias Definitions for I/O-52x(G) I/O-52x(G) Installation Page 64 SPARC/CPCI-52x(G)

  • Page 79: Hardware Description

    Hardware Description Hardware Description The SPARC/CPCI-52x(G) is a high performance CompactPCI board computer providing a CompactPCI system controller interface including DMA. It is based on • the UltraSPARC-IIi processor supporting 3 high-speed interfaces concurrently operating: – the memory interface with ECC –...

  • Page 80: Block Diagram Of The Sparc/Cpci-52X(G)

    Hardware Description Figure 23 Block Diagram of the SPARC/CPCI-52x(G) Base board Dual serial Audio (hdph, micro) EBus2 Serial I/O User flash Dual serial Boot flash Audio Audio (hdph,micro) Parallel Super-I/O NVRAM Floppy Keyboard/mouse Keyboard/mouse 10/100Base-Tx Ethernet #1 Ethernet #1 PCIO PHYceiver Ethernet #1 SCSI #1...

  • Page 81: Buses, Bus Modes, And Connected Devices

    Hardware Description The following table gives an overview of the different buses, their bus modes, and the connected devices. Table 28 Buses, bus modes, and connected devices Bus and bus mode Connected Devices EC bus, • UltraSPARC-IIi (see page 68) big endian •...

  • Page 82: Processor - Ultrasparc-Iii

    Processor – UltraSPARC-IIi Hardware Description Processor – UltraSPARC-IIi UltraSPARC-IIi is a highly integrated 64-bit SPARC V9 superscalar pro- cessor. The interfaces have been optimized to typical uniprocessor sys- tem requirements. Features • Binary compatible with all SPARC application codes • VIS instruction set •...

  • Page 83: Physical Memory Map

    Hardware Description Processor – UltraSPARC-IIi 6.1.1 Physical Memory Map Table 29 UltraSPARC-IIi physical address map (41-bit physical addresses) Address range in Addressed Size interface Access type PA<40:0> 1 GByte Main memory cacheable 000.0000.0000 …000.3FFF.FFFF reserved undefined cacheable 000.4000.0000 …1FF.FFFF.FFFF reserved undefined noncacheable 000.0000.0000...

  • Page 84: External Cache Control Unit

    Processor – UltraSPARC-IIi Hardware Description 6.1.2 External Cache Control Unit The UltraSPARC-IIi obtains an integrated L2 cache controller providing a backside interface with a 72-bit wide data bus and 150 MHz speed. The L2 cache capacity is either 256 KByte or 1 MByte. 3 synchronous late write SRAM devices (2 for data and 1 for the tags) are provided.

  • Page 85: Relating Memory Capacity To Device Type And Number Of Banks

    Hardware Description Processor – UltraSPARC-IIi Memory The main memory capacity is adjustable via installation of the appropri- modules ate memory modules. For naming conventions, see figure 6 “MEM-50 – memory module numbering scheme” on page 17. Table 31 Relating memory capacity to device type and number of banks Memory module Memory capacity Device type...

  • Page 86: Interrupt Map

    Processor – UltraSPARC-IIi Hardware Description 6.1.4 Interrupt Map Interrupt concept The UltraSPARC-IIi provides a 6-bit wide interrupt vector for 63 inter- rupt sources. A separate device, the UPA interrupt concentrator (UIC), provides the inputs for all necessary interrupts. The UIC monitors all in- terrupts by a round-robin-scheme with 33 MHz, converts them to an own vector and transmits this vector to the processor.

  • Page 87: Interrupt Sources From The I/O-52X(G)

    Hardware Description Processor – UltraSPARC-IIi Table 34 Interrupt sources from the I/O-52x(G) CPU internal CPU internal Function Device vector vector priority Ethernet #2 PCIO SCSI #2 SYM53C875 PMC1 #A PMC1 PMC1 #B PMC1 #C PMC1 #D PMC2 #A PMC2 PMC2 #B PMC2 #C PMC2 #D CompactPCI #A...

  • Page 88: Ultrasparc-Iii Pci Bus Interface

    Processor – UltraSPARC-IIi Hardware Description 6.1.5 UltraSPARC-IIi PCI Bus Interface The CPU uses a 66 MHz PCI bus as its bus for I/O extensions. This bus is 32 bits wide. Table 35 UltraSPARC-IIi PCI address space (8 GByte) Address range in PA<40:0>...

  • Page 89: Apb (Advanced Pci Bridge) And Compactpci Interface

    Hardware Description APB (Advanced PCI Bridge) and CompactPCI Interface APB (Advanced PCI Bridge) and CompactPCI Interface The APB (Advance PCI Bridge) is a PCI-to-dual-PCI bus bridge and is assembled on the base and on the I/O board (see figure 23 “Block Dia- gram of the SPARC/CPCI-52x(G)”...

  • Page 90: Ethernet Interface - Pcio

    Ethernet and EBus2 Devices – PCIO Hardware Description • Expansion bus 2 interface (EBus2), supporting up to 8 external devices and 4 buffered slave DMA channels. 6.3.1 Ethernet Interface – PCIO The PCIO on the Base-520(G) delivers the Ethernet #1 interface and the PCIO on the I/O-52x(G) delivers the Ethernet #2 interface.

  • Page 91: Ebus2 Interface - Pcio

    Hardware Description Ethernet and EBus2 Devices – PCIO 6.3.2 EBus2 Interface – PCIO The PCIO also provides the interface to the EBus2. EBus2 is a generic slave 8-bit wide DMA bus (pseudo ISA bus) to which off-the-shelf pe- ripherals can be connected. Base addresses The base addresses of all 8 PCIO chip select signals in the 4 GByte PCI of PCIO chip...

  • Page 92: Pcio Ebus2 Dma Channels

    Ethernet and EBus2 Devices – PCIO Hardware Description Table 37 EBus2 memory map in the PCI bus 4 GByte address space (cont.) EBus_ PCI addr. range Description reserved F110.0000 …F11F.FFFF “Audio Interface – CS4231A” on page 84 F120.0000 …F12F.FFFF “Keyboard/Mouse, FDC and Parallel Interface – Super I/O” F130.0000 …F13F.FFFF on page 81...

  • Page 93: Boot Prom, Boot And User Flash Eprom

    Hardware Description Ethernet and EBus2 Devices – PCIO 6.3.3 Boot PROM, Boot and User Flash EPROM The PCIO’s 16-MByte chip select signal EBus_CS#0 is decoded to 3 chip select signals for • 1 boot PROM device or 1 boot flash EPROM device (2 MByte address space).

  • Page 94: Serial Interfaces - Sab 82532

    Ethernet and EBus2 Devices – PCIO Hardware Description Table 39 Boot and user flash address space configuration PCI addr. range Configuration Device type F000.0000 Default config. with SW6-2 = OFF in 1 MByte boot PROM …F00F.FFFF case of 4-MByte user flash fact. opt. one 27C080, 1Mbx8 read-only device 4 MByte user flash EPROM...

  • Page 95: Keyboard/Mouse, Fdc And Parallel Interface - Super I/O

    Hardware Description Ethernet and EBus2 Devices – PCIO • Protocol support (HDLC/SDLC) • Interrupt controlled 6.3.5 Keyboard/Mouse, FDC and Parallel Interface – Super I/O To implement a major part of the UltraSPARC-IIi architecture’s I/O-sub- system a standard PC Super I/O device is utilized, the Super I/O – PC87332VLJ at PCI bus base address F130.000016 on the EBus2.
  • Page 96 Ethernet and EBus2 Devices – PCIO Hardware Description Parallel interface The parallel interface is Centronics compatible. One of the 4 DMA chan- nels of the PCIO EBus2 is used for the Super-I/O parallel interface (see table 38 “PCIO EBus2 DMA channels” on page 78). •...

  • Page 97: Rtc/Nvram - M48T58

    Hardware Description Ethernet and EBus2 Devices – PCIO 6.3.6 RTC/NVRAM – M48T58 The Base-520(G) provides a RTC/NVRAM – M48T58 at PCI bus base address F100.000016 on the EBus2. Table 40 Address map of the RTC/NVRAM Address offset range Access NVRAM with 8 KByte minus 8 bytes capacity 0000 …...

  • Page 98: Audio Interface - Cs4231A

    Ethernet and EBus2 Devices – PCIO Hardware Description 6.3.7 Audio Interface – CS4231A The Base-520(G) provides an Audio Controller – CS4231A at PCI bus base address F120.000016 on the EBus2. 2 DMA channels of the PCIO EBus2 are used for the audio interface (see table 38 “PCIO EBus2 DMA channels”...

  • Page 99: System Configuration Registers - Scr

    Hardware Description Ethernet and EBus2 Devices – PCIO 6.3.8 System Configuration Registers – SCR The Base-520(G) implements a set of system configuration registers via a field programmable gate array XC4003E (FPGA Xilinx LCA) at PCI bus base address F160.000016 on the EBus2. The table below gives an overview of all SPARC/CPCI-52x(G) system configuration registers: Table 41 System configuration register set (SCR), all 8-bit wide...

  • Page 100: Scr: Front Panel And Switches

    Ethernet and EBus2 Devices – PCIO Hardware Description Table 42 System Configuration Identification Register F160.000F Value ID (ro) ID indicates the hardware ID of the device containing the system config- uration registers. 6.3.9 SCR: Front Panel and Switches The following registers control front-panel or switch related features: •...

  • Page 101: 7-Segment Led Display Control Register

    Hardware Description Ethernet and EBus2 Devices – PCIO Table 44 7-Segment LED Display Control Register F160.0010 Value DP and SEG_G DP and SEG_G … SEG_A control the status of the decimal point (DP) … SEG_A (w) and the segments (SEG_G…SEG_A) in the hexadecimal display (see fig- ure below for naming conventions).
  • Page 102 Ethernet and EBus2 Devices – PCIO Hardware Description Page 88 SPARC/CPCI-52x(G)

  • Page 103: 6.3.10 Scr: Boot And User Flash

    Hardware Description Ethernet and EBus2 Devices – PCIO Table 46 SW4 and SW5 Status Register F160.0012 Value SW5-4 SW6-2 SW5-3 SW5-2 SW5-1 SW4-4 SW4-3 SWx-y (ro), SWx-y indicates the setting of the respective switch (see table 11 “De- except SW5-2 fault switch settings”...

  • Page 104: 6.3.11 Scr: Watchdog, Temperature Sensors, And Reset

    Ethernet and EBus2 Devices – PCIO Hardware Description Table 47 Boot and User Flash Size Control Register F160.0002 Value USERROM_SIZE BOOTROM_SIZE USERROM_SIZE and BOOTROM_SIZE indicate the decoding of the x ROM_SIZE (ro) user and boot flash EPROM, respectively. , 01 reserved = 00 Offset range 00.0000...

  • Page 105: Miscellaneous Control And Status Register

    Hardware Description Ethernet and EBus2 Devices – PCIO – is cleared (0) whenever the current temperature exceeds an upper temperature limit (T ) or falls below a lower limit (T HYST – is set (1) only upon reading one of the temperature sensor’s inter- nal registers via the I C-Bus.

  • Page 106: Reset Status Register

    Ethernet and EBus2 Devices – PCIO Hardware Description IP_TEMP (ro) IP_TEMP indicates whether one of the 2 temperature sensors signals an alarm condition. Only if enabled via appropriate setting of IE_TEMP, an interrupt is generated. No temperature control interrupt is pending. A temperature control interrupt is pending.

  • Page 107: Miscellaneous Control Register

    Hardware Description Ethernet and EBus2 Devices – PCIO Once one of the bits has been set to 1, it is cleared (0) by setting RESET_STAT_CLR in the Miscellaneous Control Register (see page 93). KEY_RESET indicates that a reset has been generated via the front-panel KEY_RESET (ro) reset key if KEY_RESET = 1.

  • Page 108: 6.3.12 Scr: Enum Interrupt

    Ethernet and EBus2 Devices – PCIO Hardware Description 6.3.12 SCR: ENUM Interrupt Note: All SPARC/CPCI-52x(G) variants provide the ENUM #1 interrupt since this is the ENUM interrupt of the CompactPCI interface related to the base board of the SPARC/CPCI-52x(G). However, note that in case of using the I/O-523G and only in this case, there is a second ENUM interrupt related to the CompactPCI interface of the I/O board: ENUM #2.

  • Page 109: Scr: I C-Bus

    Hardware Description Ethernet and EBus2 Devices – PCIO 6.3.13 SCR: I C-Bus The SPARC/CPCI-52x(G) is equipped with an I C bus consisting of a data line and a clock line which are software-controlled. For further infor- mation on the I C Bus, refer to the I C Bus specification.

  • Page 110: I 2 C Bus Control And Status Register

    See I2C_SDAO for information how to write data to I C Bus slaves. See I2C_SDAI for information how to read data from I C Bus slaves. I2C_SDAO is used to force low (0) or high (1) level on the I C Bus data I2C_SDAO (r/w) line.

  • Page 111: Scsi Interface - Sym53C875

    Hardware Description SCSI Interface – SYM53C875 SCSI Interface – SYM53C875 Ultra/wide SCSI #1 and #2 (single-ended) are implemented on the Base-520(G) and on the I/O-52x(G) (SCSI), respectively. Ultra SCSI (Fast-20) is an extension of the SCSI-3 standard that expands the band- width of the SCSI bus and allows faster synchronous SCSI transfer rates (approximately double the synchronous transfer rates of Fast SCSI-2).

  • Page 112: Pmc Slots With Busmode Support

    PMC Slots with Busmode Support Hardware Description PMC Slots with Busmode Support The PMC busmode signals are supported for both PMC slots via 5 gener- al purpose I/O pins of the SCSI #2 controller on-board the I/O-52x(G) (see section 6.4 “SCSI Interface – SYM53C875” on page 97). The bus- mode signals allow detection of installed PMC cards and proper initial- ization of the PMC card according to the protocol supported by the installed PMC module.

  • Page 113: Pmc#X Busmode[1] (Ro) Response Encoding

    Hardware Description PMC Slots with Busmode Support Table 58 PMC# x BUSMODE[1] (ro) response encoding PMC# x Description BUSMODE[1] “Card Present”: PMC module present which has the requested capability and uses the requested protocol no PMC module present or PMC module does not have the requested capability or PMC module does not use the requested protocol SPARC/CPCI-52x(G)
  • Page 114 PMC Slots with Busmode Support Hardware Description Page 100 SPARC/CPCI-52x(G)

  • Page 115: Force Openboot Enhancements

    OpenBoot versions are marked with the version given, e.g..(OpenBoot 3.10.4 and above) ..For information on the latest OpenBoot version and how to upgrade refer to the SMART service accessible via the FORCE COMPUTERS World Wide Web site. Base information For a description of standard OpenBoot 3.x firmware features, see the...

  • Page 116: System Configuration

    System Configuration FORCE OpenBoot Enhancements System Configuration This section consists of the following parts: • section 7.1.1 “System Configuration Register Accesses” on page 102, • section 7.1.2 “LEDs, Seven Segment Display and Rotary Switch” on page 106, • section 7.1.3 “ID PROM” on page 107, •...
  • Page 117 FORCE OpenBoot Enhancements System Configuration user-rom-size-ctrl! ( byte — ) stores the 2-bit data in the User ROM Size Control Register. led-display@ ( — byte ) returns the contents – an 8-bit data – of the LED Display Con- trol/Status Register. Since the LED Display Control Register is only writ- able, the command returns the contents of the LED Display Control Shadow Register.
  • Page 118 System Configuration FORCE OpenBoot Enhancements connected to the front panel. Otherwise, the SCSI front panel termination is disabled. scsi_bp@ ( — true | false ) returns the state of the SCSI Backplane Termination Switch (SW5-2). The SCSI backplane termination is disabled if true is re- turned.
  • Page 119 FORCE OpenBoot Enhancements System Configuration ENUM#2 interrupt is pending if true is used with this command. In that case an interrupt is generated to the processor provided that the ENUM#2 interrupt is enabled by the ENUM#2 Interrupt Enable Register. This sig- nal is low level sensitive.

  • Page 120: Leds, Seven Segment Display And Rotary Switch

    System Configuration FORCE OpenBoot Enhancements 7.1.2 LEDs, Seven Segment Display and Rotary Switch The commands described below are available to control the seven seg- ment LED display, the user LEDs, as well as to get information about the state of the rotary switch.

  • Page 121: Id Prom

    FORCE OpenBoot Enhancements System Configuration ter using this command. rotary-switch@ ( — byte ) returns the current state of the rotary switch. The value of byte may be one of the values in the range 0…15. 0 corresponds to posi- tion 0 of the rotary switch, 1 corresponds to position 1, and so forth.

  • Page 122: Viewing The Switch Status And Controlling The Temperature Sensors

    System Configuration FORCE OpenBoot Enhancements addr = 0 …511. mem>idprom ( src-addr dest-addr size — ) copies a number of bytes from the on-board memory to the ID PROM selected via select-idprom. The number of bytes to be copied is specified by size, size = 1 …512. The source data start at the virtual address src-addr in the on-board memory.

  • Page 123: Pci-Probing - Nvram Configuration Variables

    FORCE OpenBoot Enhancements System Configuration set-conf ( byte sensor# — ) stores the value byte in the configuration register of the tem- perature sensor specified by sensor#, sensor# = 1, 2. The contents of the status register data is left on the evaluation stack.

  • Page 124: Flash Eprom Support

    111). This allows to program the user flash with an executable image and use the FORCE OpenBoot enhancements to load and execute such an image from user flash (see section 7.2.3 “Loading and Executing Programs from User Flash EPROM” on page 115). For general information on NVRAM configuration parameters and methods available for flash EPROM, see section 7.2.2 “Flash EPROM Device Node”...
  • Page 125 FORCE OpenBoot Enhancements Flash EPROM Support select-flash ( USER | BOOT — ) selects the flash EPROM to be programmed and pre- pares the selected flash EPROM for programming. No further words may follow in the same command line (see “Example: Programming the User Flash”...

  • Page 126: Flash Eprom Device Node

    Flash EPROM Support FORCE OpenBoot Enhancements select-flash informs the user that the user flash EPROM has been made accessible. It displays the available boot flash EPROM and user flash EPROM. After the user flash has been selected, all following commands oper- ate on the user flash.
  • Page 127 FORCE OpenBoot Enhancements Flash EPROM Support After selecting the flash EPROM device node, the word words displays the names of the methods of the flash EPROM device. ok words close open selftest reset load write-blocks read-blocks seek write read max-transfer block-size To unselect the current device node, i.e.
  • Page 128 Flash EPROM Support FORCE OpenBoot Enhancements read ( addr length — actual ) reads at most length Bytes from the flash EPROM and copies it to memory beginning at address addr. If actual is 0 or negative, the read failed. The value of length can be chosen independently of the de- vice’s block size.

  • Page 129: Loading And Executing Programs From User Flash Eprom

    FORCE OpenBoot Enhancements Flash EPROM Support 7.2.3 Loading and Executing Programs from User Flash EPROM Besides the ability to load and execute an executable image from disk, from a network component, or from other components, the SPARC/CPCI-52x(G) OpenBoot also provides a convenient way to load and execute an executable image from available user flash EPROM.

  • Page 130: Hardware Dependencies

    Hardware Dependencies FORCE OpenBoot Enhancements Hardware Dependencies Note: To make use of the features described in this section proceed as follows: • copy the OpenBoot image from the boot PROM which is a read-only device to the boot flash EPROM (see section 7.3.1 “Copying the OpenBoot Image from Boot PROM to Boot Flash EPROM”...
  • Page 131 FORCE OpenBoot Enhancements Hardware Dependencies Note: In case of an error during one of the 2 following procedures proceed as follows: • select booting from the boot PROM, • reset the system, • and try again. 1. version: To copy the OpenBoot image from the boot PROM into the boot flash OpenBoot 3.10.4...

  • Page 132: Drop-In Drivers

    Hardware Dependencies FORCE OpenBoot Enhancements The OpenBoot image is copied from the boot PROM into the boot flash EPROM. To operate the CPU board, install the CPU board with the boot flash EPROM used for subsequential booting by setting SW6-2 to ON.
  • Page 133 SYSTEMS HARDWARE SOFTWARE SYSTEMS ERROR DESCRIPTION: THIS AREA TO BE COMPLETED BY FORCE COMPUTERS: DATE: PR#: RESPONSIBLE DEPT.: MARKETING PRODUCTION ENGINEERING BOARD SYSTEMS Send this report to the nearest Force Computers headquarter listed on the back of the title page.

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