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Summary of Contents for Bruker AQS
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Communication Control Unit CCU 9/10 AQS/AQX Technical Manual Version BRUKER...
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The information in this manual may be altered without notice. BRUKER accepts no responsibility for actions taken as a result of use of this manual. BRUKER accepts no liability for any mis- takes contained in the manual, leading to coincidental damage, whether during installation or operation of the instrument.
1. Starting with CU09/10 1. 1. Special features of CU09/10 CU09/10 provides the same devices and connectors as CU08 except the console connec- tor which has been changed to the same type as on Indy (Mini D, 8 pin). Therefor, the CU08–Indy Console Cable can be used in reverse direction to connect CU09/10 to O2.
replace the AUI/10Base2 ”Micro Transceiver” by an AUI/10BaseT ”Micro Transceiver”, Part# O00744 which fits to the cable. The Fast Ethernet will adjust itself to the 10 MHz speed of the Indy. The console interface of CU09/10 can be connected to the Indy by the Console cable Part# HZ10091.
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Workaround Swap logically both ethernet devices of the O2. That means, connect the to ether- spect net controller on the motherboard of the O2. This can easy be carried out by modify- ing the file netif.options Type on O2 as superuser: vi /etc/config/netif.options This file contains the 2 parameter entries of .
The AQS_CCU is a CPU board specially designed for use in the new AQS–Rack. CCU version CU10 is based on the CU09 hardware and have the same features but with the addition it contains a new extended AQS Bus System. Therefor, can be not used in the old AQX System Rack.
(”tty01,...,tty09”) at the front edge) real time clock MK48T02 with 2 kbyte non volatile memory configuration register, status register, interrupt register component identification channel to handle the AQX/AQS component identification system (CIS) JTAG Boundary–Scan controller brings the JTAG test bus to the Backplane.
CU09 PAL set H5834 Front–Panel Assembly Set Hz0548 Front–Panel–Ident ”CCU/9” Hz3954 2. 6. Part numbers of AQS CU10 P/N H9503 AQS_CCU Assembled PCB H9503 PCB Layout H3P2380 Plain PCB H9504 CU10 PAL set H9505 Front–Panel Assembly Set Hz06237 Front–Panel–Ident ”CCU/10”...
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SCSI Cable P/N 73104 Connecting to RS232/RS485 of CU10 The RS485 Channels (tty10 and tty20) are only avalable at the AQS Backplane, Connec- tor X3. Connecting the RS232 Channels ”tty01,...tty09” to the separate Sub–D–9 Connectors the following parts can be used (see Figure 4: )
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Connecting to the Console CU09/O2 console cable 10m P/N HZ04161 This is the CU08/Indy console cable which can be used for CU09 in reverse direc- tion. CU09/Terminal console cable 3m P/N HZ04112 This cable was originally designed to connect a plotter to the Indy. Connecting to Fast Ethernet 10–MBit Mini Hub, Part# O001114 Fast Ethernet Cable Types...
2. 8. Controls and Indicators Reset Button The general hardware reset signal of CCU and VME–Bus can be initiated by pushing the ”Reset Button”. It stays active for about 80 milliseconds. Activity LED’s The 4 digit LED–Display forms a hexadecimal coded value with MSB at the left side. Lighting re- flects a logical ”One”.
R4600 vendor=BRUKER rootname=0 use_bootparams=1 keyswtch=0 keyboard=AT This procedure takes a few minutes. The monitor prints a test protocol and at last its prompt ( ) on which is the default >>...
NVRAM, you have only the chance to insert it into a running CCU without powering off and set the parameters to their correct values or clear to an other value than magic RISCPROM The monitor uses tty0 as console. This is the default value if and the monitor initial- magic...
Installed type of firmware Prom’s A choice out of 2 types is possible, 2 devices in PLCC–Package are re- quired. W11 removed: 272048 may be used resulting in 512 kbyte W11 inserted: 274096 can be used resulting in 1 megabyte firmware space Access time is required to be 120 nsec or less SYSCLK on VME Bus...
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ST7 ”Console” (tty00) RS232–Connector Fast Ethernet signal assignment at the RJ45–8 connectors The twisted pair Ethernet requires a category 5 (CAT5) unshielded twisted–pair (UTP), 2–pair cable for a 100BASE–TX network connection or a category 3 (CAT3), or higher UTP cable for a 10BASE–T network connection. The standard twisted–pair cable has a straight–through pin to pin connection from plug to plug.
2. 11. Power Requirements The CU09 requires power supply of the following voltages: H2570 5,3 A 0,3 A 0,1 A H9503 CU09 supplies fused current at the following connectors: ST8/9 RS485 +12 Volt 0.2 Ampere The resistance of the fuse will be suddenly growing with temperature caused by high cur- rent.
All connections can be carried out as on CU09 with the exception of the RS485 interface that is now available on the AQS backplane. The BNC cable of the Thin Wire Ethernet (10Base2) should be left unconnected. 10Base2 is considered to be obsolete on CU10 and no longer available.
To Indy The Fast Ethernet will adjust itself to the 10 MHz speed of the Indy. To Aspectstation The LINK Led (2. led from left in upper row) shows a good link status after power up. Otherwise one of the two link partners is down by software or power. The Fast Ethernet cable can be pulled out and plugged in under power and activity.
depending on the interface to which the is connected to. spect 3. 4. Problems of Point–to–Point Connection to the O2 Both link partners of a Fast Ethernet Connection exchange their abilities (10 or 100 MBit and Half or Full Duplex) after power up and without software interaction. They decide then for the fastest common possibility.
The Ethernet address consists of 12 hexadecimal digits. The 6 leftmost ones are the constant Bruker Code, the 2 rightmost ones identify a special group of Bruker devices. The rest of them build the consecutively numbered ethernet address of each device.
0000ad 0000 0000ad 0000 0000ad 0000 3. 7. Introduction Status of the AQX CU09 CCU 3. 7. 1. Modifications of the introduced layout There are 25 prototypes of CU09 using layout H3P2160C with some modifications. The PCB layout put into production is H3P2160D without any modification. 3.
3. 8. Introduction Status of the AQS CCU10 3. 8. 1. Modifications of the introduced layout The new AQS CCU CU10 board contains the same functions as the previous CU09 P/N H2570 excepted the middle J0/ST2 connector for the backplane which has been changed . Addi- tionally, the RS485 interface is connected to the J0/ST2 connector and now available on the backplane X3 connector.
3. 8. 3. Configurations of the introduced layout CCU configuration of Serial Interfaces: Pin out of the X3 connector at the AQS backplane : TxD–/+ 1, RxD–/+ 1, WUP 1 TxD–/+ 2, RxD–/+ 2, WUP 2...
1o––––o2 3o––––o4 3o––––o4 Note: Any installed DRAM module is not available if jumper W7 is removed The new CCU version need following software Boot PROM version: 970611 Diskless version: 970501 included XWIN NMR 2.0 re- lease 3. 8. 3. 1. NVRAM The way how you can set the NVRAM parameters to the right value depends on the value of its parameter ”magic”.
R4600 vendor=BRUKER rootname=0 use_bootparams=1 keyswtch=0 keyboard=AT 3. 8. 3. 2. Firmware CU09/10 needs the firmware version 97/05/01 or later. It is put into production with ver- sion 97/06/11. This version declares CU09/10 during autonegotiation as being able to send in half duplex mode only.
H3P2160D 2455 12.1.98 H2570 Correct Part List to the originally used Clock 2331 driver with CMOS signal level IDT49FCT805ASO20–2 3. 10. AQS CU10 CCU History of Modifications 2482 19.6.98 H9503 Introduction of AQS CCU CU10 Layout ver- 0010 sion H3P2380...
4. Condensed technical Description 4. 1. Architecture The CCU is build out of three Units : Processor . Memory L_bus incorporating 1. The ETHERNET and the Fast–ETHERNET interface, which can be a Master on the L–bus and can access only the Memory. 2.
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fast Init & Clock circ. VME int. Ethernet Ethernet Power up Resets Boot Clocks Processor PCI bus Interface R 4700 Processor Addr. reg. Addr. reg. 32 <> 16 Addr. reg. ( Orion ) R/T Clock SysA(4..0) Sys Cmd (8..0) Data reg. Buffer A(4..2) Int(4..0)*...
4. 2. Logical References to memory and I/O devices Access Characteristics Depending on configuration, the cpu can work in big or little endian mode. For independence the operands within io–device code ranges should be referred to as word (32 bit) operands with the valid bytes indi- cated by ”b”...
4. 2. 1. Firmware The reserved firmware range is 8 mbyte. The firmware memory is 32 bits wide, containing 2 Mbyte from address 1FC00000 to 1FDFFFFF. It consists of 2 devices, 16 bits wide each. 4. 2. 2. Flash EPROM The reserved Flash firmware range is 4 mbyte.
1E89xxxx 1E8Axxxx 1E8Bxxxx 1E8Cxxxx 1E8Dxxxx 1E8Exxxx 1E8Fxxxx 4. 2. 4. 2. Slave Port VME bus accesses can reach only the on board DRAM addresses via this port. The address range depends on the installed volume and starts always with VME bus address 0x0.
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can work in big or little endian mode supports byte, word and longword accesses supports DMA bursts of up to 32 longwords The DEC 21140A Fast Ethernet LAN Controller is mapped into I/O address space. Configuration Register Device Codes 1F080000 bbbb 00091011 1F080004...
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1F090040 bbbb 00000000 1F090048 bbbb FFF097F0 1F090050 bbbb undefined 1F090058 bbbb FFFE0000 1F090060 bbbb FFFFFEXX 1F090068 bbbb undefined 1F090070 bbbb undefined 1F090078 bbbb FFFFFEC8 The chip is a Physical Layer device for Ethernet 10BASE–T and 100BASE–X using category 5 Unshielded, Type 1 Shielded and Fiber Optic cables The chip interfaces the PMD sublayer through DP82223 Twisted Pair Transceiver to the MAC layer 21140A through a Media...
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1Dh–1Fh Differences between DP83840 and 83840A 15:0...
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Differences between DP83840 and 83840A in full duplex mode 07h–0fh 10h–11h...
1Dh–1Fh 4. 2. 7. RS232 Interface Notes The RS232/RS485 Interfaces reside in six Z85C230 providing 12 sepa- rate channels. Channel A is intended to be the ”console”, channel B to L to be ”tty01”, ”tty02”,..., ”tty09”,”tty10”,”tty20” tty10 and tty20 are configured as RS485 channels The frequency of PCLK at pin 23 of Z85C230 is 10 MHz Device Codes 1F020xxx...
1F039xxx 1F03Axxx 1F03Bxxx 1F03Cxxx 1F03Dxxx 1F03Exxx 1F03Fxxx 4. 2. 8. JTAG Interface The JTAG Interfaces is based on SCANPSC100F National Embedded Boundary Scan Controller. It is 8 bits wide parallel interface, and mapped in to 1F0A0000 – 1F0A3FFF address region. JTAG submodul is compatible with IEEE 1149.1 JTAG Standard Test Access Port and Boundary Scan Architecture.
1F0A0014 1F0A0014 1F0A0018 1F0A0018 1F0A001C 1F0A001C 4. 2. 9. Real Time Clock and NVRAM Notes The MK48T02 of SGS–Thomson is installed to implement these two functions by one device. It is a 2K–Byte–Static–RAM with its eight upmost cells being reserved as hold register for the real time clock information.
1F007FEx 1F007FFx 4. 2. 10. Configuration and Status Register Notes There are 4 configuration register and 1 status register. Each of them is 8 bit wide. Each configuration register provides two hexadecimal digits indicating the version of two individual onboard subsystems as follows: A subsystem is not available if the respective digit equals to zero.
Write access stores the upper 4 bits (D7,...,D4) of the transferred byte to the 4Bit–Led– Register. D3, D2 and D1 control the serial bus lines SDA, SCLK and ACLK. Leftmost Right- SCLK ACLK at front edge most at J1/B21 at J2/B3 at J1/B22 TMP_IN VME bus...
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RS_INT1 is interrupt of Channel C and D RS_INT2 is interrupt of Channel E and F RS_INT3 is interrupt of Channel G and H RS_INT4 is interrupt of Channel I and J RS_INT5 is the output of Z85C230, Channel K and L JTAG_INT JTAG interrupt, connected to pin 19 of the SCANPCS100F...
1F042xxx 1F043xxx 1F044xxx 1F048xxx 4. 2. 12. CIS access The information EEPROM of the Component Identification System is connected to the CCU con- trolled CIS channel. The EEPROM of all CCU’s have one and the same unique address out of all possible channel addresses as follows:...
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