Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Summary of Contents for Corelis PCIe-1149.1
- Page 1 CORELIS PCIe-1149.1 PCIe-1149.1 High-Speed PCI Express Bus Boundary-Scan Controller User’s Manual Document Part Number: 70369 REV B Copyright 2006 - 2007 Corelis Inc. 12607 Hidden Creek Way Cerritos, CA 90703-2146 Telephone: (562) 926-6727 • Fax: (562) 404-6196...
- Page 3 All rights reserved. No part of this document may be reproduced or translated to other languages without the prior written consent of CORELIS. CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is not furnished by CORELIS. ENVIRONMENTAL NOTICE This product must be disposed of in accordance with the WEEE directive.
-
Page 4: Product Warranty
PRODUCT WARRANTY This CORELIS product has a warranty against defects in material and workmanship for a period of 90 days from date of shipment. During the warranty period, CORELIS will, at its option, either repair or replace products that prove to be defective. -
Page 5: Table Of Contents
CHAPTER 3 CONNECTING TO THE TARGET ............3-1 Connecting to the Target..........................3-1 20-Pin ScanTAP Connector ........................3-3 68-pin Host Connector..........................3-4 PCIe-1149.1 Parallel I/O Connectors......................3-5 CHAPTER 4 USING PCIE-1149.1 WITH SCANPLUS ..........4-1 Hardware Setup............................4-1 Using PCIe-1149.1 with ScanPlus Tools....................4-1 ScanTAP-4 TAP Configuration .........................4-5 TAP Configuration - Method 1........................4-6 TAP Configuration - Method 2........................4-8... - Page 6 APPENDIX B SELF TEST UTILITY SOFTWARE ............1 Self-Test................................ 1...
- Page 7 Figure A-6. 20-pin TAP Connector Schematic for SPI....................10 Figure A-7. 20-pin TAP Connector Schematic for I2C ....................11 Figure B-1. Self-Test Result for the PCIe-1149.1 when the ScanTAP-4 is NOT connected .........2 Figure B-2. Self-Test Results for the PCIe-1149.1 with the ScanTAP-4 Connected.............3...
- Page 8 Table 4-2. ScanPlus Runner Naming Conventions....................4-8 Table 4-3. ScanPlus Runner Naming Conventions for Gang Programming ............4-13 Table 4-4. ScanPlus Runner ScanTAP-4 Configuration..................4-19 Table 5-1. PCIe-1149.1 Controller Parameters ....................... 5-2 Table A-1. Signal Description and Termination......................2 Table A-2. Standard 10-Pin TAP Connector ........................2 Table A-3.
-
Page 9: Chapter 1 Product Overview
ScanTAP-4, ScanTAP-8 or ScanTAP-32. The PCIe-1149.1 is shown in Figure 1-1. Figure 1-1. The Corelis PCIe-1149.1 Boundary-Scan Controller The most popular Intelligent Pod is the ScanTAP-4. It connected to the PCIe-1149.1 card via a standard SCSI-II cable and it provides up to 4 independent TAP connectors with a programmable low-voltage-compatible interface. -
Page 10: What Is Ieee Standard 1149.1
The JTAG interface also enables programming target Flash and CPLD devices, as well as downloading and uploading of data blocks to and from various storage devices. Application software for the PCIe-1149.1 is sold separately. What Is IEEE Standard 1149.1? The IEEE Standard 1149.1 test bus and boundary-scan architecture enable control of an IC, board,... -
Page 11: Features Of The Pcie-1149.1
The PCIe-1149.1 contains several performance enhancing functional sections aimed at increasing test vector throughput. A functional block diagram of the PCIe-1149.1 is shown in Figure 1-3. Key functional elements include the TAP controller, and the memory resources that support it. The on- board memory provides scan data storage and can store the entire scan data for maximum performance, real-time scan operations. -
Page 12: Adjustable Voltage Interfaces
This accommodates the returned target scan stream delays due to signal travel time down and up the cables. It can also adjust for a target’s on-board TCK-to-TDO response delay. An auxiliary feature of the PCIe-1149.1 is the target power-shorted detector for two voltages sense target interface pins. -
Page 13: Programmable Clocks
68-pin SCSI II type HOST connector. No external power supply is required—the PCIe-1149.1 card supplies it. Differential signal driving supports cables of up to 30 feet. Automatic delay mechanisms compensate for transport delays through the cable. The four TAPs are individually configurable for interface voltages from 1.25 to 3.3 V. -
Page 14: Pcie-1149.1 Specifications
34-pin header (3M part no. 2534-6002UB or equivalent) Power Requirements (from host expansion bus) 3.3 V 1.5 Amps maximum On-board Fuse (feeds power from PCIe-1149.1 to external pod) 1.5 Amp, SLO-BLO Littelfuse part number 045401.5 Operating Environment Temperature 0C to 55C... -
Page 15: Scantap-4 Specifications
Number of TAPs Maximum TCK frequency 80 MHz (Concurrent scanning at all TAPs occurs at up to the full TCK rate capability of the PCIe-1149.1) Maximum scanning data length unlimited Programmable Interface Voltage 1.25 to 3.3 V in 0.05 V increments... -
Page 16: Table 1-3. Scantap-4 Spi Interface Dc Characteristics
SPI Interface - available on ScanTAP-4 units P/N 10302A or later (with blue power-on LED) SCK frequency 1 MHz Signal DC Characteristics See Table 1-3: Symbol Test Conditions Limit Min Limit Max Units Vdd Adjust >= 2.5 V Vdd + 0.5 Vdd Adjust <... -
Page 17: Table 1-4. Scantap-4 I2C Interface Dc Characteristics
I2C Interface - available on ScanTAP-4 units P/N 10302A or later (with blue power-on LED) The ScanTAP-4 I2C interface has open-drain outputs and the SDA/SCL signals must be pulled up to 3.3V ( ) by the target. SCL frequency 100 kHz Signal DC Characteristics See Table 1-4: Symbol... - Page 18 Power Short Test Pins Power (Vcc) Sense Pins 2 per TAP connector (Vcc1, Vcc2), 8 total Vcc Measurement Type Short to GND detect, Target un-Powered, Voltage sense/measurement of +/- 50 VDC Voltage Sense Resolution 12-bit ADC Voltage Sense Accuracy +/- 50 mV Physical Box Outline Dimensions 4.00 in.
-
Page 19: Chapter 2 Pcie-1149.1 Installation
PCIe-1149.1 User’s Manual Ensure all materials listed are present and free from visible damage or defects before proceeding. If anything appears to be missing or damaged, contact Corelis at the number listed on the front cover immediately. The ScanTAP-4 typically consists of the following components: ... -
Page 20: Software Installation First
PCIe-1149.1 the first time it is detected in your system. WARNING ! You MUST install the software first – before installing the card. Do not install the PCIe-1149.1 card until you have successfully installed the application software (ScanPlus, CodeRunner, etc.). -
Page 21: Hardware Installation
Disconnect the PC power cord from the power source and then remove the enclosure cover from the PC. Plug the PCIe-1149.1 board into the PC in an available full height PCI Express slot. Use a screw to firmly attach the PCIe-1149.1 card bracket to the PC chassis. - Page 22 PCIe-1149.1 Installation...
-
Page 23: Connecting To The Target
Chapter 3 Connecting to the Target Connecting to the Target The connection to the user target (UUT) board/system is done from the ScanTAP-4 Intelligent Pod TAP connectors to mating connectors on the target. The ScanTAP-4 connects to the target via the supplied 1:1 TAP flat cables, P/N 15310, 15311 or 15312. - Page 24 To accommodate target boards with TAP connectors other than this standard, Corelis offers short, custom adapter cables for connectors such as the Altera ByteBlaster connector, the Xilinx 9 pin header, the Lattice TAP connector or the TI 14 pin DSP connector)
-
Page 25: 20-Pin Scantap Connector
20-Pin ScanTAP Connector The ScanTAP-4 contains four 20-pin TAP connectors. All four connectors have the same signals and the same pinout. Each connector is a shrouded header (0.100 × 0.100 in. spacing) with long ejectors that are compatible with standard 20-pin IDC flat cable connectors (with strain relief). The pin assignment is shown in Table 3-1. -
Page 26: 68-Pin Host Connector
The ScanTAP-4 comes standard with 4 short cables that connect it to a target system with up to 4 TAP connectors. These 20-pin to 10-pin cables, Corelis P/N 15310, are standard flat cables and can easily be made from off-the-shelf connectors. Each cable mates with a matching 10-pin header on the target system. -
Page 27: Pcie-1149.1 Parallel I/O Connectors
PCIe-1149.1 Parallel I/O Connectors The parallel output port connector (P2 on the PCIe-1149.1) is a 34-pin connector that includes all of the signals for the parallel output ports A and B. The connector is located near the top of the card. -
Page 28: Table 3-4. Connector P1 Parallel Input Pin Assignment
The parallel input port connector (P1 on the PCIe-1149.1) is a 34-pin connector that includes all of the signals for the parallel input port. The connector is located near the top of the card. The pin- out of the P1 connector is shown in Table 3-4. -
Page 29: Chapter 4 Using Pcie-1149.1 With Scanplus
Using PCIe-1149.1 with ScanPlus Hardware Setup You must configure the PCIe-1149.1 controller in a ScanPlus application before the application can use it. This chapter uses ScanPlus Runner as an example to illustrate the configuration process. Using PCIe-1149.1 with ScanPlus Tools The PCIe-1149.1 card is compatible with ScanPlus Runner, ScanPlus Debugger and ScanPlus Flash... -
Page 30: Figure 4-2. Pcie-1149.1 Setup Screen (But Scantap-4 Not Connected)
Select the PCIe-1149.1 controller from the icons on the left. Adjust the settings to the desired values. After you have made your selections, click on the Apply button to test and save the settings. When the program saves the settings successfully, it displays the controller in the Current Controller box. -
Page 31: Figure 4-3. Successful Pcie-1149.1 With Scantap Setup Screen
Once ScanPlus Runner finds the PCIe-1149.1 controller, with the ScanTAP-4 connected to it, it displays a screen similar to Figure 4-3 Note that saving the test plan (.tsp) file in ScanPlus Runner FILE menu also saves the settings in the system registry. The next time the .tsp file is loaded into ScanPlus Runner it will use these settings to initialize the controller. -
Page 32: Figure 4-4. Advanced Configuration Setup Screen
3.3 V setting for one TAP, 2.5 V for another, and 1.8 V for one or two additional TAPs. The Advanced Configuration screen is shown in Figure 4-4. Figure 4-4. Advanced Configuration Setup Screen Using PCIe-1149.1 with ScanPlus... -
Page 33: Scantap-4 Tap Configuration
This method is not recommended and will no longer be supported in future software releases. Method 3 Using the ScanPlus Runner tool Options menu. Use this method only when specific test step(s) require TAP configuration settings different from the global settings selected in Method 1 above. Using PCIe-1149.1 with ScanPlus... -
Page 34: Tap Configuration - Method 1
4 ScanTAP-4 TAPs to use for connecting to the target. This feature is available in all relevant ScanPlus Tools, including ScanPlus Runner, ScanPlus Debugger and ScanPlus Flash Programmer. Figure 4-5. Controller Configuration TAP Configuration Options Using PCIe-1149.1 with ScanPlus... -
Page 35: Table 4-1. Scanplus Runner Scantap-4 Configuration
Serialize TAPs 1 through 4 TAPs 1, 2, 3, and 4 in series Table 4-1. ScanPlus Runner ScanTAP-4 Configuration NOTE: Additional selection options are available for Flash Programming (.fpi) test steps as described later in this chapter. Using PCIe-1149.1 with ScanPlus... -
Page 36: Tap Configuration - Method 2
Note that since in most cases the file name already contains a suffix, the file name ID is inserted between the suffix and the rest of the file name. For example, infrastructure_inf.cvf becomes infrastructure_TAP1+2+3+4_inf.cvf. NOTE: Additional selection options are available for Flash Programming (.fpi) test steps as described later in this chapter. Using PCIe-1149.1 with ScanPlus... -
Page 37: Tap Configuration - Method 3
Use this method only when specific test step(s) require TAP configuration settings different from the global settings selected in Method 1. A typical ScanPlus Runner main screen with multiple test steps is shown in Figure 4-6: Figure 4-6. Typical ScanPlus Runner Test Plan Using PCIe-1149.1 with ScanPlus... -
Page 38: Figure 4-7. Scanplus Runner Pop-Up Menu
Highlight a test step by pointing to it with the mouse and then clicking once with the left mouse button. The test step is now highlighted. Right-click on the test step name to bring up a pop-up menu, and select Options as shown in Figure 4-7. Figure 4-7. ScanPlus Runner Pop-up Menu 4-10 Using PCIe-1149.1 with ScanPlus... -
Page 39: Figure 4-8. Infrastructure Test Options Dialog Box
Figure 4-8 illustrates an options dialog for an infrastructure test step. Consult the ScanPlus Runner User’s Manual for more information on the Options dialog boxes. Figure 4-8. Infrastructure Test Options Dialog Box Using PCIe-1149.1 with ScanPlus 4-11... -
Page 40: Figure 4-9. Available Scantap-4 Configuration
Click the Use the following ScanTAP configuration check box and select the desired programming topology configuration from the drop-down list. Figure 4-9 shows the selections available from the configuration drop-down list. Figure 4-9. Available ScanTAP-4 Configuration 4-12 Using PCIe-1149.1 with ScanPlus... -
Page 41: Gang Programming With Scanplus Runner
For example, to gang program all four target boards using the file program U7.fpi, change the file name to program U7_TAP1-4.fpi. The ScanTAP-4 is configurable on the fly, and adding a filename suffix from Table 4-3 to a test file name will configure the system to run that test. Using PCIe-1149.1 with ScanPlus 4-13... -
Page 42: Figure 4-10. Scanplus Runner Test Plan For Gang Programming
Note that for files that already contain a suffix, the file name ID is inserted between the suffix and the rest of the file name. For example, infrastructure_inf.cvf becomes infrastructure_TAP1- 4_inf.cvf. Figure 4-10. ScanPlus Runner Test Plan for Gang Programming 4-14 Using PCIe-1149.1 with ScanPlus... -
Page 43: Figure 4-11. Scanplus Runner Pop-Up Menu
The Options dialog provides an alternate way to specify gang programming from ScanPlus Runner. Right-click on the test step name to bring up a pop-up menu, and select Options as shown in Figure 4-11. Figure 4-11. ScanPlus Runner Pop-up Menu Using PCIe-1149.1 with ScanPlus 4-15... -
Page 44: Figure 4-12. Infrastructure Test Options Dialog Box
Figure 4-12 illustrates an options dialog for an infrastructure test step. Consult the ScanPlus Runner User’s Manual for more information on the Options dialog boxes. Figure 4-12. Infrastructure Test Options Dialog Box 4-16 Using PCIe-1149.1 with ScanPlus... -
Page 45: Figure 4-13. Available Scantap-4 Tap Configuration
Click the Use the following ScanTAP configuration check box and select the desired programming topology configuration from the drop-down list. Figure 4-13 shows the selections available from the configuration drop-down list. Figure 4-13. Available ScanTAP-4 TAP Configuration Using PCIe-1149.1 with ScanPlus 4-17... -
Page 46: Figure 4-14. Available Scantap-4 Tap Configuration For .Fpi Files
(programming) test steps. These additional configuration options are only available for Gang Flash programming of .fpi files and is not shown for regular test steps (.cvf files). See Figure 4-14. Figure 4-14. Available ScanTAP-4 TAP Configuration for .fpi files 4-18 Using PCIe-1149.1 with ScanPlus... -
Page 47: Table 4-4. Scanplus Runner Scantap-4 Configuration
TAPs 1 and 2 are active Enable TAPs 1 through TAP3 in parallel (Gang) TAPs 1, 2 and 3 active Enable TAPs 1 through TAP4 in parallel (Gang) All 4 TAPs are active Table 4-4. ScanPlus Runner ScanTAP-4 Configuration Using PCIe-1149.1 with ScanPlus 4-19... -
Page 48: Gang Programming With Scanplus Flash Programmer
Invoke ScanPlus Flash Programmer, select the Setup menu item, and the Gang Programming entry. Then check off the TAPs on which you are programming the Flash Devices. Figure 4-15 below shows the setup for programming four targets in parallel. Figure 4-15. ScanPlus Flash Programmer Gang Programming Window 4-20 Using PCIe-1149.1 with ScanPlus... -
Page 49: Chapter 5 Third Party Application Interface
ScanPlus Runner provides a general purpose, third-party application interface that includes specifying the correct controller card and settings. This section clarifies the requirements related to the PCIe-1149.1 card and to the ScanTAP-4. Refer to the ScanPlus Runner manual for further information. -
Page 50: Table 5-1. Pcie-1149.1 Controller Parameters
… (0.05 MHz increment) 1.25 MHz 1.225 MHz … … (0.025 MHz increment) .625 MHz .609MHz … … (0.0156 MHz increment) .391MHz .350 MHz … … (0.05 MHz increment) .050 MHz Table 5-1. PCIe-1149.1 Controller Parameters Third Party Application Interface... - Page 51 Compensation No Delay 0.5 Clock Delay 1.0 Clock Delay 1.5 Clock Delay 2.0 Clock Delay 2.5 Clock Delay (the following are for PCIe-1149.1 without ScanTAP only) 3.0 Clock Delay … (0.5 clock increment) … 14.5 Clock Delay 15.0 Clock Delay...
- Page 52 1.35 V … … (0.05 V per step) 3.20 V 3.25 V 3.30 V TAP1 Automatic Input Threshold TAP2 Automatic Input Threshold TAP3 Automatic Input Threshold TAP4 Automatic Input Threshold Table 5-1. PCIe-1149.1 Controller Parameters (continued) Third Party Application Interface...
- Page 53 Example: To select a PCIe-1149.1 controller card with a TAP1 voltage of 3.30 V, TCK frequency of 1 MHz, and automatic delay compensation, use this “controller specification” string: -controller “PCIe-1149.1,42,196,1,,,,” To select a PCIe-1149.1+ScanTAP4 controller card with all TAP voltages of 3.30 V, TCK frequency of 1 MHz, automatic delay compensation, automatic input threshold, slow slew rate and TAP1, use this “controller specification”...
-
Page 55: 10-Pin Tap Connector
Boundary-scan based test equipment, such as the Corelis ScanPlus family of products, utilize a single TAP to interface to the UUT. This section explains how to implement a TAP connector that is compatible with most standard test equipment. -
Page 56: Table A-1. Signal Description And Termination
Table A-1 describes the 10 pin TAP connector signals and Corelis recommended values of terminating resistors: Signal Direction Termination TRST* Input to the UUT 1K pull-up (or 1.5K pull-down) Note: Some target boards may require a pull-down resistor on Input to the UUT... -
Page 57: Figure A-2. Tap Connector Schematic
Figure A-2 shows a typical schematic of the target TAP connector with the recommended termination resistors. The 1K pull-up resistors should connect to the target Vcc supply corresponding to the interface voltage (programmable on the PCIe-1149.1 from 1.25 to 3.3 V). Recommended resistor values are +/- 5%. Vcc Vcc Vcc Vcc... -
Page 58: Flash Programming Tap Connector
Flash Programming TAP Connector To build in support for in-circuit programming of flash or microprocessor devices, Corelis recommends including supplemental control signals in the TAP interface. The ScanPlus Flash Programmer can use a 16-pin TAP, similar to Figure A-3, to improve programming time. This interface adds Write_Strobe*, Ready/Busy*, and ground signals to the standard 5-signal interface. -
Page 59: Table A-3. Flash Programming Tap 16 Pin Connector
Part Number Flash TAP Straight header, 16-pin, 4 wall, with center notch 2516-6002UG Table A-3. Flash Programming TAP 16 Pin Connector Table A-4 describes the signals and Corelis recommended values of terminating resistors: Note: Some target Signal Direction Termination boards may require a... -
Page 60: Figure A-4. Flash Programming Tap Connector Schematics
Figure A-4 shows a typical schematic of the target TAP connector with termination resistors. The 1K pull-up resistors should connect to the target Vcc supply corresponding to the interface voltage (programmable on the PCIe-1149.1 from 1.25 to 3.3 V). Recommended resistor values are +/- 5%. Vcc Vcc... -
Page 61: 20-Pin Tap Connector
20-pin TAP Connector To build in support for in-circuit programming of flash or microprocessor devices, Corelis recommends including supplemental control signals in the TAP interface. The ScanPlus Flash Programmer can use a 16-pin TAP, similar to Figure A-5, to improve programming time. This interface adds Write_Strobe*, Ready/Busy*, and ground signals to the standard 5-signal interface. -
Page 62: Table A-5. Flash Programming Tap 16 Pin Connector
Part Number Flash TAP Straight header, 16-pin, 4 wall, with center notch 2516-6002UG Table A-5. Flash Programming TAP 16 Pin Connector Table A-4 describes the signals and Corelis recommended values of terminating resistors: Note: Some target Signal Direction Termination boards may require a... -
Page 63: Table A-6. Signal Description And Termination
UUT Power Test VCC1 Point I2C_SCL Input to the UUT 1K pull-up UUT Power Test VCC2 Point SPI_CS1* / Input to the UUT 1K pull-up I2C_SDA Table A-6. Signal Description and Termination Recommended Target Connectors... -
Page 64: Figure A-6. 20-Pin Tap Connector Schematic For Spi
Figure A-6 shows a typical schematic of the target TAP connector with termination resistors. The 1K pull-up resistors should connect to the target Vcc supply corresponding to the interface voltage (programmable on the PCIe-1149.1 from 1.25 to 3.3 V). Recommended resistor values are +/- 5%. The 33 ohm resistor... -
Page 65: Figure A-7. 20-Pin Tap Connector Schematic For I2C
Figure A-7 shows a typical schematic of the target TAP connector with termination resistors. The 1K pull-up resistors should connect to the target Vcc supply corresponding to the interface voltage (programmable on the PCIe-1149.1 from 1.25 to 3.3 V). Recommended resistor values are +/- 5%. 3.3V 3.3V... - Page 67 Self Test Utility Software The PCIe-1149.1 has a self test utility that can be used to test the card and make sure that it is fully functional. Logic at the TAP connectors can read back data shifted out on TMS and TDO synchronously with the TCK.
-
Page 68: Figure B-1. Self-Test Result For The Pcie-1149.1 When The Scantap-4 Is Not Connected
Figure B-1. Self-Test Result for the PCIe-1149.1 when the ScanTAP-4 is NOT connected Self Test Utility Software... -
Page 69: Figure B-2. Self-Test Results For The Pcie-1149.1 With The Scantap-4 Connected
Figure B-2. Self-Test Results for the PCIe-1149.1 with the ScanTAP-4 Connected Self Test Utility Software...
Need help?
Do you have a question about the PCIe-1149.1 and is the answer not in the manual?
Questions and answers