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Related Manuals for Davicom DM9000A
Summary of Contents for Davicom DM9000A
- Page 1 DM9000A APPLICATION NOTES DM9000A 16 / 8 Bit Ethernet Controller with General Processor Interface Application Notes V1.21 Technical Reference Manual Davicom Semiconductor, Inc Preliminary Version: DM9000A-AN-V121 November 27, 2007...
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Page 2: Table Of Contents
4.3.1 GPR PHYPD Setting......................20 4.3.2 PHY Register Setting......................20 5 HOW TO PROGRAM DM9000A..............21 5.1 How to Read/ Write DM9000A Register .................21 5.2 Driver Initializing Steps ......................22 5.3 How to Read/ Write EEPROM Data ..................23 5.3.1 HOWTO Read EEPROM Data ..................23 5.3.2 HOWTO Write EEPROM Data ..................24... - Page 3 5.6.3 To Check the Packet Status and Length................31 5.6.4 Receive the Packet's Data ....................32 6 THE OTHERS.....................33 6.1 How to transmit and receive more than 2048-byte packets.............33 6.2 The performance of DM9000A....................33 6.3 WOL (Wake-up on LAN)......................33 6.4 IP/TCP/UDP checksums Offload ....................37 6.5 AUTO-MDIX and Application....................38...
- Page 4 DM9000A APPLICATION NOTES FIGURE 1.1 DM9000A INTERNAL BLOCK DIAGRAM..............6 FIGURE 2.1 SIGNAL CONNECTION WITH A PROCESSOR INTERFACING ......7 FIGURE 2.2 CMD PIN AND PROCESSOR INTERFACE ..............9 FIGURE 3.1 SCHEMATIC FOR 8-BIT PROCESSOR ..............17 FIGURE 3.2 SCHEMATIC FOR 16-BIT PROCESSOR ..............18 FIGURE 5.1 PACKET TRANSMITTING BUFFER.................28...
- Page 5 TABLE 3.2 EEPROM FORMAT IN 16-BIT MODE ................. 11 TABLE 3.3 EEPROM FORMAT IN 8-BIT MODE ................13 TBALE 3.4 GENERAL PURPOSE CONTROL REGISTER (GPCR) TABLE .........15 TABLE 3.5 GENERAL PURPOSE REGISTER (GPR) TABLE ............16 Preliminary Version: DM9000A-AN-V121 November 27, 2007...
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Page 6: Introduction
It is good integrated 10/100 Mbps transceiver with AUTO-MDIX and IP/TCP/UDP-Checksum Offload. The goal of this document is for the embedded design engineers, to implement the DM9000A LAN chip on any processor's architecture quickly and successfully, with providing the exact reference information and pertaining to many embedded systems. -
Page 7: General Processor Bus Description
APPLICATION NOTES 2 General Processor Bus Description This chapter is intended to aid design engineers connecting the DM9000A device to a micro-processor or micro-controller. The discussion will include the pin functional table, and the individual control signals of the DM9000A involved in the connection between the device and an associated micro-processor/ micro-controller in detail. -
Page 8: Pin Function Table
2.1.2 8/ 16-Bit Mode Setting There are two operation modes of DATA bus width, 8-bit or 16-bit, when access to the internal memory in the DM9000A. These two modes are selected by the strap pin 21 EECS shown the following table:... -
Page 9: Command Type
APPLICATION NOTES 2.1.3 Command Type In the DM9000A, there are only two registers, named INDEX port and DATA port, which can be accessed directly. These two ports are distinguished by the CMD pin in the access command cycle. When CMD is low in command cycle, INDEX port is accessed; otherwise, when CMD is high, DATA port is accessed. -
Page 10: System Hardware Design
Both of CS pin and IOW/ IOR pin should be active to write/ read the value into INDEX port or DATA port. So, if the IOW and IOR signals in the system are only used by the DM9000A, the CS pin can be forced to the active logic level to simplify the system design. -
Page 11: Serial Eeprom Operation
All of accesses to the EEPROM are done in words. All of the EEPROM addresses in the specification are specified as word addresses. The default settings of the DM9000A can be changed by the I/O strap pins, or the EEPROM bits settings with higher priority. The priority for setting the pins polarity is EEPROM > strap pins >... - Page 12 *1: The internal PHY is enabled after power-on. The GPR REG. 1FH Bit [0] is modified from this Bit [8]. Bit [13:9]: Reserved = 0. Bit [14] = 0: AUTO-MDIX OFF, *1: AUTO-MDIX ON. Bit [15]: Reserved = 0. Preliminary Version: DM9000A-AN-V121 November 27, 2007...
- Page 13 Bit [4] = *0: Processor INT pin is force output. 1: Processor INT pin is force open-collected. Bit [5] = 0: Processor IOWAIT is active high. *1: Processor IOWAIT is active low. Bit [6] = 0: Processor IOWAIT is force output. Preliminary Version: DM9000A-AN-V121 November 27, 2007...
- Page 14 LED2 pin 38 act as "IOWAIT" pin used. "XX:XX:XX:XX:XX:XX, 5445, 0A46, 9000, 01E7, E180" if LED1 pin 39 act as "IO16" and LED2 pin 38 act as "WAKE" pin used. Table 3.3 EEPROM Format in 16-bit mode Preliminary Version: DM9000A-AN-V121 November 27, 2007...
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Page 15: Gpio Pins Setting
APPLICATION NOTES 3.4 GPIO Pins Setting If the DM9000A operated in 8-bit mode, there are 6 general purpose pins, GP1~GP6, can be used. Their I/O types are controlled by GPCR REG. 1EH. And their I/O data are presented by GPR REG. 1FH. -
Page 16: Table 3.5 General Purpose Register (Gpr) Table
GPR Bit [1] is "0" to represent a low signal is received. "1": power down the internal PHY PHYPD 1, RW "0": power up the internal PHY. Table 3.5 General Purpose Register (GPR) Table Preliminary Version: DM9000A-AN-V121 November 27, 2007... -
Page 17: Schematic Reference Design
C S# SD BUS_6 C M D SD BUS_7 IN T SD BUS_8 R ST# SD BUS_9 SD BUS_10 SD BUS_11 SD BUS_12 SD BUS_13 SD BUS_14 SD BUS_15 Figure 3.1 Schematic for 8-Bit Processor. Preliminary Version: DM9000A-AN-V121 November 27, 2007... -
Page 18: Figure 3.2 Schematic For 16-Bit Processor
DM9000A APPLICATION NOTES Figure 3.2 Schematic for 16-Bit Processor. Preliminary Version: DM9000A-AN-V121 November 27, 2007... -
Page 19: Reset Operation And Phy Power-Down Mode
20 ms. All of the MAC and PHY registers will be reset to the default values and the hardware strap pins will also be latched. The DM9000A is ready after 5 us when this pin is de-asserted and then the data will be downloaded from the EEPROM. -
Page 20: Gpr Phypd Setting
"0" to PHYPD in the GPR REG. 1FH. 4.3.2 PHY Register Setting In the PHY registers, the Bit [11] Power-down of the basic mode control register (BMCR REG. 00) can be set high "1" to enable the PHY power-down mode. Preliminary Version: DM9000A-AN-V121 November 27, 2007... -
Page 21: How To Program Dm9000A
RX/ TX FIFO SRAM (total 16K bytes), the address of the register must be written into INDEX port. Please refer to the DM9000A datasheet chapter 9.1 about host interface. Here are the examples to read and write the DM9000A register: (Where CMD pin is connected to Processor SA2) UINT16 IOaddr;... -
Page 22: Driver Initializing Steps
"0" to PHYPD (GP0 = 0). Please refer to the ch.3.4 about setting the GPIO pins. 2. To do a software reset for the DM9000A initial (see chapter 4.2): i. iow ( 0x00, 0x01 ); to set NCR (REG. 00) RST Bit [0] = 1 for a period time 10 us. -
Page 23: How To Read/ Write Eeprom Data
APPLICATION NOTES 5.3 How to Read/ Write EEPROM Data The DM9000A supports the serial EEPROM interface and provides a very easy method to access it. It is only to read/ write the EEPROM&PHY control/ address/ data register (REG. 0BH ~ REG. 0EH), which are used to control and read/ write the EEPROM address or data. -
Page 24: Howto Write Eeprom Data
Step 5: wait 500 us at least, then, write "0" into EPCR REG. 0BH to clear WRITE command. HOWTO write 0x1E7 into SROM Word 0x06, Pin Control, shown as follows: 1. write word address = 0x06 to EPAR REG. 0CH iow ( 0x0C, 0x06 ); Preliminary Version: DM9000A-AN-V121 November 27, 2007... - Page 25 /* wait >500 us for SROM + WRITE completed then write "0" to clear command */ do { udelay (10); tmpv= inb (IOaddr+4); i++; } while ( (i < 500) && (tmpv & 1) ); udelay ( 60000 ); iow( 0x0B, 0 ); Preliminary Version: DM9000A-AN-V121 November 27, 2007...
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Page 26: How To Read/ Write Phy Register
APPLICATION NOTES 5.4 How to Read/ Write PHY Register The DM9000A PHY supports only 32 registers, which are mapped to EPAR (REG. 0CH) Bit [4:0]. The default value of EPAR (REG. 0CH) PHY_ADR Bit [7:6] is "01" to select the PHY mode. -
Page 27: Howto Write Phy Register
5. delay 5 us maximum, then write "8" into EPCR REG. 0BH to clear it and keep PHY udelay ( 5 ); /* wait 1~5 us for the PHY+WRITE command completion */ iow ( 0x0B, 0x08 ); /* clear this PHY "WRITE" command */ Preliminary Version: DM9000A-AN-V121 November 27, 2007... -
Page 28: How To Transmit Packets
TXREQ (Transmit Request), Bit [0] in TCR REG. 02, for transmitting this packet. The DM9000A will generate an interrupt at PTS Bit [1] = 1 in ISR REG. FEH, if setting Bit [1] = 1 in IMR REG. FFH, and also to set a completion flag to either TX1END Bit [2] = 1 or TX2END Bit[3] = 1 in NSR REG. -
Page 29: To Check A Completion Flag
IMR PTM Bit [1] = 1 enable: (u8) INT_status = ior ( 0xFE ); /* got DM9000A interrupt status in ISR */ if ( INT_status & 0x02 ) { /* TX success */ /* check if PTS Bit [1] = 1, TX ok */ iow ( 0xFE, 0x02 );... -
Page 30: How To Receive Packets
The received and filtered packet's data save in the RX FIFO, which is the internal SRAM address 0x0C00 ~ 0x3FFF (13K Byte size) in the DM9000A MAC. There are four bytes for the MAC header of each packet saving in the RX FIFO SRAM, and using the two registers of MRCMDX REG. -
Page 31: Packet Reception
I/O bus width is Byte/ Word to increase one or two bytes respectively. MRCMD (REG. F2H) is only used to read the RX status, length and the packet's data from the RX SRAM. Preliminary Version: DM9000A-AN-V121 November 27, 2007... -
Page 32: Receive The Packet's Data
( i = 0 ; i < tmp_length ; i++ ) /* loop to READ a Word data from RX FIFO SRAM*/ ( (u16 *)RX_data)[ i ] = inw ( IOaddr + 4 ); Preliminary Version: DM9000A-AN-V121 November 27, 2007... -
Page 33: The Others
6.3 WOL (Wake-up on LAN) The DM9000A LAN chip also supports the WOL function and the pin 22 WAKE (or the pin 38 LED2, if setting the EEPROM Word 7 Bit [13:12] = 10 in 16-bit mode) output the wake-up signal to the embedded system. - Page 34 The Sample Frame would be made up of 6 packets and the maximum size of each packet can be 2048-byte. The wake-up pin will be active if the DM9000A receives only one set of the sample frames. The following description will show how to set the Sample Frame in detail.
- Page 35 Restart the Sample Frame function by setting the Bit [4] SAMPLEEN in WCR REG. 0FH to "1" and enable the WOL function by setting the WAKEEN Bit [6]=1 in NCR (REG. 00). Restart the DM9000A receiver function by setting the Bit [0] in RCR REG. 05 to be "1". Preliminary...
- Page 36 (i = 0, sample_ptr = 0; i < sample_length; i++, sample_ptr += 4) { /* set sample_ptr to MWRL as low byte and to MWRH as high byte in DM9000A SRAM */ iow ( MWRL, sample_ptr & 0xff );...
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Page 37: Ip/Tcp/Udp Checksums Offload
APPLICATION NOTES 6.4 IP/TCP/UDP checksums Offload The DM9000A chip supports the IP/TCP/UDP checksum generations and status checking. And enable the IP/TCP/UDP checksums offload function in the TCP/IP upper layers of the embedded OS, while setting the DM9000A IP/TCP/UDP checksum generations and checking. -
Page 38: Auto-Mdix And Application
DM9000A. Figure 6.1 AUTO-MDIX 10Base-T/100Base-TX Application. The DM9000A is default turning on AUTO-MDIX feature, and there are two ways to disable AUTO-MDIX function: 1. To set the SROM Word 7, Wake-up Mode Control, Bit [14] = 1 then zero to re-load it, srom_write (0x07, 0x180);...
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