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PLL
U N I T
t
X 5 0 - 1 6 5 0 - 1 0
0
r
2 5 1 1 9 I G l l l
D
I
(SV50..
SCHEMATIC DIAGRAM (W)[T)
0 1 . 2 . 1 5
35u741LI
019
2 5 C 2 2 4 0 I G R )
D
o
1N63
0 1 . 1 1
2 S C 4 9 2 3 1 0 1
.
0 2 . 1
4 5 2 5 6 1
0
.
. 3 S U 7 4 I L 1
01-11.11 .11
2SC46OlB)
OSD
T 1 7 0 6 1 A P
r - - - - - - - - -
o.
15516
otl.ll
b 3 ,
I S ( 2 1 2
2 S C I 7 7 5 I E )
0 1 1 . 1 4
2 5 1 6 4 I G R I
D ~ - S . ~ Z . ~ ~ . S . Z ~ - Z ~
151555
0..10-l2
2 5 C 4 6 O I B I
0 5
1 5 2 2 0 3
.
.
O I . - ~ S . I . . ~ . . I ~ . ~ L
2 5 C f W I 5 l Y )
0 3 6
2 5 C 2 5 3 W - 2 2 - 1
D O
0 3
. 2 5 1 3 0 A l G R )
x z - o w n
O t I . 2 I
2 1 4 1 0 1 5 1 1 1
01,.1.
2SC45BIB:
O(7
X Z - 0 6 0
0 6 . 7
2 S C 2 2 4 0 1 t R I
0 2 0
t l A 4 3 6 6 l
D ~ I
1 2 - 0 7 0
0 .
Z S C I T 7 5 I E l
0
14.11
r P C 7 B a B H
0 0
VOSB
0
1 3
25A.96111
0 I D .
I 4
. 1 5 2 2 0 B
0
2.
. ? S t 4 9 6 111
D , , , z I - H
: I T T 4 , 0
--.
--
.:x
CI
--
DER
U N I T ( X 5 4 - 1 5 0 0 - 1 0 )
,
-
.
.
TR
7 8 5 0
1T.WI
----
\
0 1
L B 1 4 0 9
0 1 . 1 ' T C 4 O O l BP
0 3
: T C 4 0 4 9 B P
0 1 . 3 . 5 . P R 5 5 3 2 K
Voltage measure condition
"-
0 2 . 4
. P Y 5 5 3 2 K
.
0 6
: T ~ ~ 4 4 3 5
f1146.0 MHz
0 7
' T L R 3 2 3
Common DC line
C ,
( ) :
inTX
Signal
------
Control
8
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