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Summary of Contents for Sensoray 526
- Page 1 PC/104 Multifunction I/O Board Hardware Manual Model 526 | Rev.B | February 2009...
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Page 2: Table Of Contents
Table of Contents TABLE OF CONTENTS ......................2 LIMITED WARRANTY......................4 SPECIAL HANDLING INSTRUCTIONS ..................4 INTRODUCTION......................... 5 PROGRAMMABLE COUNTERS....................7 Input Signals......................... 7 Captured Events ......................8 Output Signals ......................8 Counter Preload ......................8 Output Register......................9 Examples of Counter Applications ..................9 One-shot (software trigger).................. - Page 3 Counter Mode Register....................26 Counter Control/Status Register ..................27 EEPROM Data Register....................28 EEPROM Command/Status Register ................28 SPECIFICATIONS ......................29...
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Page 4: Limited Warranty
The reader should consult Sensoray if errors are suspected. In no event shall Sensoray be liable for any damages arising out of or related to this document or the information contained in it. -
Page 5: Introduction
Requires one power supply (+5V). Model 526 is controlled through a set of 27 registers mapped into I/O space. The base address of the board is selected with jumpers from a range of 0x0000 to 0xFFC0. The board is shipped with the base address set to 0x2C0. - Page 6 Fig.1. Model 526 board outline.
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Page 7: Programmable Counters
Programmable Counters Model 526 contains 4 identical 24-bit up/down counters with enable and preload. The block diagram of one of the counters is shown on Fig.2. DATA BUS COUNTER CORE PRELOAD BUFFER 0 DATA BUS LATCH PRELOAD BUFFER 1 RTGL "1"... -
Page 8: Captured Events
• quadrature x2 (both edges of CLKA); • quadrature x4 (both edges of both CLKA and CLKB); In normal mode the clock sources are: • CLKA↑; • CLKA↓; • Internal clock (27 MHz); • Internal clock divided by 2 (13.5 MHz). Count direction (up or down) is set through the software (normal mode) or determined from CLKA-CLKB phase relationship (quadrature mode). -
Page 9: Output Register
determined by the state of the RTGL signal: PR0 when RTGL is low, PR1 when RTGL is high. The autoload occurs under a programmable combination of the following conditions: • INDEX↑ - rising edge of INDEX signal; • INDEX↓ - falling edge of INDEX signal; •... -
Page 10: One-Shot (Hardware Trigger)
RegisterWrite (0x14, 0x0001); //load Preload Register high word RegisterWrite (0x12, 0x3C68); //load Preload Register low word Step 2. Reset the counter (to clear RTGL), load the counter from Preload Register 0. RegisterWrite (0x18, 0x8000); //reset the counter RegisterWrite (0x18, 0x4000); //load the counter from PR0 Step 3. -
Page 11: Interrupt Timer
To change the duty cycle steps 1-2 have to be repeated with the new preload register values. Interrupt Timer The interrupt timer provides a way of generating interrupts at precise time intervals in the range between approximately 100 µs and 25.5 ms. The timer is an 8-bit down counter with a preload counting a 99.852 µs clock. -
Page 12: Watchdog Enable/Disable
Watchdog enable/disable Watchdog enable/disable is controlled by bit [3] of the Watchdog Timer Control register and jumper 1 of J4. Shunt in position 1 of J4 Bit [3] of Control Register Watchdog timer Not installed Disabled Not installed Enabled Installed Enabled Installed Disabled... -
Page 13: D/A Converter
D/A Converter Model 526 implements a 4-channel 16-bit D/A converter. Each channel has an individual preload buffer. Preload buffers are accessed through a single write register (DAC/ADC Data register) and selected with 2 bits of the DAC Control register. Upload to the DAC is performed for all 4 channels from their corresponding preload buffers with a single software command and takes approximately 8 µs to complete. - Page 14 − ⋅ meas − meas where - the actual value of the on-board 10V reference (from the EEPROM); - ADC reading corresponding to the measured voltage; meas - ADC reading corresponding to the on-board +10V reference; - ADC reading corresponding to the on-board 0V reference.
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Page 15: Digital I/O
Digital I/O Digital I/O on model 526 consists of 8 signals, which can be configured as inputs or outputs in groups of 4: DIO group 1 (DIO0-3) and DIO group 2 (DIO4-7). Interrupts can be generated on rising or falling edges of DIO signals. Interrupt condition (rising or falling edge) can be selected individually for every signal in group 1, and for group 2 as a whole. -
Page 16: Calibration Eeprom
Calibration EEPROM An on-board EEPROM is provided for calibration data storage. Data from the EEPROM is read by using a set of 2 registers: EEPROM Command/Status register and EEPROM data register. The EEPROM is organized as 64 2-byte words, with addresses from 0x00 to 0x3F. The address map of the EEPROM is as following: Address Contents... -
Page 17: Configuration Jumpers
Configuration Jumpers A set of configuration jumpers (J1) allows selection of board’s base address and interrupt line (See Fig.1). Jumpers marked ADDR15-6 select the higher 10 bits of the board’s base address in I/O space. Inserted jumper sets the corresponding bit to 0. The board ships with base address set to 0x2C0. Jumpers marked IRQ3-0 select the interrupt line used by the board. -
Page 18: Digital Connector (J5)
Digital connector (J5) Signal Signal Clock A 0 - Clock A 0 + Clock B 0 - Clock B 0 + Index 0 - Index 0 + Count Enable 0 Counter Output 0 Encoder 0 power (+5V) Ground Clock A 1 - Clock A 1 + Clock B 1 - Clock B 1 +... -
Page 19: Registers
Registers Register Map Register addresses are relative to the base address selected with address jumpers (ADDR 15 – 6). All register accesses are 2-byte. Single byte and odd address accesses are not supported. Address Write Read 0x00 Timer control register 0x02 Watchdog timer control register 0x04... -
Page 20: Timer Control Register
Timer Control Register 0x00 Bits Type Default Description [15:8] 0x00 Timer preload data in 100 us ticks. [7:2] XXXXXX Reserved Timer mode: 0 – manual restart; 1 – auto restart. Manual restart. Writing a 1 restarts the timer if [1] is 0. Bit [0] of the Interrupt Status register is set to 1 when timer expires. -
Page 21: Dac Control Register
DAC Control Register 0x04 Bits Type Default Description [15:4] Reserved. DAC reset. Writing a 1 to this bit resets all DAC channels. Writing a 0 has no effect. [2:1] DAC data buffer select. Write accesses to DAC Data Register are routed to the corresponding data buffer: 00 - channel 0;... -
Page 22: Adc Control Register
ADC Control Register 0x06 Bits Type Default Description [15] Input multiplexor settling delay: 0 – no delay; 1 – 12 µs delay. [14:5] 0x000 ADC conversion control. A 1 enables conversion of the corresponding channel: [14] – enable conversion on reference 1 (0 V); [13] –... -
Page 23: Digital I/O Control Register
Digital I/O Control Register 0x0A Bits Type Default Description [15] DIO(3) interrupt condition: 0 – interrupt on a rising edge; 1 – interrupt on a falling edge. [14] DIO(2) interrupt condition: 0 – interrupt on a rising edge; 1 – interrupt on a falling edge. [13] DIO(1) interrupt condition: 0 –... -
Page 24: Interrupt Enable Register
Interrupt Enable Register 0x0C Bits Type Default Description [15] DIO7 interrupt enable. [14] DIO6 interrupt enable. [13] DIO5 interrupt enable. [12] DIO4 interrupt enable. [11] DIO3 interrupt enable. [10] DIO2 interrupt enable. DIO1 interrupt enable. DIO0 interrupt enable. Reserved. Counter 0 interrupt enable. Counter 1 interrupt enable. -
Page 25: Miscellaneous Register
Miscellaneous Register 0x10 Bits Type Default Description [15:1] Reserved. LED control. A 0 turns the LED on, a 1 turns it off. Counter Preload/Data Register low word 0x12 – counter 0, 0x1A – counter 1, 0x22 – counter 2, 0x2A – counter 3. Bits Type Default... -
Page 26: Counter Mode Register
Counter Mode Register 0x16 – counter 0, 0x1E – counter 1, 0x26 – counter 2, 0x2E – counter 3. Bits Type Default Description [15] Reserved. [14] Preload register select: 0 – writes to Preload Register directed to PR0; 1 – writes to Preload Register directed to PR1. [13] Output register latch control: 0 –... -
Page 27: Counter Control/Status Register
Notes. 1. In “Latch on read” mode data from the counter is latched on the read access to the Counter data low word register. Thus the low word has to be always read first in this mode. 2. In “Latch on event” mode data from the counter is latched by the event(s) selected with bits [12:10] of Counter Control/Status register. -
Page 28: Eeprom Data Register
EEPROM Data Register 0x32 Bits Type Default Description [15:0] 0x0000 EEPROM data. Read accesses return the last value read from EEPROM. EEPROM Command/Status Register 0x34 Bits Type Default Description [8:3] 000000 EEPROM address. [2:1] Must be set to 10 for read access. EEPROM access start bit. -
Page 29: Specifications
Specifications Parameter Value Units Notes D/A Converter Number of channels Resolution bits µs Upload time, max µs Settling time, max ±10 Output range, min ±2 Max output current Each channel A/D Converter Number of channels Resolution bits ±10 Input range, min µs Conversion time, no channel switching, max µs...
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