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Hotenda MPC8349EA Technical Data Manual

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Freescale Semiconductor
Technical Data
MPC8349EA PowerQUICC II Pro
Integrated Host Processor Hardware
Specifications
The MPC8349EA PowerQUICC II Pro is a next generation
PowerQUICC II integrated host processor. The
MPC8349EA contains a processor core built on Power
Architecture® technology with system logic for networking,
storage, and general-purpose embedded applications. For
functional characteristics of the processor, refer to the
MPC8349EA PowerQUICC II Pro Integrated Host
Processor Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC8349EA product summary page on our website,
as listed on the back cover of this document, or contact your
local Freescale sales office.
© 2006-2011 Freescale Semiconductor, Inc. All rights reserved.
Electronic Component Distributor. Source::Freescale Semiconductor
P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:sales@hotenda.cn Phone:(+86) 075583794354
Document Number: MPC8349EAEC
Rev. 13, 09/2011
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 15
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 53
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
21. System Design Information . . . . . . . . . . . . . . . . . . . 79
22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 82
23. Document Revision History . . . . . . . . . . . . . . . . . . . 84

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Summary of Contents for Hotenda MPC8349EA

  • Page 1: Table Of Contents

    Integrated Host Processor Hardware Specifications The MPC8349EA PowerQUICC II Pro is a next generation Contents 1. Overview ........2 PowerQUICC II integrated host processor.

  • Page 2: Overview

    — 32-Kbyte instruction cache, 32-Kbyte data cache — Lockable portion of L1 cache — Dynamic power management — Software-compatible with the other Freescale processor families that implement Power Architecture technology MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 3 — PCI agent mode on PCI1 interface — PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses and support for delayed read transactions — Posting of processor-to-PCI and PCI-to-memory writes MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 4 – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes • Universal serial bus (USB) dual role controller — USB on-the-go mode with both device and host functionality MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 5 — External and internal interrupts directed to host processor — Redirects interrupts to external INTA pin in core disable mode. — Unique vector number for each interrupt source MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 6: Electrical Characteristics

    This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8349EA. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
  • Page 7 Figure 6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 8 Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8349EA. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
  • Page 9 Electronic Component Distributor. Source::Freescale Semiconductor P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA Web:http://www.hotenda.cn E-mail:sales@hotenda.cn Phone:(+86) 075583794354 Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349EA for the 3.3-V signals, respectively. 11 ns (Min) +7.1 V Overvoltage 7.1 V p-to-p...

  • Page 10: Power Characteristics

    , and OV ) do not have any ordering requirements with respect to one another. Power Characteristics The estimated typical power dissipation for the MPC8349EA device is shown in Table Table 4. MPC8349EA Power Dissipation Core Frequency (MHz) CSB Frequency (MHz)
  • Page 11 — — 0.01 — — Multiply by 2 if using 2 ports. 480 MHz — — — — Other I/O — — — 0.01 — — — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 12: Clock Input Timing

    — ±50 AC Electrical Characteristics The primary clock source for the MPC8349EA can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the device.

  • Page 13: Reset Initialization

    This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8349EA. RESET DC Electrical Characteristics Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8349EA. Table 9. RESET Pins DC Electrical Characteristics Parameter Symbol...
  • Page 14 PowerQUICC II Pro Integrated Host Processor Family Reference Manual. 2. t is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA CLKIN PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

  • Page 15: Ddr And Ddr2 Sdram

    + 0.125 + 0.3 — Input low voltage –0.3 – 0.125 — μA Output leakage current –9.9 Output high current (V = 1.420 V) –13.4 — — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 16 MV . This rail should track variations in the DC level of MV ≤ ≤ 4. Output leakage is measured with all outputs disabled, 0 V MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 17 At recommended operating conditions with GV of 2.5 ± 5%. Parameter Symbol Unit Notes AC input low voltage — – 0.31 — AC input high voltage + 0.31 — — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 18 3. This specification applies only to the DDR interface. Figure 5 illustrates the DDR input timing diagram showing the t timing parameter. DISKEW MCK[n] MCK[n] MDQS[n] MDQ[x] DISKEW DISKEW Figure 5. DDR Input Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 19 400 MHz — 333 MHz — 266 MHz 1100 — 200 MHz 1200 — –0.5 × t –0.5 × t MDQS preamble start – 0.6 + 0.6 DDKHMP MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 20 The timing parameters listed in the table assume that these two parameters are set to the same adjustment value. See the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual for the timing modifications enabled by use of these bits.

  • Page 21: Duart

    This section describes the DC and AC electrical specifications for the DUART interface of the MPC8349EA. DUART DC Electrical Characteristics Table 21 provides the DC electrical characteristics for the DUART interface of the MPC8349EA. Table 21. DUART DC Electrical Characteristics Parameter Symbol...

  • Page 22: Ethernet: Three-Speed Ethernet, Mii Management

    — = 100 μA Low-level output voltage, I — DUART AC Electrical Specifications Table 22 provides the AC timing parameters for the DUART interface of the MPC8349EA. Table 22. DUART AC Timing Specifications Parameter Value Unit Notes Minimum baud rate baud —...
  • Page 23 The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This section describes the GMII transmit and receive AC timing specifications. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 24 — — RX_CLK duty cycle — GRXH RXD[7:0], RX_DV, RX_ER setup time to RX_CLK — — GRDVKH RXD[7:0], RX_DV, RX_ER hold time to RX_CLK — — GRDXKH MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 25 TX_CLK clock period 10 Mbps — — TX_CLK clock period 100 Mbps — — TX_CLK duty cycle — MTXH/ TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay MTKHDX MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 26 RX_CLK duty cycle — MRXH RXD[3:0], RX_DV, RX_ER setup time to RX_CLK 10.0 — — MRDVKH RXD[3:0], RX_DV, RX_ER hold time to RX_CLK 10.0 — — MRDXKH MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 27 Valid Data RX_ER MRDVKH MRDXKH Figure 13. MII Receive AC Timing Diagram 8.2.3 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 28 At recommended operating conditions with LV of 3.3 V ± 10%. Parameter/Condition Symbol Unit PMA_RX_CLK clock period 16.0 PMA_RX_CLK skew — SKTRX RX_CLK duty cycle — TRXH MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 29 TBI receive AC timing diagram. TRXR PMA_RX_CLK1 TRXH TRXF RCG[9:0] Even RCG Odd RCG TRDVKH SKTRX TRDXKH PMA_RX_CLK0 TRXH TRDXKH TRDVKH Figure 15. TBI Receive AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 30 5. Duty cycle reference is LV MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 31 Output low voltage = 1.0 mA = Min GND – 0.3 0.40 Input high voltage — = Min — Input low voltage — = Min –0.3 0.70 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 32 — MDKHDX MDIO to MDC setup time — — — MDDVKH MDIO to MDC hold time — — — MDDXKH MDC rise time — — — MDCR MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 33 333 MHz, the delay is 58 ns). Figure 17 shows the MII management AC timing diagram. MDCR MDCH MDCF MDIO (Input) MDDVKH MDDXKH MDIO (Output) MDKHDX Figure 17. MII Management Interface Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 34: Usb

    Electronic Component Distributor. Source::Freescale Semiconductor P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA Web:http://www.hotenda.cn E-mail:sales@hotenda.cn Phone:(+86) 075583794354 This section provides the AC and DC electrical specifications for the USB interface of the MPC8349EA. USB DC Electrical Characteristics Table 35 provides the DC electrical characteristics for the USB interface.

  • Page 35: Local Bus

    Low-level input voltage –0.3 μA Input current — ±5 = –100 μA High-level output voltage, I – 0.2 — = 100 μA Low-level output voltage, I — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 36 8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 37 9. DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 20 provides the AC test load for the local bus. = 50 Ω Output = 50 Ω Figure 20. Local Bus C Test Load MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 38 Input Signal: LGTA LBKLOV Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE LBKHOZ LBKLOV Output Signals: LAD[0:31]/LDP[0:3] LBKLOV LBOTOT LALE Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 39 Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) LBKHOZ LBKLOV UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 40 Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) LBKHOZ LBKLOV UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 41: Jtag

    Unit Input high voltage — – 0.3 + 0.3 Input low voltage — –0.3 μA Input current — — ±5 Output high voltage = –8.0 mA — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 42 JTIVKH Input hold times: Boundary-scan data — JTDXKH TMS, TDI — JTIXKH Valid times: Boundary-scan data JTKLDV JTKLOV Output hold times: Boundary-scan data — JTKLDX — JTKLOX MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 43 5. Non-JTAG signal output timing with respect to t TCLK 6. Guaranteed by design and characterization. Figure 27 provides the AC test load for TDO and the boundary-scan outputs of the MPC8349EA. = 50 Ω Output = 50 Ω Figure 27. AC Test Load for the JTAG Interface Figure 28 provides the JTAG clock input timing diagram.
  • Page 44 TDI, TMS Data Valid JTKLOV JTKLOX Output Data Valid JTKLOZ Output Data Valid VM = Midpoint Voltage (OV DD /2) Figure 31. Test Access Port Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 45: I 2 C

    2. C = capacitance of one bus line in pF. 3. Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if OV is switched off.
  • Page 46 AC timing diagram for the I C bus. I2CF I2DVKH I2KHKL I2CF I2CL I2SXKL I2CR I2SXKL I2CH I2SVKH I2PVKH I2DXKL Figure 33. I C Bus AC Timing Diagram MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 47: Pci

    13.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8349EA. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is configured as a host or agent device.
  • Page 48 4. Input timings are measured at the pin. 5. The setup and hold time is with respect to the rising edge of PORESET. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 49: Timers

    This section describes the DC and AC electrical specifications for the timers. 14.1 Timer DC Electrical Characteristics Table 47 provides the DC electrical characteristics for the MPC8349EA timer pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 47. Timer DC Electrical Characteristics Parameter...

  • Page 50: Gpio

    μA Input current — — ±5 Output high voltage = –8.0 mA — Output low voltage = 8.0 mA — Output low voltage = 3.2 mA — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 51: Ipic

    2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least t ns to ensure proper operation in edge triggered mode. PICWID MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 52: Spi

    (first two letters of functional block)(reference)(state)(signal)(state) NIKHOX (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 53: Package And Pin Listings

    Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram 18 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8349EA is available in a tape ball grid array (TBGA). See Section 18.1, “Package Parameters for the MPC8349EA TBGA”...
  • Page 54 Package outline Interconnects Pitch 1.00 mm Module height (typical) 1.46 mm Solder balls 62 Sn/36 Pb/2 Ag (ZU package) 96.5 Sn/3.5Ag (VV package) Ball diameter (typical) 0.64 mm MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 55 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement must exclude any effect of mark on top surface of package. Figure 40. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8349EA TBGA MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13...
  • Page 56 AD33, AD34, AE29, AE30, AH32, AH33, AH34, AM33, AJ31, AJ32, AJ33, AJ34, AK32, AK33, AK34, AM34, AL33, AL34, AK31, AH30 PCI2_C/BE[3:0]/PCI1_C/BE[7:4] AC32, AE32, AH31, AL32 — PCI2_PAR/PCI1_PAR64 AG34 — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 57 AG2, AG1, AK1, AL4 — MCKE[0:1] H3, G1 MCK[0:5] U2, F4, AM3, V3, F2, AN3 — MCK[0:5] U3, E3, AN2, V4, E1, AM4 — MODT[0:3] AH3, AJ5, AH1, AJ4 — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 58 LGPL5/cfg_clkin_div AL26 — LCKE AM27 — LCLK[0:2] AN28, AK26, AP29 — LSYNC_OUT AM12 — LSYNC_IN AJ10 — General Purpose I/O Timers GPIO1[0]/DMA_DREQ0/GTM1_TIN1/ — GTM2_TIN2 GPIO1[1]/DMA_DACK0/ — GTM1_TGATE1/GTM2_TGATE2 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 59 DR_D0_ENABLEN MPH1_D1_SER_TXD/ — DR_D1_SER_TXD MPH1_D2_VMO_SE0/ — DR_D2_VMO_SE0 MPH1_D3_SPEED/DR_D3_SPEED — MPH1_D4_DP/DR_D4_DP — MPH1_D5_DM/DR_D5_DM — MPH1_D6_SER_RCV/ — DR_D6_SER_RCV MPH1_D7_DRVVBUS/ — DR_D7_DRVVBUS MPH1_NXT/DR_SESS_VLD_NXT — MPH1_DIR_DPPULLUP/ — DR_XCVR_SEL_DPPULLUP MPH1_STP_SUSPEND/ — DR_STP_SUSPEND MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 60 — MPH0_CLK/DR_RX_VALID — Programmable Interrupt Controller MCP_OUT AN33 IRQ0/MCP_IN/GPIO2[12] — IRQ[1:5]/GPIO2[13:17] C22, A22, D21, C21, B21 — IRQ[6]/GPIO2[18]/CKSTOP_OUT — IRQ[7]/GPIO2[19]/CKSTOP_IN — Ethernet Management Interface EC_MDC — EC_MDIO MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 61 A13, B13, C13, A12 — TSEC2_RXD[3:0]/GPIO1[13:16] D7, A6, E8, B7 — TSEC2_RX_ER/GPIO1[25] — TSEC2_TXD[7]/GPIO1[31] — TSEC2_TXD[6]/ — DR_XCVR_TERM_SEL TSEC2_TXD[5]/ — DR_UTMI_OPMODE1 TSEC2_TXD[4]/ — DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] B5, A5, F8, B6 — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 62 AN9, AP9, AM10, — PCI_CLK_OUT[3]/LCS[6] AN10 — PCI_CLK_OUT[4]/LCS[7] AJ11 — PCI_CLK_OUT[5:7] AP10, AL11, AM11 — PCI_SYNC_IN/PCI_CLOCK AK12 — PCI_SYNC_OUT AP11 RTC/PIT_CLOCK AM32 — CLKIN — JTAG — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 63 Power for DDR — — DLL (1.2 V nominal, 1.3 V for 667 MHz) AJ13 Power for LBIU — DLL (1.2 V nominal, 1.3 V for 667 MHz) MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 64 AC30, AE31, AF30, AG29, AJ17, AJ30, (3.3 V) AK11, AL15, AL19, AL21, AL29, AL30, AM20, AM23, AM24, AM26, AM28, AN11, AN13 MVREF1 — reference voltage MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 65 11. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to LV 12. For systems that boot from local bus (GPCM)-controlled NOR flash, a pullup on LGPL4 is required. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 66: Clocking

    The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the MPC8349EA is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT.
  • Page 67 SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset, clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock subsystem.
  • Page 68 Electronic Component Distributor. Source::Freescale Semiconductor P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA Web:http://www.hotenda.cn E-mail:sales@hotenda.cn Phone:(+86) 075583794354 Clocking Table 57 provides the operating frequencies for the MPC8349EA TBGA under recommended operating conditions (see Table Table 57. Operating Frequencies for TBGA Characteristic...
  • Page 69 16.67 33.33 66.67 at Reset Input Clock Ratio csb_clk Frequency (MHz) 0010 2 : 1 0011 3 : 1 0100 4 : 1 0101 5 : 1 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 70 16.67 33.33 66.67 at Reset Input Clock Ratio csb_clk Frequency (MHz) 0010 2 : 1 0011 3 : 1 0100 4 : 1 0101 5 : 1 MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 71 Core VCO frequency = core frequency × VCO divider VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 72 Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 73 — — 1010 0000100 — — 66 MHz CLKIN/PCI_CLK Options 0011 0000100 0011 0100100 0100 0000011 0100 0100011 0011 0000101 — 0101 0000011 — 0100 0000100 — MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 74: Thermal

    20 Thermal This section describes the thermal specifications of the MPC8349EA. 20.1 Thermal Characteristics provides the package thermal characteristics for the 672 35 × 35 mm TBGA of the MPC8349EA. Table 63 Table 63. Package Thermal Characteristics for TBGA Characteristic...
  • Page 75 In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 76 When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: θ θ θ MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 77 Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 78 Dow-Corning Corporation 800-248-2481 Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...

  • Page 79: System Design Information

    1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in Section 19.1, “System PLL Configuration.” MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 80 21.3 Decoupling Recommendations Due to large address and data buses and high operating frequencies, the MPC8349EA can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8349EA system, and the device itself requires a clean, tightly regulated source of power.
  • Page 81 MPC8349EA. 21.5 Output Buffer DC Impedance The MPC8349EA drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV or GND.

  • Page 82: Ordering Information

    21.7 Pull-Up Resistor Requirements The MPC8349EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins, including I C pins, and IPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, refer to application note AN2931, “PowerQUICC Design Checklist.”...
  • Page 83 Part Numbers Fully Addressed by This Document Table 66 shows an analysis of the Freescale part numbering nomenclature for the MPC8349EA. The individual part numbers correspond to a maximum processor core frequency. Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration parts including extended temperatures, refer to the device product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office.

  • Page 84: Document Revision History

    PBGA from 95.5 Sn/0.5 Cu/4 Ag to 96.5 Sn/3.5 Ag. • In Table 66, footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1 and DDR2. MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor...
  • Page 85 • In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts. • In Table 4, “MPC8349EA Power Dissipation,” added two footnotes to 667-MHz row showing nominal core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
  • Page 86 VIL in Table 40Table 44,“PCI DC Electrical Characteristics.” • In Table 55, “MPC8349EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω...

  • Page 87: Web:http://Www.hotenda.cn E-Mail:sales@Hotenda.cn Phone

    Electronic Component Distributor. Source::Freescale Semiconductor P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA Web:http://www.hotenda.cn E-mail:sales@hotenda.cn Phone:(+86) 075583794354 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software Technical Information Center, EL516 implementers to use Freescale Semiconductor products.

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