Contents Page An Overview _______________________________________________________ 3 Hardware __________________________________________________________ 3 2.1. PCI9030 from PLX Technology________________________________________ 4 2.1.1. The PCI Bus Interface _______________________________________________ 4 2.1.2. Local bus Interface __________________________________________________ 4 2.2. JTAG Support ______________________________________________________ 5 2.3. EEPROM __________________________________________________________ 5 Example Application_________________________________________________ 5...
(timing etc.) of the PCI bus system. PCI-Proto LAB/PLX-S is a long PCI board manufactured in four layers. It can be trans- formed into a short board when cutting it off at the marked place.
The PLX PCI9030 is a 32-bit, 33-MHz PCI Bus general purpose PCI Target device. It acts as a PCI bridge between the PCI bus and the user circuits. The PLX pci9030 handles all of the PCI signaling and software interfacing and translates the PCI bus cycles to a simple control, address, data general interface for easy connectivity of memory and I/O devices.
In order to successfully design PCI hardware development with PCI-Proto LAB/PLX-S, it is absolutely necessary to study this documentation and the technical manual on the PCI control- ler. If it is not enclosed in the PCI-Proto LAB/PLX-S product, you can request it at no cost from: PLX Technology /USA or Scantec –...
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PCI-Proto LAB/PLX-S easier. We will list them here without putting them any specific or- der. − PCI-Proto LAB/PLX-S is initialized in such a fashion that there are four I/O and memory address regions. They make the following accesses possible: PCI region 0...
3h data bits 24 -31, byte lane The user finds further information about handling and use of the PLX SDK and the accompa- nying software on the disk containing manuals and documentation. The PLX SDK software package is not accompanying part of the PCI-Proto LAB/PLX-S...
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Connection Table Pin Header JP20, JP21 Name PCI9030 Name PCI9030 Functions Functions power supply LA 02 output LA 03 output LA 04 output LA 05 output LA 06 output LA 07 output LA 08 output LA 09 output LA 10 output LA 11 output...
6.5. Solder jumper settings Jumper default Function setting open closed closed motherboard JTAG chain broken Motherboard JTAG chain closed closed Card Power Requirement Indication Card Power Requirement Indication PRSNT1# is open (high) PRSNT1# is low open Card Power Requirement Indication Card Power Requirement Indication PRSNT2# is open (high) PRSNT2# is low...
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6.8.1 Oscillogram, host accesses to the example application at the local bus, local 'ready' controlled...
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Oscillogram, 32bit host write access to the local bus, 6.8.2. (PlxMon command: &ol adr 0h), local 'ready' controlled...
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6.8.3 Oscillogram, 32bit host read access from the local bus, (PlxMon command: &il adr ), local 'ready' controlled...
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6.8.4 Oscillogram, 32bit host write accesss to the local bus, (PlxMon command: &ol adr FFFFh), local 'ready' controlled...
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6.8.5 Oscillogram, 32bit host read access from the local bus with view to a data line LDx, (PlxMon command: &il adr ), local 'ready' controlled...
6.9. Source Code EPLD M4A3-64/32 6.9.1. ABEL based Source Code 6.9.2. VHDL based Source Code In this shortened manual version this chapter is not included.
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