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Wiener AVM16 User Manual

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AVM16 / AVX16
16 channel ADC, 160 MHz
with features extraction
User's Manual
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Summary of Contents for Wiener AVM16

  • Page 1 –N AVM16 / AVX16 16 channel ADC, 160 MHz with features extraction User’s Manual...
  • Page 3 General Remarks The only purpose of this manual is a description of the product. It must not be interpreted as a declaration of conformity for this product including the product and software. -R revises this product and manual without notice. Differences between the description in manual and the product are possible.

  • Page 4: Table Of Contents

    Table of contents: GENERAL SPECIFICATIONS GENERAL DESCRIPTION INPUT CIRCUITRY TRIGGERING Internal trigger functionality External trigger functionality Software trigger TECHNICAL DESCRIPTION OF AVM-16 / AVX-16 Technical description FPGA logic 5.2.1 Window control 5.2.2 Feature Extraction VME addressing Software registers 5.4.1 Overview of registers 5.4.2 First group of registers (control FPGA) 5.4.3...

  • Page 5: General Specifications

    General Specifications Bus standard VME-64, VME-64/VXS No. of channels Input standard LEMO Sampling speed 160 MHz Input voltage range +/- 1.000 V Bandwidth - 10 Hz..100 MHz (DC, full bandwidth option) - 200 kHz..user limited (AC, limited bandwidth) Resolution 12 bit Noise 0.8 LSB (RMS) Buffer length...

  • Page 6: General Description

    General description The AVM-16 / AVX-16 modules contain four quad-channel ADC blocks, a VME / VXS control part and a clock and synchronization utility, see figure 1. AVM-16 / AVX-16 AMP+ADC AMP+ADC Feature AMP+ADC AMP+ADC extraction FPGA AMP+ADC AMP+ADC Feature AMP+ADC AMP+ADC extraction...
  • Page 7 Each of the ADC channel is equipped with a symetrizing amplifier, anti-aliasing filter and an individual 12-bit Analog-to-Digital converter running at 160 Msamples/s. After conversion, the digital data is passed to 4 FPGA circuits providing buffers for data retention and a feature extraction logic. One Spartan-3 FPGA from Xilinx is used for a block of four channel keeping a history of 1024 samples for each channel in it’s internal registers.

  • Page 8: Input Circuitry

    C_fil ADCn AD8132AR TEST PULSE Figure 2: Input symetrizing amplifier and anti-aliasing filter (R5, R7, C2). The gain resistors, the location of the test pulse and the values and locations of capacitors may depend on AVM16 version or be customized.

  • Page 9: Triggering

    Triggering AVM16 / AVX16 can either be trigger internally or externally. The external trigger time is distributed via a broadcast command. Trigger time is used to set time boundaries for scanning the Dual-Ported RAM’s, given user defined trigger latency and trigger window, see figure 3.

  • Page 10: Technical Description Of Avm-16 / Avx-16

    Technical description of AVM-16 / AVX-16 Figure 6. shows location of key connectors user may interface to Figure 4: The AVM-16 / AVX-16 Printed circuit board...

  • Page 11: Technical Description

    XC5VLX50T Figure 5: Chips diagram AVM16/AVX16 works with a sampling frequency of 160 MHz. ADC chips are LTC2240 with 12 Bit resolution. The input circuit differential amplifier is AD8132. The coupling is capacitive, thus the baseline is situated in the middle of the measurement range.

  • Page 12: Fpga Logic

    FPGA logic Data storage and the feature extraction are implemented in programmable logic circuits (FPGA). Each of the FPGAs handles data from 4 ADC channels. 5.2.1 Window control After detection of a trigger, the corresponding time stamp is sent to all ADC FPGAs. With this time stamp the trigger window is determined and all data in the DPRAM within this window are retrieved and analysed.

  • Page 13: Vme Addressing

    * If pileup occurs, the integral Pq is only calculated untill PPi time VME addressing A32/D32 write and read accesses with Address Modifiers (AM) AVM16/AVX16 reacts to 0x09/0x0D, to A32/D32 Block Transfer (BLT) with AM 0x0B/0x0F and to A32/D64 Block Transfer (MBLT) with AM 0x08/0x0C. The base address...

  • Page 14: Software Registers

    Base Address 0x80000000 0x40000000 0x20000000 0x10000000 0x08000000 0x04000000 Table 1: Base Address Settings A switch in the „on“ position means that the corresponding address bit should be 0. Address bits 25:11 must always be 0. If for example only switch 1 is „off“, the address range is 0x04000000 to 0x040007FC.

  • Page 15: First Group Of Registers (Control Fpga)

    0x7FC transfer 5.4.2 First group of registers (control FPGA) ident 0x000 - Board Id. Contains firmware version number. Value Meaning 0x70 AVM16 Module Id 15:8 0x01 Firmware Version (here 0.1) 31:16 Reserved serial 0x004 - User serial number. This number can be programmed by the user and is...
  • Page 16 com_ids 0x008 - In this register there are three identifiers for communication. Meaning Interrupt Request Level (1 to 6) an interrupt is issued if data are available. A 0 disables the interrupt Null 15:8 Interrupt Vector, transmitted Interrupt Acknowledge in order to identify the interrupt 19:16 Data recognition.
  • Page 17 DAC. The height of the test pulse is set by means of this td_dac register. Since the DAC has 8 bits, only bits 11:4 are relevant. offset_dac[4] 0x020 - (Not in all AVM16 version implemented). When no signal is connected, the ADC mean output value is about 0x800, i.e. a signal in one polarity can use only half of the measurement range.

  • Page 18: Registers That Are Sent To All Adc Fpgas Too

    The readback of these registers occurs from a shadow register in VIRTEX-5. 0x100 - Control/Mode Register Bit Name Function General enable. If this bit is not set, AVM16 is in its groud state. All data are deleted. EXTRIG Enables trigger...
  • Page 19 TRIGGER Software Trigger TPULSE Generates a test pulse of 25 ns cha_inh 0x108 - The corresponding channel to each bit (0 bis 15) which is set is inhibited. cha_raw 0x10C - If the corresponding channel to each bit is set all ADC data that are within WINDOW are transmitted and afterward all available analysis data (including start, min and max pairs).

  • Page 20: Registers That Are Individually Available For Every Channel

    minimum between the peaks, where the integral for next peak starts, or by reaching the baseline level for the last peak. With the value in this register it is possible to end the integration earlier when the number of bins reaches the value. aclk_shift 0x12C - The ADC clock must have a fixed phase to the FPGA clock, in order to correctly transmit ADC data.

  • Page 21: Decoding Output

    Figure 8: graphical representation of configuration parameters with details of dX Decoding output The output can be verbose or compact, depending on the value of the cha_raw register for each channel individually. Each 32 bit double word is made of one label, the first word, an one value, the second word.
  • Page 22 number of clock units after the last maximum (start time point) from where a new pulse (even a pile up) can be detected. Maxima and minima computed according to parametrization are found in • Label 0x32: minimum time • Label 0x33: minimum level •...
  • Page 23 Figure 9: upper picture: graphical representation of the extracted features. Lower picture: input parameters with details on SW_INT_LENGTH...
  • Page 24 Example: label 0x037 for channel 2 is: 0x037 + 4 * 2 * 0x10 = 0x0B7 label 0x037 for channel 10 (0xA) is: 0x037 + 4 * 0xA * 0x10 = 0x2B7 Practical example for decoding AVM16 data: Figure 10: representation of the data analysis output...

  • Page 25: Example Of Data Readout

    Example of data readout This examples helps to understand the data analysis and shows how data are extracted from the raw data samples. Data were taken in channel 0. Figure 11: Example of raw data (pileup event with small noise peaks) Sample Raw value Time Hex...
  • Page 26 2087 00B7 2303 018F 2408 01F8 2455 0227 A66 peak 1 2662 02F6 34 -> #FF0 2596 02B4 35 -> #2F6 2649 02E9 2616 02C8 2605 02BD First integral 2580 02A4 11622 2485 0245 2D66 20 -> 2D66 2517 0265 2472 0238 2421...
  • Page 27 2675 0303 2576 02A0 2512 0260 2534 0276 Second integral 2438 0216 15957 2430 020E 3E55 20 -> 3E55 2400 01F0 2309 0195 2339 01B3 2273 0171 2206 012E 2235 014B 2146 00F2 2141 00ED 2133 00E5 2050 0092 2074 00AA 2021 0075...

  • Page 28: Sample Column

    5.6.2 Raw data column Here we have the data as read out from the FIFO. Maxima and minima are highlighted. Only the data in this column and the analysis data (see 5.5) are read out from AVM16. 5.6.3 Time column Here we have the time at which the corresponding raw data value was sampled.

  • Page 29: Absolute Hex

    5.6.7 Absolute hex Translation of absolute column into hex. 5.6.8 Register value Shows the relationship between the data computed by the FPGA and the raw data. This is to verify if the FPGA correctly inferred timing and values of maxima and minima as well as integrals, averages and zero crossing times.
  • Page 31 –N User’s Manual AVM16 / AVX16 Plein & Baus GmbH September 10...
  • Page 33 –N User’s Manual AVM16 / AVX16 Plein & Baus GmbH September 10...

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