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Table of Contents
Summary of Contents for Kaskod CANPC527D
- Page 1 KASKOD 1999 Sankt-Peteterburg...
- Page 2 189625, S Petrsburg, Pavlovsk, Filtrovskoy road, 3 tel.: (812) 466 5784, 476 0795 Fax: (812) 465 3519 E mail : cascod@online.ru kaskod@spb.cityline.ru http://www.kaskod.ru...
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Page 3: Table Of Contents
What exactly happens when an interrupt occurs? Using interrupt in your program Writing an interrupt service routine (ISR) Saving the startup IMR and interrupt vector Common Interrupt mistakes APPENDIX A - CANPC527D Specification APPENDIX B. What is CAN Interface? APPENDIX C. Architectural Overlview... -
Page 4: Can Bus Controller
This filter is designed to meet EMI requirements. Mechanical description The CANPC527D is designed on a ISA form factor. An easy mechanical interface to both PC/104 and EUROCARD systems can be achieved. PUT your CANPC527D directly on a ISA compatible computer using the onboard mounting holes. -
Page 5: Terminal Resistors
User‘s manual Board accessories In addition to the items included in your CANPC527D delivery, several software and hardware accesso- ries are available. Call your distributor for more information on these accessories and for help in choosing the best items to support your distributed control system. - Page 6 CANPC527D The CANPC527D CAN bus interface board has jumper settings which can be changed to suit your applicacation and host computer memory configuration. The factory setting are listed and shown in the diagram in the beginning of this chapter. Fig.1 CANPC527D contains 2 identical optoisolated CAN 2.0B specification channels.
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Page 7: Base Address Jumpers
CANPC527D Base Address Jumpers For base address setting J2 is used. J2 consists of 11 sections, and each section is associated with its address line. Note: Section 0 (connectors 1-2) is reserved for S version. Sections are arranged as following: TABLE 1-2 Thus base address possible range setting is: 080000h-0FFE00h. -
Page 8: Chapter 2 - Board Installation
General installation guidelines: 1. Turn OFF the power to your computer and all devices connected to CANPC527D 2. Touch the grounded metal housing of your computer to discharge any antistatic buildup and then remove the board from its antistatic bag. - Page 9 CANPC527D Chapter 3 - Hardware discription describes the major features of the CANPC527D: the Intel 82527 CAN bus controller, Galvanic isolation of the CAN-bus. Figure 3-1 shows the general block diagram of the CANPC527D. This chapteer describes the major features of the CANPC527D: the Intel 82527 CAN-bus controller, Galvanic isolation of the CAN-bus, the Fiberoptic interface, the Onboard configuration EEPROM, and Digital I/O.
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Page 10: Galvanic Isolation Of The Can Bus
Message object 15 is also buffered to allow the CPU time to service a message received. Galvanic isolation of the CAN-bus The galvanic isolation of the CANPC527D is implemented using 1) Optocouplers for data transmission and 2) a DC/DC converter to supply power to the CAN bus and the physical interface circuitry. -
Page 11: Defining The Memory Map
This chapter shows you how to program and use your CANPC527D. It provides a complete detailed description of the memory map and a detailed discussion of programming operations to aid you in pro- gramming. The full functionality of the CANPC527D is described in the datasheet reprint from Intel on the 82527 CAN controller chip. -
Page 12: End-Of-Interrupt (Eoi) Command
Second, just before exiting the routine, you must clear the interrupt on the CANPC527D by writinf to the 82527 CAN controller, and write the EOI command to the interrupt controller. Finally, when exiting the interrupt routine the processor registers must be popped from the system stack and you must execute the IRET assembly instruction. - Page 13 Push any procesor registers used in your ISR. Most C compiler do this automatically Put the body of your routine here Read interrupt status register of the 82527 chip on your CANPC527D board Clear the interrupt bit by writing to the 82527 CAN controller Issue the EOI command to the 8259 by writing 20h to address 20h Pop all registers.
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Page 14: Common Interrupt Mistakes
The vectors for the hardware interrupts on the XT-bus are vec- tors 8-15., where IRQ0 uses vector 8 and IRQ7 uses vector 15. Thus if your CANPC527D is using IRQ5 it corresponds to vector number 13. - Page 15 CANPC527D Forgetting to clear the IRQ mask bit in the IMR Forgetting to send the EOI command after ISR code. Disables further interrupts. Example on Interrupt vector table setup in C-code: void far_interrupt new_IRQ1_handler(void); /* ISR function prototype */ #define IRQ1_VECTOR...
- Page 16 CANPC527D Host Interface Memory mapped into low memory, occupies 512 bytes Jumper-selectable base address, 11 jumpers 8-bit data bus, 16 bit ISA bus connector CAN Interface – Galvanically isolated transceiver with 1 Mb/s datarate – Timing parameters and speed of bus programmable –...
- Page 17 CANPC527D Overview The Controller Area Network (the CAN bus) is a serial data communications bus for real-time applications. CAN operates at data rates of up to 1 Megabits per second and has excellent error detection and confine- ment capabilities. CAN was originally developed by the German company Robert Bosch for use in the car industry to provide a cost-effective communications bus for in-car electronics and as as alternative to expensive and cumbersome wiring looms.
- Page 18 CANPC527D The Solution The Robert Bosch company (a highly regarded supplier of components and sub systems to the automotive industry) provided the answer in the mid 1980s by specifying the Controller Area Network (CAN). Bosch defined the protocol (subsequently standardised internationally as ISO11898 and ISO 11519) and also licensed a number of companies to allow the design and manufacture of CAN-compliant semicon- ductor controllers and other devices.
- Page 19 CANPC527D Safety The safety-related aspects of using CAN in cars attracted the attention of manufacturers of medical sys- tems. Because of the inherent reliability of the data transmission and the stringent safety requirements that need to be built into medical equipment such as X-ray machines, CAN is now used in a range of these systems.
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Page 20: Bit Encoding
CANPC527D Data Rate vs Bus Length The rate of data transmission depends on the total overall length of the bus and the delays associated with the transceivers. For all ISO11898 compliant devices running at 1Mbit/sec speed, the maximum possible bus length is specified as 40 Metres, For longer bus lengths it is necessary to reduce the bit rate. To give... - Page 21 CANPC527D The ISO11898 standard “Recommends” that bus interface chips be designed so that communication can still continue (but with reduced signal to noise ratio) even if: – Either of the two wires in the bus is broken – Either wire is shorted to power –...
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Page 22: Error Detection
CANPC527D The Benefits Non-destructive bitwise arbitration provides bus allocation on the basis of need, and delivers efficiency benefits that can not be gained from either fixed time schedule allocation (e.g. Token ring) or destructive bus allocation (e.g. Ethernet.) With only the maximum capacity of the bus as a speed limiting factor, CAN will not collapse or lock up. - Page 23 CANPC527D Receivers of the message will automatically delete (de-stuff) such bits before processing the message in any way. Because of the bit stuffing rule, if any receiving node detects six consecutive bits of the same level, a stuff error is flagged.
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Page 24: Message Frames
CANPC527D Error Passive nodes can still transmit and receive messages but are restricted in relation to how they flag any errors that they may detect. The ISO standard (and some of the device data sheets) explain the precise mechanisms in more detail. - Page 25 CANPC527D Fig 1. CAN 2.0A Message Frame A Control Field containing six bits: * two dominant bits (r0 and r1) that are reserved for future use, and * a four bit Data Length Code (DLC). The DLC indicates the number of bytes in the Data Field that follows A Data Field, containing from zero to eight bytes.
- Page 26 CANPC527D – The distinction between the two formats is made using an Identifier Extension (IDE) bit. – A Substitute Remote Request (SRR) bit is also included in the Arbitration Field. The SRR bit is always transmitted as a recessive bit to ensure that, in the case of arbitration between a Standard Data Frame and an Extended Data Frame, the Standard Data Frame will always have priority if both messages have the same base (11 bit) identifier.
- Page 27 CANPC527D Phase-seg2 is a buffer segment that may be shortened during resynchronisation (described below) to compensate for negative phase errors and oscillator drift. The Sample point is always at the end of Phase-seg1 and is the time at which the bus level is read and interpreted as the value of the current bit.