Alcor Micro AU9412EEP Technical Reference Manual

Usb keyboard/hub controller

Advertisement

Quick Links

AU9412EEP
USB Keyboard/Hub Controller
Technical Reference Manual
Revision 1.03
© 1998 Alcor Micro Inc.
All rights reserved

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AU9412EEP and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Summary of Contents for Alcor Micro AU9412EEP

  • Page 1 AU9412EEP USB Keyboard/Hub Controller Technical Reference Manual Revision 1.03 © 1998 Alcor Micro Inc. All rights reserved...
  • Page 2 Alcor Micro Inc. reserves the right to change this product without notice. Alcor Micro Inc. makes no warranty for the use of its products and bears no responsibility for any errors which appear in this document. Specifications are subject to change without notice.
  • Page 3: Table Of Contents

    1.2. Features .........................1 2.0 Application Block Diagram ................3 3.0 Pin Assignment....................5 4.0 System Architecture and Reference Design..........10 4.1. AU9412EEP Block Diagram..................10 4.2. Sample Schematics....................10 4.3. Sample Key Matrix Layout Table ................10 5.0 Electrical Characteristics ................10 5.1. Maximum Ratings ....................10 5.2.
  • Page 4 This Page Intentionally Left Blank...
  • Page 5: Introduction

    The AU9412EEP is an integrated USB keyboard and 2 port hub controller chip. The AU9412EEP has a built-in default keyboard matrix, so that it can be directly connected to an 18 x 8 keyboard matrix. The keyboard matrix can be customized via an optional external 512-byte serial EEPROM.
  • Page 6 This Page Intentionally Left Blank INTRODUCTION...
  • Page 7: Application Block Diagram

    2.0 Application Block Diagram The AU9412EEP is a single chip which integrates USB keyboard and hub functionality. The upstream port is connected to the USB system. The downstream ports can be used for a mouse and joystick. APPLICATION BLOCK DIAGRAM...
  • Page 8 This Page Intentionally Left Blank APPLICATION BLOCK DIAGRAM...
  • Page 9: Pin Assignment

    3.0 Pin Assignment The AU9412EEP is a 48-pin dual inline package (DIP). The following figure shows the signal names for each of the pins on the chip. The table on the following page describes each of the pin signals. PIN ASSIGNMENT...
  • Page 10 Table 3-1. Pin Descriptions Pin # Pin Name Description VCC3.3 3.3V output for upstream D+ pull-up; 4 mA USB_DP USB D+ for upstream port. Need external 1.5KΩ pull- up to 3.3V USB_DM USB D- for upstream port USB1_DP USB D+ for downstream port 1. Add 15KΩ pull-down to ground PIN ASSIGNMENT...
  • Page 11 Table 3-1 (continued). Pin Descriptions Pin # Pin Name Description USB1_DM USB D- for downstream port 1. Add 15KΩ pull-down to ground SCAN1_1 Matrix scan line; internal 3.3k pull-up SCAN1_2 Matrix scan line; internal 3.3k pull-up SCAN1_3 Matrix scan line; internal 3.3k pull-up SCAN1_4 Matrix scan line;...
  • Page 12 Table 3-1 (continued). Pin Descriptions Pin # Pin Name Description SCAN2_15 Matrix scan line; 16 mA, internal 33k pull-down SCAN2_16 Matrix scan line; 16 mA, internal 33k pull-down SCAN2_17 Matrix scan line; 16 mA, internal 33k pull-down SCAN2_18 Matrix scan line; 16 mA, internal 33k pull-down EEP_CS Chip select, external EEPROM;...
  • Page 13 Table 3-1 (continued). Pin Descriptions Pin # Pin Name Description RESET# Reset. Active low; Schmitt trigger input +5v power; VDD pad Ground; VSS pad SCAN2_4 Matrix scan line; 16mA, internal 33k pull-down SCAN2_5 Matrix scan line; 16mA, internal 33k pull-down SCAN2_6 Matrix scan line;...
  • Page 14 This Page Intentionally Left Blank PIN ASSIGNMENT...
  • Page 15: System Architecture And Reference Design

    4.0 System Architecture and Reference Design 4.1. AU9412EEP Block Diagram SYSTEM ARCHITECTURE AND REFERENCE DESIGN...
  • Page 16: Sample Schematics

    4.2. Sample Schematics SYSTEM ARCHITECTURE AND REFERENCE DESIGN...
  • Page 17: Sample Key Matrix Layout Table

    4.3. Sample Key Matrix Layout Table This table is the default key matrix. The AU9412EEP can support this matrix without an external EEPROM. Table 4-1. AU9412 Built-in Key Matrix Pause Ctrl_R Ctrl_L Caps < > “ Scr_Lock Alt_L Alt_R Prt_Sc...
  • Page 18 This Page Intentionally Left Blank SYSTEM ARCHITECTURE AND REFERENCE DESIGN...
  • Page 19: Electrical Characteristics

    5.0 Electrical Characteristics 5.1. Maximum Ratings Absolute Maximum Ratings VALUES PARAMETER • • Ambient Operating Temperatures • • Storage Temperature Supply Voltage (Vdd) -0.3V 7.0V 5.2. Recommended Operating Conditions The following table gives the recommended operating conditions for integrated circuits developed with the pad libraries: Symbol Param.
  • Page 20: Crystal Oscillator Circuit Setup For Characterization

    5.3. Crystal Oscillator Circuit Setup for Characterization The following setup was used to measure the open loop voltage gain for crystal oscillator circuits. The feedback resistor serves to bias the circuit at its quiescent operating point and the AC coupling capacitor, Cs, is much larger than C1 and C2. 5.4.
  • Page 21 ABSOLUTE MAXIMUM RATINGS 1, 2 In accordance with the Absoute Maximum Rating System, Voltages are referenced to GND (Ground=0v) SYMBOL PARAMETER CONDITIONS LIMITS UNIT DC supply voltage -0.5 +6.5 DC input diode current Vi<0 DC input voltage Note 3 -0.5 +5.5 DC input voltage range for I/Os -0.5...
  • Page 22 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (Ground=0V). LIMITS • • SYMBOL PARAMETER TEST CONDITIONS C to +86 UNIT VHYS Hysteresis on inputs Vcc=3.0V to 3.6V 50.4 HIGH level input Vcc=3.0V to 3.6V LOW level input Vcc=3.0V to 3.6V Output impedance (HIGH Note 2...
  • Page 23 AC ELECTRICAL CHARACTERISTICS GND=0V, Is = IS=3.0 C=50pf, RL=500ohms LIMITS • • • • SYMBOL PARAMETER WAVFORM C to +86 C to +86 C UNIT tpLH VMO/VPO to D+/D- tpHL Full Speed trise Rise and Fall Times tfall Full Speed tRFM Rise and Fall Time Matching...
  • Page 24 ELECTRICAL CHARACTERISTICS...
  • Page 25: Esd Test Results

    5.5. ESD Test Results Test Description: ESD Testing was performed on a Zapmaster system using the Human- Body-Model (HBM) and Machine-Model (MM), according to MIL-STD 883 and EIAJ IC- 121 respectively. • Human-Body-Model stresses devices by sudden application of a high voltage supplied by a 100pF capacitor through 1.5k-ohm resistance.
  • Page 26: Latch-Up Test Results

    5.6. Latch-Up Test Results Test Description: Latch-Up testing was performed at room ambient using an IMCS-4600 system which applies a stepped voltage to one pin per device with all other pins open except Vdd and Vss which were biased to 5Volts and ground respectively. Testing was started at 5.0V (Positive) or 0V (Negative), and the DUT was biased for 0.5 seconds.
  • Page 27 Test Circuit: Negative Input/Output Overvoltage/Overcurrent Supply Overvoltage Test Latch-Up Data Mode Voltage (V)/Current (mA) Results 11.0 Pass Voltage 11.0 Pass Pass Current Pass Vdd - Vxx Pass ELECTRICAL CHARACTERISTICS...
  • Page 28 This Page Intentionally Left Blank ELECTRICAL CHARACTERISTICS...
  • Page 29: Mechanical Information

    6.0 Mechanical Information Following diagram shows the dimensions of Alcor AU9412EEP 48-DIP package. Measurements are in millimeters; measurements in parenthesis are in inches. MECHANICAL INFORMATION...

Table of Contents