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Dynamic Engineering PCIe3IP User Manual

Pcieip carrier series pci express x1 to ip (industry pack) bridge
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DYNAMIC ENGINEERING
150 DuBois, Suite C Santa Cruz, CA 95060
PCIeIP Carrier Series
IP (Industry Pack) Bridge
Other trademarks and registered trademarks are owned by their respective manufacturers.
(831) 457-8891 Fax (831) 457-4793
www.dyneng.com
sales@dyneng.com
Est. 1988

User Manual

PCI Express x1 to
Models in Group :
PCIe3IP [Released]
PCIe5IP [Released]
VPX2IP [Released]
VPX4IP [Coming soon]
Revision A1.3
December 2016
©2013-2016 by Dynamic Engineering.
Embedded Solutions
Page 1 of 71

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Summary of Contents for Dynamic Engineering PCIe3IP

  • Page 1: User Manual

    IP (Industry Pack) Bridge Models in Group : PCIe3IP [Released] PCIe5IP [Released] VPX2IP [Released] VPX4IP [Coming soon] Revision A1.3 December 2016 ©2013-2016 by Dynamic Engineering. Other trademarks and registered trademarks are owned by their respective manufacturers. Embedded Solutions Page 1 of 71...
  • Page 2 PCIe3IP: PCI Express carrier with 3 IP positions. Fab Number: 10-2014-0202/3 FLASH Rev 0x10 PCIe5IP: PCI Express carrier with 5 IP positions. Fab Number: 10-2015-1601 FLASH Rev 0x10 E m b e d d e d S o l u t i o n s...
  • Page 3 VPX2IP: PCI Express carrier with 2 IP positions. Fab Number: 10-2016-1901 FLASH Rev 0x10 E m b e d d e d S o l u t i o n s P a g e...
  • Page 4 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice.

  • Page 5: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION PROGRAMMING VPX2IP ADDRESS MAP PCIE3IP ADDRESS MAP PCIE5IP ADDRESS MAP PCIEIP RESETS, CLOCKS, & BUS ERROR IP CHANNEL TRANSFER ACTIVITY MONITOR AND LOGIC PCIEIP INTERRUPTS PCIEIP REGISTERS LED DECODE TABLE PCIEIP BOARD FEATURES...
  • Page 6 PCIe3IP LED’s PCIe3IP IP1/IP2 connectivity option PCIe3IP Board Revision PCIE5IP BOARD FEATURES PCIe5IP DIP Switches PCIe5IP LED’s PCIe5IP Board Revision VPX2IP BOARD FEATURES VPX2IP DIP Switches VPX2IP LED’s VPX2IP IP0/IP1 connectivity options VPX2IP Board Revision MECHANICAL APPLICATIONS GUIDE ELECTRICAL AC/DC TIMING...
  • Page 7 For Service Contact: SPECIFICATIONS ORDER INFORMATION Embedded Solutions Page 7 of 71...

  • Page 8: List Of Figures

    PCIeIP IP I/O to 50 pin Header Connections Figure 9 VPX2IP IP Carrier Rear IO Connector Assignment Figure 10 PCIe3IP IP[2:0] I/O to 50 pin J[2:0] Header Diagram Figure 11 VPX2IP IP[1:0] I/O to Condo Header or Rear IO (VPX) connector Diagram Embedded Solutions...

  • Page 9: Product Description

    Product Description The PCIeIP Carrier Series is part of Dynamic Engineering’s IP Compatible family of modular I/O components. The PCIeIP Carrier Series uses a single PCI Express (PCIe) slot or lane (VPX). Products in the PCIeIP Carrier Series covered by this manual include: 1) PCIe3IP - A half-length card providing three IndustryPack Compatible sites.
  • Page 10 IP clock outputs are designed to be “phase stepped” in relation with one another to reduce simultaneous switching noise. For the PCIe3IP and PCIe5IP the rising edge of IP1 clock is 8ns and IP2 clock is 16ns after the rising edge of IP0’s clock.
  • Page 11 PCIeIP beats this aggressive specification by a comfortable margin. For the PCIe3IP/PCIe5IP the IO’s for each IP are brought out to their own 50 pin headers. For the VPX2IP, stuffing options route the IO to either the Condo header or the VPX rear connector.
  • Page 12 The bezel for the PCIe3IP is a special design with accommodation for the right angle header and cable routing for the other two. All of the IO can come through the bezel without wasting another IO position. The bezel incorporates an arm with hinge to allow the side of the bezel to be rotated out of the way to aide in threading the rear IO through the bezel.
  • Page 13 • 1:1 50 pin headers with matched 5 mill trace & spacing widths between IO and header • IP1/IP2 I/O SMT to 50 pin headers trace configuration/stuffing options - PCIe3IP only • Configurable IO routing to Condo header or VPX Rear IO connector – VPX2IP only •...
  • Page 14 The PCIeIP Architecture is the foundation for all the devices in the PCIeIP Carrier Series. The PCIe3IP Block Diagram (Figure 1) and PCIe3IP FPGA Block Diagram (Figure 2) illustrate a 3IP channel design using the PCIeIP Architecture. To create the PCIe5IP two additional IP channels (IP3 &...
  • Page 15 PCIe3IP FPGA Block Diagram Register Channel PCI Express Receive Un-support Request FIFO Core & Read/Write Receive Register Rx Packet Packet Packet Packet Rx Packet Router Processor FIFO Interface PICe3IP IP0 Rx Packet Registers READ Transmit IP1 Rx Packet Completion Packet...

  • Page 16: Theory Of Operation

    PCIe Endpoint. As an Endpoint the PCIeIP is downstream from the Host/Root Complex which detects it and configures it during the enumeration process using PCIe configuration read and write packets. The VPX2IP/PCIe3IP requests a total of 32MB and the PCIe5IP requests 64MB from the Host who provides the requested memory space via BAR0.
  • Page 17 Flow Control DLL packet(s) to inform/update the Host that more space/credit is available inside the PCIeIP. For the VPX2IP/PCIe3IP/PCIe5IP there are three/four/six possible read targets and/or sources for read completion packets, they are: IP[1:0]/IP[2:0]/IP[4:0], and a register access.

  • Page 18: Programming

    We use MS Visual C++ in conjunction with the driver to write our test software. Please consider purchasing the engineering kit for the VPX2IP, PCIe3IP or PCIe5IP; the software kit includes our test suite. In addition Linux and VxWorks drivers and reference suites are available.

  • Page 19: Pcie3Ip Address Map

    8 MB-4KB MEM Space – IP0 0x080_0000 to 0x0FF_FFFF 8 MB MEM Space – IP1 0x100_0000 to 0x17F_FFFF 8 MB MEM Space – IP2 0x180_0000 to 0x1FF_FFFF 8 MB Figure 4 PCIe3IP Base Address Map Embedded Solutions Page 19 of 71...

  • Page 20: Pcie5Ip Address Map

    PCIe5IP Address Map Function Offset Size Registers – IP[2:0] 0x000 – 0x3FF 1K Bytes ID Space – IP0 0x400 to 0x47F 128 Bytes ID Space – IP1 0x480 to 0x4FF 128 Bytes ID Space – IP2 0x500 to 0x57F 128 Bytes ID Space –...
  • Page 21 Third party utilities can be useful to see how your system Memory Map is configured. The interrupt level expected and style is also set in the registry. Dynamic Engineering recommends using the Dynamic Engineering Driver to take care of initialization and device registration.

  • Page 22: Pcieip Resets, Clocks, & Bus Error

    PCIeIP Resets, Clocks, & Bus Error PCI Express Reset (PERST#) summary There are two types of resets in PCIe, both of which are supported by the PCIeIP, they are:  Fundamental Reset (cold or warm) – assertion of PERST# o Cold - Power applied to a cold (non-powered) system. o Warm –...
  • Page 23 PCIeIP Reset* functional behavior PCI Express PERST# assertion response - Each IP’s Reset* is asserted as long as the PERST# is asserted. Once PERST# is de-asserted each channel starts its own 256 millisecond counter, which when it expires causes that channels Reset* to be synchronously de-asserted relative to its clock.
  • Page 24 PCIeIP Clocks Each IP channel on the PCIeIP has its own independent clock (CLK). IP CLK’s are held low until PERST# is de-asserted. Upon de-assertion of PERST# each IP CLK becomes active and runs at 8MHz. Each IP channel’s CLK frequency can be set independently to 32MHz or back to 8MHz at any time without restriction by setting or clearing that channels Clock SEL bit - IPx Control0 Register bit [8].
  • Page 25 A Bus Error event occurs when the PCIeIP initiates an R/W access to an IP and the IP doesn’t assert its ACK* within the predefined number of IP clocks. The number of clocks the PCIeIP waits is determined by the frequency of operation and the setting of the Bus Error timeout select bit.

  • Page 26: Ip Channel Transfer Activity Monitor And Logic

    IP Channel Transfer Activity Monitor and Logic To provide the ability to check an IP channel’s transfer activity status, health, or to enable sequenced IP transfers the PCIeIP contains an IPx Channel Transfer Monitor Register (IPx CTM) for each IP channel. Below is a summary the IPx CTM register bits and logical behavior: ...
  • Page 27 One possible usage example would be as follows: A system engineer wants to issue and ensure completion of 20 Dword transfers (composed of Reads and Writes) to IP0, then do and ensure completion of 20 Dword transfers to IP1, then do and ensure completion of 20 Dword transfers to IP2. To do this with the PCIeIP the engineer could do the following.

  • Page 28: Pcieip Interrupts

    PCIeIP Interrupts This sections purpose is to summarize the PCIeIP Interrupts, Interrupt registers, programmable features usage, and behavior. Here’s a brief description of what’s covered: o Summary of PCIe spec. Interrupt configuration registers o Summary of Interrupt registers/bits contained in the PCIeIP. o Summary of the PCIeIP’s Interrupt specific registers and bits.
  • Page 29 PCIeIP PCI Express INTx# Interrupt Configuration Registers Summary Command Register (offset 0x04)  Interrupt Disable (bit [10]) R/W, 0 = INTx# enabled (default), 1 = INTx# disabled. Status Register (offset 0x06)  Interrupt Status (bit [3]) RO, 0 = no Interrupt pending (default), 1 = Interrupt pending.
  • Page 30 PCIeIP Interrupts and Registers Summary For each IP channel there are four possible interrupt sources.  IPx Force/P5VGOODn Interrupt – Dual source, either user programmable interrupt via register bit or interrupt set due to detection of the 5 volt power source being out of range.
  • Page 31 PCIeIP Interrupt Functional Operation The descriptions of the PCIeIP interrupt behavior to follow refer to the PCIe compliant configuration registers and PCIeIP specific Interrupt registers both of which were summarized in sections 1.0 and 2.0. This was done for the convenience of the reader and should be sufficient for understanding the remainder of this document.
  • Page 32 PCIeIP Interrupt Level/Edge Functionality PCIeIP IPx ICR [11:8] Level/Edge bits individually configure each of a channels four IP interrupts to be either Level or Edge. In Level mode, if an IPx ISR bit (i.e. source) is asserted and enabled when a W1C for that ISR bit occurs, it triggers the de-assert INTA# packet to be generated.
  • Page 33 PCIeIP Interrupt Aggregation PCIeIP contains an Interrupt Aggregation timer and logic that enables the user to program the rate at which an interrupt can be generated. The Interrupt Aggregation enable bit (ICR bit [13]) is =0 off/disabled by default, when enabled (ICR bit [13] = 1) the Interrupt Aggregation timer starts counting and provides a pulse when the user selected time delay is reached.
  • Page 34 PCIeIP IP Interrupts When asserted each of the IP interrupt sources: Force/P5VGOODn, Bus Error, and IntReq[1:0]* if enabled will set their respective bit in the ISR. The current status of the source value can be read at any time by reading the respective IP’s IPx ISR. If the source “goes away”...
  • Page 35 ISR bit, but the IPx ISR bit [1:0] source could be de-asserted/cleared when read if the IP toggles the IntReq[1:0]* pin(s). This would be considered unusual behavior. Dynamic Engineering IP Modules do not operate in this manner.
  • Page 36 Once enabled, the key difference between PCIeIP’s MSI and INTA# interrupt generation is that only one MSI packet will be sent to the Host to indicate an Interrupt assertion. No MSI packet is generated or sent when the ISR interrupt bit or bits are cleared using a W1C.

  • Page 37: Pcieip Registers

    PCIeIP Registers PCIeIP register map – Offset 0x000 to 0x3FF 128 bytes for Global/Carrier Card Registers Offset Register Description 0x00 Switch and LED Control Switch status and LED control 0x04 Reserved 0x08 Interrupt Status Contains Interrupt bits for up to 8 IP’s 0x0C Interrupt Control Interrupt assertion/de-assertion control...
  • Page 38 PCIeIP Register Address Map Register summary notes: Global and IP register locations are the same for the VPX2IP, PCIe3IP and PCIe5IP. Registers for IP’s that are not implemented are reserved. Writes to reserved registers are dropped and reads return 0x0000_0000’s. For the VPX2IP register locations between 0x140 to 0x25F are reserved.
  • Page 39 11 = 32MB space with 127 PH/PD & 32 NPH/NPD credits. Reserved 10:8 FPGA Select [2:0] - TBD (No logic implemented at this time). VPX2IP/PCIe3IP – Value read = SW2 [7:5] switch values. PCIe5IP – Value read: bits[10:9] = 00, bit[8] = SW2 [5] User Switch values/settings Embedded Solutions...
  • Page 40 Reserved Register – Offsets 0x004 Bit(s) Description Attribute Default 31:0 Interrupt Status Register (ISR) – Offset 0x008 When any one or more of these interrupt bits are set an MSI or INTA# interrupt packet will be generated and sent to the Host. The pre-masked source of these bits are contained in the relative IPx Interrupt Status Register (i.e.
  • Page 41 Interrupt Control Register (ICR) – Offset 0x00C Bit(s) Description Attribute Default 31:14 Reserved Interrupt Aggregation enable 0 = Interrupt Aggregation off, Interrupt Aggregation timer & logic disabled. Interrupts will be generated upon occurrence, or after the Interrupt de-assert time has expired (time relative to the last de-assertion).
  • Page 42 IP Slots Available – Indicates # of slots available on carrier 2h or 0x2h = VPX2IP 3h or 0x3h = PCIe3IP 0x5h = PCIe5IP 15:8 CPLD Version ID – [15:12] Major Rev ID, [11:8] Minor Rev ID FPGA Version ID – [7:4] Major Rev ID, [3:0] Minor Rev ID...
  • Page 43 Reserved Registers – Offsets 0x020 -0x07F Bit(s) Description Attribute Default 31:0 IP Control0 Register (IPx CR0) IP0/IP1/IP2/IP3/IP4 - Offset 0x080/0x0E0/0x140/0x1A0 Bit(s) Description Attribute Default 31:19 Reserved IP Reset* pin status 0 = IP Reset* is de-asserted (1), 1 = IP Reset* is asserted (0) Reset IP and IP Channel 0 = Normal IP Reset* operation.
  • Page 44 IP Control0 Register (IPx CR0) IP0/IP1/IP2/IP3/IP4 - Offset 0x080/0x0E0/0x140/0x1A0 Bit(s) Description Attribute Default 31:8 See descriptions on previous page for bits 31:8 Reserved Increment Write Disable - Word Address Offset Selects which 16-bit word is accessed on a 32bit or 64bit write relative to the accesses address.
  • Page 45 IP Control1 Register (IPx CR1) IP0/IP1/IP2/IP3/IP4 - Offset 0x084/0x0E4/0x144/0x1A4/0x204 Bit(s) Description Attribute Default 31:29 IPx Data-in Timing Mux 000 = Normal Timing mode: Warning: Non Zero Values not intended for normal use. Errors will occur with non-zero values. Multiplexors were added the PCIeIP Data and ACK* paths to enable the IP interface’s to meet/exceed the 0ns setup timing.
  • Page 46 IP Interrupt Status Register (IPx ISR) IP0/IP1/IP2/IP3/IP4 - Offset 0x088/0x0E8/0x148/0x1A8/0x208 These bits contain the Interrupt value/setting before the Mask is applied. See PCIeIP Interrupts section for additional details regarding these interrupts. Bit(s) Description Attribute Default 31:6 Reserved for additional IPx Interrupts and/or control IPx Bus Error Interrupt Read RW1C 0 = Indicates a Bus Error has not occurred on a read.
  • Page 47 IP Interrupt Control Register (IPx ICR) IP0/IP1/IP2/IP3/IP4 - Offset 0x08C/0x0EC/0x14C/0x1AC/0x20C Mask bits either mask or allow the Interrupt to progress to the Interrupt Status Register located at offset 0x008. If an Interrupt occurs and is not masked by this register either a legacy INTA# or MSI Interrupt will be generated.
  • Page 48 IPx Channel Transfer Monitor Register (IPx CTM) IP0/IP1/IP2/IP3/IP4 - Offset 0x094/0x0F4/0x154/0x1B4/0x214 This register provides control of and access to IPx’s channel ACK* counter, additionally it provides channel activity status. See IP Channel Transfer Activity Monitor and Logic section for further application/usage details. Bit(s) Description Attribute...

  • Page 49: Led Decode Table

    LED Decode Table LED Select = 0000 - Link and board status Signal Name Description LED[7:4] - Reserved – 0x0 - LED’s are off LED[3] dl_up Data Link Layer is up LED[2] L0 – L0 state has been reached LED[1] poll Polling –...
  • Page 50 LED Select = 0111 - Reserved LED[7:0] Reserved All LED’s off if selected LED Select = 1000 – Posted Header Credits Signal Name Description LED[7:0] tx_ca_ph[7:0] Posted Header Credits – Host Posted header credits available, i.e. provided from/by host. Actual Internal bus is [8:0].
  • Page 51 LED Select = 1101 – Completion Data Credits Signal Name Description LED[7:0] tx_ca_cpld[7:0] Completion Data Credits – Lower 8 LSBs of Completion Data Credits available - provided by host. Internal bus is [12:0]. When [12] =1 infinite credits provided and all LED’s turned on.

  • Page 52: Pcieip Board Features

    PCIeIP Board Features PCIeIP Carrier IP Logic Connector Pin Assignment The figure below gives the pin assignments for each IP’s Module Logic Interface on the PCIeIP. Pins marked n/c below are defined by the specification, but not used on the PCIeIP.

  • Page 53: Pcieip Ip Carrier Io Connector To 50 Pin Header Assignment

    PCIeIP IP Carrier IO Connector to 50 Pin Header Assignment The Figure 5 below gives the default pin assignments for each IP’s Module I/O Interface to 50 pin Header for each of the PCIeIP IP channels (PCIe3IP illustrated). PCIe3IP IP Carrier I/O SMT to 50 pin Header Connections...

  • Page 54: Vpx2Ip Ip Carrier Rear Io Connector Assignment - Option 2

    Notes: VPX_BP = VPX Back Plane side connectivity provided for user convenience; Module 1 IO can be swapped in place of IO from module 0 to balance signaling. See VPX2IP IP0/IP1 connectivity options section/diagram and/or contact Dynamic Engineering for customization Figure 9...

  • Page 55: Pcie3Ip Board Features

    PCIe3IP Board Features PCIe3IP DIP Switches There are two DIP Switches on PCIe3IP, each with 8 switches. They are labeled SW1 and SW2 with bit numbers 7 to 0 and 1/0 for on/off in the silk screen. SW1 is for user purposes. The settings of SW1 can be seen/used by reading the Switch and LED register [7:0] bits which correspond to SW1 [7:0] bit positions.

  • Page 56: Pcie3Ip Led's

    PCIe3IP LED’s The PCIe3IP has sixteen LED’s. All the LED’s are in the upper right hand corner of the PCIe3IP board and are oriented as follows: LED7 ACK0 ACK2 ACK1 LED6 LED5 1.2V LED4 3.3V LED3 PCIe3IP LED Layout 5.0V LED2 12.0V...

  • Page 57: Pcie3Ip Ip1/Ip2 Connectivity Option

    1) By default R0 & R3 are 0 ohm and R1 & R2 are open. 2) R3, R2, R1, R0 are 0402, 1/16W pads - contact Dynamic Engineering for stuffing options. 3) When not stuffed R1 & R2 leave virtually no-stub.

  • Page 58: Pcie3Ip Board Revision

    PCIe3IP Board Revision The current PCIe3IP board revision is 10-2014-0203. At the release of this manual there are no known issues or Errata with this version of the PCIe3IP. Embedded Solutions Page 58 of 71...

  • Page 59: Pcie5Ip Board Features

    PCIe5IP Board Features PCIe5IP DIP Switches There are two DIP Switches on PCIe5IP, each with 8 switches. They are labeled SW1 and SW2 with bit numbers 7 to 0 and O/C for Open/Closed in the silk screen. SW1 is for user purposes. The settings of SW1 can be seen/used by reading the Switch and LED register [7:0] bits which correspond to SW1 [7:0] bit positions.

  • Page 60: Pcie5Ip Led's

    PCIe5IP LED’s The PCIe5IP has eighteen LED’s. All the LED’s are on the upper/top edge of the PCIe5IP board. The voltage within range monitor LEDs and USER LEDs are located at the top center of the board and the ACK[4:0] LED’s are located on the top right corner. Relative to the front top of the board the LED’s are oriented as follows: PCIe5IP LED Layout -12.0V...

  • Page 61: Pcie5Ip Board Revision

    PCIe5IP Board Revision The current PCIe5IP board revision is 10-2015-1601. At the release of this manual this version of the board has the following two issues: o The JTAG port silkscreen has the following error - TDO and TMS are swapped. That is the TDO pin/port is incorrectly labeled/Silk Screened TMS and TMS is incorrectly labeled/Silk Screened TDO o SW2 silkscreen has the following error –...

  • Page 62: Vpx2Ip Board Features

    VPX2IP Board Features VPX2IP DIP Switches There are two DIP Switches on VPX2IP, each with 8 switches. They are labeled SW1 and SW2 with bit numbers 7 to 0 and 1/0 for on/off in the silk screen. SW1 is for user purposes. The settings of SW1 can be seen/used by reading the Switch and LED register [7:0] bits which correspond to SW1 [7:0] bit positions.

  • Page 63: Vpx2Ip Led's

    VPX2IP LED’s The VPX2IP has fifteen LED’s. All the LED’s are located on the upper left hand side of the VPX2IP board and are oriented as follows: VPX2IP LED Layout ACK0 ACK1 LED7 LED6 LED0 12.0V 3.3V 1.5V 1.2V -12.0V The ACK[1:0] LED’s assert when an ACK[1:0]* is asserted on that channels IP bus.

  • Page 64: Vpx2Ip Ip0/Ip1 Connectivity Options

    Standard Rear IO option connects all 32 VPX pairs 4) Differential bus traces are length/impedance matched – standard stuffing options leave virtually no-stub. 5) R0, R1, R2, R3, and R4 are 0402, 1/16W pads - contact Dynamic Engineering for custom stuffing options. Figure 11...

  • Page 65: Vpx2Ip Board Revision

    VPX2IP Board Revision The current VPX2IP board revision is 10-2016-1901. At the release of this manual there are no known issues or Errata with this version of the VPX2IP. Embedded Solutions Page 65 of 71...

  • Page 66: Mechanical

    Mechanical Mechanical section to be available upon next release. Applications Guide Applications Guide section to be available upon next release. Electrical Electrical section to be available upon future release. AC/DC Timing AC/DC Timing section to be available upon future release. Interfacing Some general interfacing guidelines are presented below.

  • Page 67: Construction And Reliability

    Construction and Reliability PCIe Modules while commercial in nature can be conceived and engineered for rugged industrial environments. PCIeIP is constructed out of 0.062 inch thick High Temp FR4 material. Surface mount components are used. Most devices are high pin count compared to mass of the device.

  • Page 68: Warranty And Repair

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.

  • Page 69: Specifications

    50 pin header. Right angle through the bezel for position 0 and vertical headers for positions 1 and 2 for PCIe3IP or positions 1, 2, 3, 4 for PCIe5IP. Bezel has special features for routing rear connector cables through the bezel. VPX2IP - 3U 4HP with bezel or VPX connector/rear IO with blank bezel.
  • Page 70 User 8 position software readable switch 8 software controllable LED's, 5 Power Supply indicator LED’s. IP activity LED’s, one for each IP, 2 for VPX2IP, 3 for PCIe3IP, 5 for the PCIe5IP Embedded Solutions Page 70 of 71...

  • Page 71: Embedded Solutions

    The drivers detect the carrier and installed IP’s, auto load known drivers for the IP’s or IP-Generic [included with driver]. Support for Win7, and Linux with VxWorks in development. All information provided is Copyright Dynamic Engineering Embedded Solutions Page 71 of 71...

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