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Note on Schematic Diagrams:
• All capacitors are in µF unless otherwise noted. (p: pF) 50 WV or
less are not indicated except for electrolytics and tantalums.
• All resistors are in Ω and
1
/
W or less unless otherwise specified.
4
f
: internal tolerance.
• C : panel designation.
• A : B+ Line.
• Power voltage is dc 3V and fed with regulated dc power supply
from DC IN jack (J5001).
• Voltages and waveforms are dc with respect to ground under no-
signal (detuned) conditions.
no mark : PB
[
] : REC
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal production toler-
ances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production toler-
ances.
• Circled numbers refer to waveforms.
• Signal path.
F
: PB
L
: REC
Replacement of IC6001 and IC7003 used in this set requires a
special tool.
• The voltage and waveform of CSP (chip size package) cannot be
measured, because its lead layout is different from that of conven-
tional IC.
• Waveform
1
IC7003 <z/, (XTAL)
2.9 Vp-p
244 ns
1 V/DIV, 100 ns/DIV
ICD-SX25/SX25VTP
SECTION 4

DIAGRAMS

Note on Printed Wiring Boards:
• Y : parts extracted from the conductor side.
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side:
Parts on the pattern face side seen from
(Side B)
the pattern face are indicated.
Parts face side:
Parts on the parts face side seen from
(Side A)
the parts face are indicated.
Replacement of IC6001 and IC7003 used in this set requires a
special tool.
• Lead layouts
Lead layout of
CSP (chip size package)
conventional IC
MEMO
surface
11
11
ICD-SX25/SX25VTP

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