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Summary of Contents for Marvell PXA310
- Page 1 PXA300 and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual, Rev 0.94 Product Number to be assigned at a later date. Doc. No. MV-TBD-00, Rev. A December 13, 2006 Document Classification: Proprietary Information Not approved by Document Control. For review only.
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Page 2: Document Conventions
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. -
Page 3: Table Of Contents
1.2.28 Camera Image Capture Interface ................40 1.2.29 Test ........................42 ® Intel XScale Microarchitecture Compatibility ..............42 System Architecture Overview....................43 2.0.1 Differences Between PXA300 Processor and PXA310 Processor ......43 ® Intel XScale Microarchitecture Implementation Options ...........43 Endianness .........................44 Memory Switch vs. System Bus ..................44 I/O Ordering ........................44 Accessing Peripherals on Internal Peripheral Bus..............45... - Page 4 4.1.1 Differences Between PXA300 and PXA310 Processors ........65 Features..........................65 PXA300 Processors Pin List with Alternate Functions ............66 PXA310 Processor Pin List with Alternate Functions ............75 Signal Descriptions ......................86 Pin Control Unit Overview....................99 4.6.1 Checking for Completion of a Multi-Function Pin Operation........ 100 4.6.2...
- Page 5 5.3.10 GPIO Edge Detect Status Register (GEDRx) ............136 Register Summary ......................137 Services Clock Control Unit .....................141 Overview...........................141 6.1.1 Differences between the PXA300 Processor and PXA310 Processor ....142 Features..........................142 Signal Descriptions ......................142 6.3.1 Processor Oscillator In (PXTAL_IN) and Processor Oscillator Out (PXTAL_OUT) .....................143...
- Page 6 7.3.7 Coprocessor 14: Clock ..................177 Register Summary ......................178 Services Power Management Unit ................... 179 Overview........................... 179 Differences Between the PXA300 Processor and PXA310 Processor......180 Features..........................180 Signal Descriptions ......................181 8.4.1 Hardware Reset (nRESET) ................. 182 8.4.2 Reset Out (nRESET_OUT)..................
- Page 7 8.9.9 Power Management Unit Voltage Change Control Register (PVCR) ....234 8.10 Register Summary ......................236 Slave Power Management Unit ....................237 Overview...........................237 9.1.1 Differences Between PXA300 Processor and PXA310 Processor ......239 Operation ..........................239 9.2.1 Reset Management .....................239 9.2.2 Power Management.....................241 9.2.3 nBATT_FAULT Occurrence.................256 9.2.4...
- Page 8 12.5.3 Interrupt Controller FIQ Pending Registers (ICFP and ICFP2)......365 12.5.4 Interrupt Controller Mask Registers (ICMR and ICMR2) ........370 12.5.5 Interrupt Controller Level Registers (ICLR and ICLR2) ........375 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A...
- Page 9 12.5.8 Interrupt Control Highest Priority Register (ICHP) ..........382 12.6 Register Summary ......................383 Real-Time Clock (RTC) ......................385 13.1 Overview...........................385 13.2 Differences Between the PXA300 Processor and PXA310 Processor ......385 13.3 Features..........................385 13.4 Signal Description......................386 13.5 Operation ..........................386 13.5.1 Timer Module .......................389 13.5.2 Wristwatch Module ....................389...
- Page 10 Signal Descriptions ......................429 15.4 Operation .......................... 430 15.4.1 Performance Monitoring ..................430 15.4.2 PXA300 Processor and PXA310 Processor - Level Performance Events... 430 15.4.3 Debug Functionality ..................... 433 15.5 Register Definitions......................434 15.5.1 Event Select Registers (PML_ESL_(7-0)) ............434 15.5.2 PXA300 Processor and PXA310 Processor Debug Unit (MDU) Configuration...
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Memory Map..........................461 18.1 Overview...........................461 18.2 Differences Between the PXA300 Processor and PXA310 Processor ......461 18.3 Memory-Mapped Registers Summary ................464 18.4 Boot ROM Space......................466 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 11 Not approved by Document Control. - Page 12 Figures 1-1 Block Diagram ..........................23 2-1 Physical Address Map Decode Regions ..................51 3-1 PXA300 and PXA310 Processor Memory Switch Block Diagram ..........63 3-2 Memory Switch Concept......................64 4-1 Pad Module Output Path ......................114 4-2 Pad Module Input Path ......................115 5-1 General-Purpose I/O Block Diagram ..................
- Page 13 2-7 Coprocessor: New CPU ID and JTAG ID Values ...............57 2-8 Processor CPAR Register ......................58 4-1 PXA300 Processors Alternate Function Table ................66 4-2 PXA310 Processor Alternate Function Table ................75 4-3 PXA300 Processors Signal Descriptions..................86 4-4 PXA300 Processor Pad Control Addresses ................101 4-5 PXA310 Processor Pad Control Addresses ................105...
- Page 14 9-19 Processor Power Management Unit Register Summary - Coprocessor Address ....282 10-1 1-Wire Signal Descriptions ....................... 284 10-2 W1CMDR Bit Definitions ......................288 10-3 W1TRR Bit Definitions ......................289 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006...
- Page 15 13-3Valid and Invalid Data For The Wristwatch Register Fields............391 13-4Valid Data for Day of Month (DOM) Field In RYCR..............392 13-5RTTR Bit Definitions .........................399 13-6RTSR Bit Definitions .........................400 13-7RTAR Bit Definitions .........................403 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 15 Not approved by Document Control.
- Page 16 14-10OSSR Bit Definitions....................... 426 14-11OSNR Bit Definitions....................... 426 14-12OS Timers Register Summary ....................427 15-1 PXA300 Processor and PXA310 Processor Performance Monitor Events ......430 15-2 PML_ESEL_(7-0) Bit Definitions ....................435 15-3 MDU_XSCALE_BP Bit Definitions ................... 436 15-4 MDU_2DG_EVENT Bit Definitions ................... 437 15-5 MDU_CW_MATCH Bit Definitions....................
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0.93 functionality; THIS VOLUME ONLY: Added User Model chapter (chapter 4) and December 2006 0.94 partial Marvell rebranding of Volume I (content not edited by tech pubs) Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
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Product Number Developers Manual Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 18 Not approved by Document Control. For review only. -
Page 19: Introduction
Power Manager technology, enabling dynamic scaling of computing performance and power consumption based on application requirements. This chapter presents an overview of the PXA300 processor or PXA310 processor. It also describes documentation conventions and related documents referenced throughout the four-volume set. -
Page 20: Number Representation
Data Types In the context of the ARM* Architecture V5TE, a word consists of 32 bits. As a result, the following naming convention applies to the different data types in the PXA300 processor or PXA310 processor: • 8 bits = byte (abbreviation B) •... -
Page 21: Related Documents
Introduction 1.1.4 Related Documents Table 1-1 lists supplemental documentation for users of the PXA300 processor or PXA310 processor. Contact a Marvell representative for the latest revision of Marvell documents without order numbers. Table 1-1. Supplemental Documentation Title PXA310 Processor and PXA300 Processor Design Guides (PXA310 Design Guide not yet available) -
Page 22: Product Overview
The PXA300 processor or PXA310 processor is available in a discrete package configuration. The PXA300 processor or PXA310 processor is designed to provide a high degree of backward compatibility with the Marvell PXA27x Processor Family, but offers significant performance and feature set enhancements. -
Page 23: Intel Xscale ® Microarchitecture And Core
• Power management control provides power savings via device and system low-power modes. • 128-entry branch target buffer keeps the pipeline filled with statistically correct branch choices. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 24: Multimedia Coprocessor
1.2.4 Power Management The PXA300 processor or PXA310 processor provides a rich set of flexible power-management controls for a wide range of usage models while enabling very low-power operation. The key features include the following: Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright ©... -
Page 25: Power I2C Controller
Dedicated programmable I C-based external regulator interface to power management ICs • 1-Wire controller for battery gauge operations See Vol. I: PXA300 Processor and PXA310 Processor Developers Manual: System and Timer Configuration for more details. 1.2.5 Power I C Controller... -
Page 26: Graphics Controller
Vol. I: System and Timer Configuration Developers Manual 1.2.7 Graphics Controller This chapter describes the overview, requirements, functions, and architecture for the graphics controller that is inside of the PXA300 processor or PXA310 processor graphics controller. The graphics controller features are: • Graphics instruction list parser •... -
Page 27: Performance Monitor
1.2.10 Internal SRAM Memory The PXA300 processor or PXA310 processor provides on-chip SRAM that may be used in a variety of ways to provide higher system performance and lower power by reducing off-chip memory accesses. A typic use of this SRAM is as an LCD frame buffer with display resolutions up to QVGA. -
Page 28: Dynamic Memory Controller
• Programmable powerdown mode for power savings. • Supports 1.8 V low power DDR SDRAM. See Vol. II: PXA300 Processor and PXA310 Processor Developers Manual: Memory Controller Configuration for more details. 1.2.13 Static Memory Controller The static memory controller is used for interfacing to SRAM-like variable latency IO memories and CompactFlash. -
Page 29: Data Flash Controller
• Programmable power-down mode for power savings • Supports 1.8 V and 3.0 V devices. See Vol. II: PXA300 Processor and PXA310 Processor Developers Manual: Memory Controller Configuration for more details. 1.2.14 Data Flash Controller The data flash controller is used to manage external data flash memory that is typically used to hold the operating system image and as a non-volatile mass storage “hard disk drive.”... -
Page 30: Interrupt Controller
A single-counter operating at 3.25 MHz • Four match registers • Watchdog function The PXA300 processor or PXA310 processor also has an additional timer set that provides: • Eight independent channels, each consisting of: — Counter — Match register — Control register •... -
Page 31: Pulse-Width Modulation Unit (Pwm)
Introduction See Vol. I: PXA300 Processor and PXA310 Processor Developers Manual: System and Timer Configuration for more details. 1.2.17 Pulse-Width Modulation Unit (PWM) The PWM unit consists of four independent channels. Data can be provided either by DMA or CPU programmed I/O. -
Page 32: General-Purpose I/O (Gpio)
1.2.19 General-Purpose I/O (GPIO) 128 of the peripheral pins on the PXA300 processor or PXA310 processor also provide software controlled general purpose I/O (GPIO) pin functionality. The key features of the GPIO controller are: • As inputs, GPIO pins can be sampled or programmed to generate an interrupt from either a rising or falling edge •... -
Page 33: Mobile Scalable Link Controller
1.2.22 Serial Ports The PXA300 processor or PXA310 processor provides a rich set of serial controllers for general system use. All ports can be accessed through programmed I/O or through descriptor-based DMA transfers.Pins on ports not being used can be configured as GPIOs. The following sections describe these ports. -
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— nDSR — nDTR — nRI — nDCD See the Vol. IV: PXA300 Processor and PXA310 Processor Developers Manual: Serial Controller Configuration for more details. 1.2.22.2 Consumer Infrared Controller The consumer infrared unit (CIR) enables PXA300 processor or PXA310 processor to remotely control consumer devices such as televisions and VCRs. -
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• Supports fast-mode operation at 400 kbps • Start-of-day operation with 32.768 kHz operation of 100 bits/sec See Vol. IV: PXA300 Processor and PXA310 Processor Developers Manual: Serial Controller Configuration for more details. 1.2.22.4 AC’97 CODEC Interface The AC’97 CODEC interface supports these key features: •... -
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— Default configuration 0 with one interface and control endpoint 0 • Configurable 4-Kbyte memory for endpoint data storage See Vol. IV: PXA300 Processor and PXA310 Processor Developers Manual: Serial Controller Configuration for more details. 1.2.22.6 USB 1.1 Host Controller The USB host controller has the following key features: •... -
Page 37: Lcd Panel Controller
Introduction See Vol. IV: PXA300 Processor and PXA310 Processor Developers Manual: Serial Controller Configuration for more details. 1.2.22.8 Synchronous Serial Ports (SSP) The SSP controllers support these protocols: — Programmable serial protocol (PSP) with programmable frame sync and programmable start and stop delays —... -
Page 38: Mini-Lcd Panel Controller
1.2.24 Mini-LCD Panel Controller The mini-LCD controller provides an interface between the PXA300 processor or PXA310 processor and a flat-panel display module in low-power modes of operation for low power (S0/D1/C2) operation. The mini-LCD controller supports active (TFT) panels only. The LCD controller supports these key features: •... -
Page 39: Multimedia Card, Sd Memory Card, And Sdio Card
Programmable polarity for output enable, frame clock, and line clock • Operates at 39 MHz frequency See Vol. III: PXA300 Processor and PXA310 Processor Developers Manual: Graphics and Input Controller Configuration for more details. 1.2.25 Multimedia Card, SD Memory Card, and SDIO Card The PXA300 processor or PXA310 processor provides two Multimedia Card (MMC)/SD-Card/SDIO interfaces. -
Page 40: Universal Subscriber Id Controller
Polling support • Key debounce logic to check for key debounce for both matrix and direct keypads See Vol. III: PXA300 Processor and PXA310 Processor Developers Manual: Graphics and Input Controller Configuration for more details. 1.2.27 Universal Subscriber ID Controller The PXA300 processor or PXA310 processor provides two Universal Subscriber Identity Module (USIM) interfaces. -
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Color management support for RAW digital viewfinder and video clip capture — Programmable coefficients for 3x3 matrix multiplication for color and tone correction — Programmable coefficients for color space conversion from RGB to YCbCr 4:2:2 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 42: Test
Conforms to the IEEE Std. 1149.1 – 1990 and IEEE Std. 1149.1a-1993, Standard Test Access Port and Boundary-Scan Architecture • Test access port with dedicated pins: TDI, TMS, TCK, nTRST, and TDO See Vol. I: PXA300 Processor and PXA310 Processor Developers Manual: System and Timer Configuration for more details. ® Intel XScale Microarchitecture Compatibility ®... -
Page 43: System Architecture Overview
Intel XScale Microarchitecture Implementation Options The core implementation used in the PXA300 processor or PXA310 processor includes the options outlined in this chapter. Most of these options are specified within the coprocessor register space, as described in ® Section 2.15.1, “Intel XScale Microarchitecture Coprocessor Register Summary”. -
Page 44: Endianness
I/O Ordering The PXA300 processor or PXA310 processor uses queues that accept memory requests from the seven internal masters. System Bus 1 contains the DMA controller, USB host, LCD controller, camera interface, and a bridge to the peripheral buses. -
Page 45: Accessing Peripherals On Internal Peripheral Bus
The processor then uses the programmed I/O mode, via the bridge, to read the remaining bytes from the FIFO. Refer to the individual peripheral chapters for more information. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 46: Peripheral Access On Internal System Buses
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Peripheral Access on Internal System Buses Peripherals on System Bus 1 (for example, LCD controller) and System Bus 2 (for example, 2D graphics controller) mostly use their own internal DMA to access the system. The exception to this is the data flash interface, which uses the system DMA to transfer data. -
Page 47: Semaphores
No on-chip master or process can access a memory location between the load and store portion of a SWP or SWPB to the same location. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 48: Interrupts
Each type of reset, except sleep exit, affects the reset states of the processor pins. For details on how resets affect pin states refer to Section 4.2 of the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification. The Reset Controller Status register contains information that indicates which reset has occurred. -
Page 49: Selecting Peripherals Vs. General-Purpose I/O
2.14 Power-On Reset and Boot Operation Before the devices that use the PXA300 processor or PXA310 processor module/services block are powered on, the external system must assert nRESET and nTRST. To allow the internal clocks to stabilize, all power supplies... -
Page 50: Memory Map And Register Overview
The PXA300 processor or PXA310 processor does not use all register bit locations. The unused bit locations are marked reserved and are allocated for future use. Write reserved bit locations with 0b0. Ignore the values of these bits during read operations, as they are unpredictable. -
Page 51: Intel Xscale ® Microarchitecture Coprocessor Register Summary
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Block Decode Unit Decode (64 Units, Sub-Unit Decode (1 Mbyte); for the PXA300 processor or PXA310 processor (64 Blocks, 64 Mbytes 1 Mbyte each) -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 2-3. Coprocessor Register Summary (Sheet 2 of 3) Register Opcode1 Opcode2 Register Description Symbol Coprocessor 14 — Clock and Power Management CCLKCFG Core Clock Configuration Register... -
Page 53: Interrupt Controller Registers
† These registers are also accessible through memory-map addressing. 2.15.2 Interrupt Controller Registers Access: Coprocessor 6 The interrupt controller registers can be accessed in either of two modes: Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 53 Not approved by Document Control. -
Page 54: Performance Monitoring Registers
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • Memory-mapped register access mode • Coprocessor-register access mode Coprocessor-register access mode results in significantly reduced interrupt latencies. Accessing the interrupt controller registers in coprocessor-register access mode must be performed in supervisor mode.The MRC and MRC2 coprocessor operations are treated identically and access the same registers within the coprocessor. -
Page 55: Clock Configuration And Power Management Registers
USIM normal operation 2.15.5 Coprocessor Software Debug Registers Access: Coprocessor 14, registers 8 through 14 Coprocessor 15, register 14 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 55 Not approved by Document Control. For review only. -
Page 56: Coprocessor 15
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual These registers are used for software debug. 2.15.6 Coprocessor 15 The following subsections describe the registers available in coprocessor 15: • Section 2.15.6.1, “Processor ID Register” •... -
Page 57: Coprocessor: New Cpu Id And Jtag Id Values
Bit 1 of the Auxiliary Control register is defined as the page table memory attribute (P-bit). It is not implemented in the PXA300 processor or PXA310 processor and must be written with 0b0. Similarly, the P-bit in the memory-management unit (MMU) page table descriptor is not implemented and must be written with 0b0. -
Page 58: Processor Cpar Register
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Example 2-1 demonstrates setting the CPAR while in supervisor mode. Table 2-8. Processor CPAR Register Coprocessor 15 Register 15 Processor CPAR Register Processor CPAR opcode_2 = 0... -
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CP15 side effect might occur before CPWAIT completes or is issued. Use the technique shown in Example 2-2 to ensure that this does not affect the correctness of the code. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 12/13/06 Marvell Page 60 Document Classification: Proprietary Information December 13, 2006 Not approved by Document Control. For review only. -
Page 61: Memory Switch
Memory Switch Overview This chapter documents the PXA300 processor or PXA310 processor internal switch bus (memory switch) that provides a dedicated connection to/from the initiators (core subsystem, system bus #1, and system bus #2) to the completers (external static-memory controller, external dynamic-memory controller, internal SRAM memory controller, system bus #1, and system bus #2) for the data transfers. -
Page 62: I/O Pins
Vol. I: System and Timer Configuration Developers Manual • Completers execute transactions in order for each initiator I/O Pins The PXA300 processor or PXA310 processor memory switch bus has no external IO interface. Functional Description The memory switch bus consists of the following interface modules: •... -
Page 63: Pxa300 And Pxa310 Processor Memory Switch Block Diagram
Memory Switch Figure 3-1. PXA300 and PXA310 Processor Memory Switch Block Diagram Core Subsystem Interface Internal SRAM Interface Interface Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 63 Not approved by Document Control. For review only. -
Page 64: The Memory Switch Concept
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 3.4.2 The Memory Switch Concept The memory switch bus is responsible for handling the read and write address, data, and related attributes from the initiators to the completers. -
Page 65: Pin Descriptions And Control
Pin Descriptions and Control This chapter describes both the PXA300 processor and the PXA310 processor logical signals and their mapping to physical package pins. Overview The PXA300 processor and the PXA310 processor both feature single-function (dedicated) and multi-function pins. The pin-control unit manages the configuration of these multi-function pins, including the selection of alternate peripheral functions, and controls the pin state during reset and low-power modes for every pin. -
Page 66: Pxa300 Processors Pin List With Alternate Functions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 4-66 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 4-70 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
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Page 75: Pxa310 Processor Pin List With Alternate Functions
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 4-78 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 4-80 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 4-81 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 4-82 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 4-84 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
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Page 86: Signal Descriptions
Signal Descriptions Table 4-3 describes the PXA300 processor and the PXA310 processor signals used by each interface. Most of the processor pins are multiplexed so that they can be configured for one of the up to eight available functions using the MFPR xx registers. -
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ND_nRE Output flash. ND_nWE Output Third Party data Flash Write Enable—Enables writes to Third Party data flash. Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 87 Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-3. PXA300 Processors Signal Descriptions (Sheet 3 of 14) Signal Name Type Signal Descriptions Data Flash Address—Low-order address bits for the current static memory access on the data flash interface. -
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MultiMediaCard Chip Select 1—MMC/SD/SDIO Controller #1 MM1_DAT3/MM1_CS1 Bidirectional bidirectional line for read and write data. Used only for SD 4-bit data transfers SPI: chip select 1 Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 89 Not approved by Document Control. -
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Used only for SD 4-bit data transfers SPI: chip select 1 MultiMediaCard/SD/SDIO Controller #3 Signals Important: Controller #3 Is An Addition To PXA310 Processor Only MM3_CLK Output MultiMediaCard and SD Card Bus Clock—MMC/SD/SDIO Controller #3 MultiMediaCard Command—MMC/SD/SDIO Controller #3... -
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Synchronous Serial Port External Clock 2—this input may be used to supply an Input KEN2 external bit clock or an external enable request for the internally generated bit clock. Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-3. PXA300 Processors Signal Descriptions (Sheet 7 of 14) Signal Name Type Signal Descriptions Synchronous Serial Port 2 System Clock—When enabled, provides a reference clock SSPSYSCLK2 Output at four times the Port 2 bit clock. -
Page 93: Not Approved By Document Control. For Review Only
UTMI Clock—connect to the clock output of an external UTMI transceiver. U2D_DATA<7:0> Bidirectional UTMI Data Bus—connect to the data bus of an external UTMI transceiver. Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 93 Not approved by Document Control. -
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UTMI Operating Mode—These signals are used instead of U2D_OPMODE<1:0> when Output SCAN using boundary scan. USB 2.0 High-Speed Client UPLI Transceiver Interface Signals IMPORTANT: The ULPI Interface Is Available On PXA310 Processor Only Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 94... -
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Pulse Width Modulation Channel 1—pulse width modulator channel 1 output PWM<0> Output Pulse Width Modulation Channel 0—pulse width modulator channel 0 output Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 95 Not approved by Document Control. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-3. PXA300 Processors Signal Descriptions (Sheet 11 of 14) Signal Name Type Signal Descriptions General-Purpose I/O Signals General-Purpose I/O signals—these software managed logical I/O channels support interrupt generation with rising and/or falling edge detection. -
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JTAG Test Data Input—data from the external JTAG controller is sent to the PXA300 Input processor and the PXA310 processor using this signal. This pin has an internal pullup resistor. JTAG Test Data Output—data from the PXA300 processor and the PXA310 processor Output is returned to the external JTAG controller using this signal. -
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Test Clock—reserved for manufacturing test. Must be grounded for normal operation. Power Supplies NOTE: Voltages provided in this section are nominal and for reference only. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for complete voltage specification details. -
Page 99: Pin Control Unit Overview
To program multiple pins (for example to select all the pins for a multi- pin function such as a UART), several registers need to be programmed in series. Each register operation can occur in a slightly Copyright © 2006 Marvell CONFIDENTIAL Doc. -
Page 100: Checking For Completion Of A Multi-Function Pin Operation
(for example open collector, three-state drive etc.). Note: The mechanism differs considerably from previous versions of this function (for example, on the Marvell PXA270 processor) where a control was provided to ignore the input of the pad (the RDH control). -
Page 101: Pxa300 Processor Pad Control Addresses
DF_NCS1 VCC_DF 0x40E1_0278 DF_nWE VCC_DF 0x40E1_00CC DF_nRE VCC_DF 0x40E1_0200 GPIO0 VCC_DF 0x40E1_00B4 Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 101 Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-4. PXA300 Processor Pad Control Addresses (Sheet 2 of 5) Pin Name Power Supply Pad Control Address GPIO1 VCC_DF 0x40E1_00B8 GPIO2 VCC_DF 0x40E1_00BC GPIO3 VCC_CARD1 0x40E1_027C... -
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GPIO69 VCC_LCD 0x40E1_04A8 GPIO70 VCC_LCD 0x40E1_04AC GPIO71 VCC_LCD 0x40E1_04B0 GPIO72 VCC_LCD 0x40E1_04B4 Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 103 Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-4. PXA300 Processor Pad Control Addresses (Sheet 4 of 5) Pin Name Power Supply Pad Control Address GPIO73 VCC_LCD 0x40E1_04B8 GPIO74 VCC_LCD 0x40E1_04BC GPIO75 VCC_LCD 0x40E1_04C0... -
Page 105: Pxa310 Processor Pad Control Addresses
0x40E1_02DC GPIO3_2 VCC_IO3 0x40E1_02E0 GPIO4_2 VCC_IO3 0x40E1_02E4 GPIO5_2 VCC_IO3 0x40E1_02E8 GPIO6_2 VCC_IO3 0x40E1_02EC Table 4-5. PXA310 Processor Pad Control Addresses (Sheet 1 of 6) Pin Name Power Supply Pad Control Address DF_IO0 VCC_DF 0x40E1_0220 DF_IO1 VCC_DF 0x40E1_0228 DF_IO2 VCC_DF 0x40E1_0230... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-5. PXA310 Processor Pad Control Addresses (Sheet 2 of 6) Pin Name Power Supply Pad Control Address DF_IO6 VCC_DF 0x40E1_0268 DF_IO7 VCC_DF 0x40E1_0270 DF_IO8 VCC_DF 0x40E1_0224... -
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Table 4-5. PXA310 Processor Pad Control Addresses (Sheet 3 of 6) Pin Name Power Supply Pad Control Address GPIO8 VCC_CARD1 0x40E1_0290 GPIO9 VCC_CARD2 0x40E1_0294 GPIO10 VCC_CARD2 0x40E1_0298 GPIO11 VCC_CARD2 0x40E1_029C GPIO12 VCC_CARD2 0x40E1_02A0 GPIO13 VCC_CARD2 0x40E1_02A4 GPIO14 VCC_CARD2 0x40E1_02A8 GPIO15... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-5. PXA310 Processor Pad Control Addresses (Sheet 4 of 6) Pin Name Power Supply Pad Control Address GPIO44 VCC_CI 0x40E1_0444 GPIO45 VCC_CI 0x40E1_0448 GPIO46 VCC_CI 0x40E1_044C... -
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Table 4-5. PXA310 Processor Pad Control Addresses (Sheet 5 of 6) Pin Name Power Supply Pad Control Address GPIO80 VCC_MSL 0x40E1_04D4 GPIO81 VCC_MSL 0x40E1_04D8 GPIO82 VCC_MSL 0x40E1_04DC GPIO83 VCC_MSL 0x40E1_04E0 GPIO84 VCC_MSL 0x40E1_04E4 GPIO85 VCC_MSL 0x40E1_04E8 GPIO86 VCC_MSL 0x40E1_04EC GPIO87... -
Page 110: Register Descriptions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-5. PXA310 Processor Pad Control Addresses (Sheet 6 of 6) Pin Name Power Supply Pad Control Address GPIO116 VCC_IO1 0x40E1_0644 GPIO117 VCC_IO1 0x40E1_0648 GPIO118 VCC_IO1 0x40E1_064C... -
Page 111: Mfpr Bit Definitions
SLEEP_DAT The data on the pad sent during D1-D3 low power mode (see Section 4.10 Read/Write for more information). Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 111... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 4-6. MFPR Bit Definitions (Sheet 2 of 2) Physical Address MFPR xx Padring 0x40E1 XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 113: Multi-Function Pin Block Diagram
UART. This configuration raises the issue of potentially floating inputs if some device is not always driving the input. Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 114: Pad Module Output Path
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 4-1. Pad Module Output Path Multiplexer Multiplexer Data In Output High Multiplexer Multiplexer PULLUP EN Multiplexer Multiplexer PULLDOWN Multiplexer Multiplexer Output OUTPUT_E Multiplexer Sleep State Sleep... -
Page 115: Pad Module Input Path
Edge rise EN Delay Edge Fall en Output EDGE Detect EDGE Clear Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 115 Not approved by Document Control. For review only. -
Page 116: Edge-Detect Operation
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Edge-Detect Operation Each multi-function pin can detect a rising or falling edge on the input (when enabled, this monitors the pin at all times so an output transition would trigger it). The detection is controlled via the EDGE_CLEAR (which enables and disables the function), and the edge_rise (if enabled, causes an event on rising edge), and the edge_fall (if enabled causes an event on falling edge) register bits. -
Page 117: Sleep_Sel And Rdh Multi-Function Pin State Summary
SSP ports, depending upon the characteristics of the SSP devices. Some multi-function pins that would never use this functionality, for example, the DFI pins. Copyright © 2006 Marvell CONFIDENTIAL Doc. -
Page 118: Wakeup Detection
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 4.11 Wakeup Detection There are three main sets of wakeup detection: services, peripheral controller, and generic wakeups. A wakeup in this context is not necessarily the same as an interrupt. -
Page 119: Generic Wakeups
GPIO56, GPIO60, or GPIO62 are set. Refer to Table 4-10. For Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006, Preliminary Document Classification: Proprietary Information Page 119 Not approved by Document Control. -
Page 120: Wake-Up Functionality On Multi-Function Pins
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual instance, on this second level read of GPLR1, if GPLR1[28] corresponding to GPIO60 is set, this indicates that activity on the multi-function pins assigned to the I2C controllers SCL or SDA alternate function caused the wakeup event. -
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In this example, GPIO71 is connected into the SSP3 controller on the SSPRXD3 signal; any activity on GPIO71 is observable by the SSP3 controller. Copyright © 2006 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 2006 Marvell Page 122 Document Classification: Proprietary Information December 13, 2006, Preliminary Not approved by Document Control. For review only. -
Page 123: General-Purpose I/O Unit
GPIOs. It is necessary to understand the operation of both the GPIO control logic and the multi-function pin control logic to understand the operation of the GPIOs in the PXA300 processor or PXA310 processor processor. It is possible for a system to use the GPIO functions internally and not actually connect to a physical pin. -
Page 124: Features
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual Figure 5-1. General-Purpose I/O Block Diagram Pin Direction Register Pin Set and Clear Registers Processor Edge Detect Edge Status Register Detect Rising Edge Detect Enable Register Falling Edge Detect... -
Page 125: Register Descriptions
— 4 bit-wise Clear registers GCDRx (write-only)—Modifies value of GPDR. See Section 5.3.4, “GPIO Pin Bit-Wise Clear Direction Registers (GCDRx)” on page 5-129. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 125 Not approved by Document Control. -
Page 126: Gpio Pin-Level Registers (Gplrx)
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual • 8 registers control port state: — GPSRx (write-only)—Sets GPIO output port — GPCRx (write-only)—Clears GPIO output port Section 5.3.5, “GPIO Pin Output Set Registers (GPSRx) and Pin Output Clear Registers (GPCRx)”... -
Page 127: Gpio Pin Direction Registers (Gpdrx)
Note: At reset, all bits in this register are cleared configuring all GPIO ports as inputs. Table 5-3 shows the location of each port direction bit in the GPIO Pin Direction register, GPDR0. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 128: Gpio Pin Bit-Wise Set Direction Registers (Gsdrx)
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual Table 5-3. GPDR Bit Definitions Physical Address 0x40E0_000C GPDR0 0x40E0_0010 GPDR1 GPIO Controller 0x40E0_0014 GPDR2 0x40E0_010C GPDR3 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 129: Gpio Pin Bit-Wise Clear Direction Registers (Gcdrx)
Note: At reset, all bits in this register are cleared configuring all GPIO ports as inputs. Table 5-5 shows the location of each port direction bit in the GPIO Pin Direction register, GCDR0. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 130: Gpio Pin Output Set Registers (Gpsrx) And Pin Output Clear Registers (Gpcrx)
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual Table 5-5. GCDR Bit Definitions Physical Address 0x40E0_0420 GCDR0 0x40E0_0424 GCDR1 GPIO Controller 0x40E0_0428 GCDR2 0x40E0_042C GCDR3 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 131: Gpio Rising-Edge Detect-Enable Registers (Grerx)
Each GPIO can be programmed to detect a rising edge, falling edge, or either transition on a port. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for the minimum pulse width to guarantee a detection. When an edge is detected that matches the type of edge programmed for the port, a status bit is set. -
Page 132: Gpio Bit-Wise Set Rising-Edge (Gsrerx) And Gpio Bit-Wise Clear Rising-Edge (Gcrerx) Detect-Enable Registers
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual the port transitions from logic level low to logic level high. Likewise, GFERx is used to set the corresponding GEDRx status bit when a transition from logic level high to logic level low occurs. When the corresponding bits are set in both registers, either a falling- or a rising-edge transition causes the corresponding GEDRx status bit to be set. -
Page 133: Gsrerx Bit Definitions
Clear GPIO Rising Edge detect enable n (where n = 0 through 31) PD{n} 0 – GRER bit not affected 1 – GRER bit is cleared Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 133 Not approved by Document Control. -
Page 134: Gpio Falling-Edge Detect-Enable Registers (Gferx)
Each GPIO can be programmed to detect a rising edge, falling edge, or either transition on a port. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for the minimum pulse width to guarantee a detection. When an edge is detected that matches the type of edge programmed for the port, a status bit is set. -
Page 135: Gsfer Bit Definitions
Set GPIO Falling Edge detect enable n (where n = 0 through 31) PD{n} 0 – GFER bit not affected 1 – GFER bit is set Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 135 Not approved by Document Control. -
Page 136: Gpio Edge Detect Status Register (Gedrx)
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual Table 5-13. GCFER Bit Definitions Physical Address 0x40E0_04A0 GCFER0 0x40E0_04A4 GCFER1 GPIO Controller 0x40E0_04A8 GCFER2 0x40E0_04AC GCFER3 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 137: Register Summary
0x40E0_0034 GRER1 GPIO Rising-Edge Detect Enable register GPIO[63:32] 0x40E0_0038 GRER2 GPIO Rising-Edge Detect Enable register GPIO[95:64] Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 137 Not approved by Document Control. For review only. -
Page 138: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual Table 5-15. GPIO Register Summary (Sheet 2 of 3) Nos. Address Name Description Page 0x40E0_003C GFER0 GPIO Falling-Edge Detect Enable register GPIO[31:0] 0x40E0_0040 GFER1 GPIO Falling-Edge Detect Enable register GPIO[63:32]... -
Page 139: Not Approved By Document Control. For Review Only
Bit-wise Clear of GPIO Falling Edge Detect Enable 0x40E0_04AC GCFER3 register GFER [127:96] 0x40E0_04B0– — Reserved 0x40EF_FFFF Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 139 Not approved by Document Control. For review only. -
Page 140: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: Timer and System Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 12/13/06 Marvell Page 140 Document Classification: Proprietary Information December 13, 2006 Not approved by Document Control. For review only. -
Page 141: Services Clock Control Unit
Services Clock Control Unit Overview This PXA300 processor or PXA310 processor is built using a modular “system-on-a-chip” architecture designed to manage multiple subsystems with unique power-management and clocking requirements. This architecture supports the integration of both an application processor and one or more communication subsystems even though the PXA300 processor or PXA310 processor does not integrate any communications subsystems. -
Page 142: Differences Between The Pxa300 Processor And Pxa310 Processor
(when ACCR[PCCE] is set). 6.1.1 Differences between the PXA300 Processor and PXA310 Processor There are no differences between the PXA300 processor and PXA310 processor in this section. Features The services clock control unit includes the following features: •... -
Page 143: Processor Oscillator In (Pxtal_In) And Processor Oscillator Out (Pxtal_Out)
Oscillator Out (PXTAL_OUT) PXTAL_IN and PXTAL_OUT are clock I/O signals that supply 13-MHz clocks to the system. If an external clock source is used, the input frequency must be 13 MHz. See PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification. -
Page 144: Timekeeping Clock Output (Clk_Tout)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 6.3.4 Timekeeping Clock Output (CLK_TOUT) The CLK_TOUT signal outputs a buffered version of the TXTAL_IN oscillator input. The CLK_TOUT signal can be used to provide a 32.768-kHz clock for output to the external system. The CLK_TOUT signal can be enabled and disabled in S0, S2, or S3 states using the respective OSCC[TENSx] bit. -
Page 145: Processor Oscillator (13 Mhz)
VCTCXO_EN is negated in S2 and S3 and is asserted in S0 when the processor oscillator clock is required. The processor oscillator clock is required when the PEN bit in the “Oscillator Configuration Register (OSCC)” is set to 1. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 145 Not approved by Document Control. -
Page 146: Timekeeping Oscillator (32.768 Khz)
For lowest power consumption, a 32.768-kHz crystal must be connected between the TXTAL_IN and TXTAL_OUT pins. However, some applications may have other clock sources of the same frequency, and can reduce overall cost by driving the PXA300 processor or PXA310 processor TXTAL_IN pin externally while grounding the TXTAL_OUT pin. -
Page 147: Ring Oscillator (120 Mhz ± 15%, 40 Mhz ± 5%)
PMU is in D0 or D1 power modes. When the PXA300 processor or PXA310 processor PMU is in D1 power mode, the 40 MHz ring oscillator is enabled to output the 40-MHz clock for the mini-LCD panel controller; the core does not use the 40-MHz clock. When the PXA300 processor or PXA310 processor PMU is in D0 mode, the 120 MHz ring oscillator is enabled to output the 120-MHz clock. -
Page 148: Oscc Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 6-3. OSCC Bit Definitions (Sheet 1 of 2) Physical Address Services Unit Clock 0x4135_0000 OSCC Control Unit User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 149: Register Summary
Table 6-4. Services Unit Clock Control Unit Register Summary Address Name Description Page 0x4135_0000 OSCC Oscillator Configuration register Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 149 Not approved by Document Control. For review only. -
Page 150: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 12/13/06 Marvell Page 150 Document Classification: Proprietary Information December 13, 2006 Not approved by Document Control. For review only. -
Page 151: Slave Clock Control Unit
Ring oscillator (120 MHz ± 15%)—Creates the fixed-frequency clocks used during S0/D0 mode (if selected), S3 low-power reset exit (if enabled), and power-mode startup operation (if enabled). There are no differences between the PXA300 processor or PXA310 processor for the BCCU. See Overview in Chapter 6, “Services Unit Clock Control... -
Page 152: Core Phase-Locked Loop (104-624 Mhz)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • System PLL clock is 624 MHz. Most of the fixed-frequency clocks are derived from this clock. • The high-speed I/O (HSIO) bus clock is derived from the system PLL and is not related to the core clocks. -
Page 153: Core Pll, Turbo And Run Mode Output Frequencies
Table 7-3. Intel XScale® Core PLL, Turbo and Run Mode Output Frequencies (Sheet 1 of 2) Frequency (MHz) Ring — Oscillator* † — 19.5 — Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 153 Not approved by Document Control. For review only. -
Page 154: Not Approved By Document Control. For Review Only
D2, D3, or D4 power modes, so no clocks are provided in these power modes. 7.2.2.1 Turbo/Run Mode Note: This definition of turbo vs. run for PXA300 processor or PXA310 processor is different from the ® one used in previous generations of Intel XScale processors. -
Page 155: Not Approved By Document Control. For Review Only
Note: A core frequency change may be executed automatically due to a high temperature Frequency and Voltage change, if the PVCR[TVE] bit is set. Refer to the Services Power Management Unit Chapter fo details. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 156: System Phase-Locked Loop (624 Mhz)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Warning: Writing different values to XL and XN bits in ACCR register must be followed by writing 1 to F-bit in “Application Core Clock Configuration Register (XCLKCFG)” register. -
Page 157: Devices Operating In D0Cs Mode
PLL is not used (D1, D2, D3 or D4), the core PLL is disabled and powered down. When the processor exits the power mode where the core PLL was powered down, the BCCU optionally provides the core with clocks from Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 158: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual the ring oscillator while the core PLL is enabled and locked. Once the core PLL output is locked and stable, the BCCU transitions the core to the core PLL outputs by stopping their clocks for a short duration and switching them to the core PLL clocks. -
Page 159: Not Approved By Document Control. For Review Only
Software is allowed to proceed but with no state change. An exit sequence takes the PXA300 processor out of D0CS and places it in regular PLL run mode (D0). Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 160: Ring Oscillator (40 Mhz ± 5%) During D1 Mode
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Warning: A core clock frequency/turbo change operation is not allowed while in D0CS 7.2.4.6 Non-CP14 Commands While in D0CS Aside from the coprocessor commands discussed in Section 7.2.4.5, “CP14 Commands While in D0CS”,... -
Page 161: Performing Peripheral Frequency Changes
• All core loads are completed, and core stores are sent to the core system bus. • The core clock is stopped. The core PLL remains enabled. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 162: Core Idle Mode Coupled With Software-Controlled Voltage Changes
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • Core interrupts are no longer held and are recognized as wake-up sources from idle mode. When the core is in idle mode, all peripherals and system resources are fully operational except that the core clock is stopped. -
Page 163: Application Subsystem Clock Configuration Register (Accr)
Once the PLL outputs are locked and stable, the processor clocks are started with the PLL outputs. In this case, no software intervention is necessary (or possible, given the absence of clocks). Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 164: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Note 1:In the case of a low-power mode exit with PCCE=1, software has the option of not switching the clocks over to PLLs and continuing to run off the ring oscillator. While operating in this mode, it is entirely legitimate for software to issue a second low-power mode-entry command. -
Page 165: Accr Bit Definitions
1 = System PLL is disabled and will not be used after a frequency change NOTE: System PLL can only be disabled after entering D0CS mode and can only be enabled after exiting D0CS mode. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 166: Not Approved By Document Control. For Review Only
Reset 0 Bits Access Name Description Video Accelerator Unit Frequency Select These bit fields are only available in the PXA300 or PXA310 processor. 0b00 -- 104 MHz 29:28 VAUF 0b01 -- 156MHz 0b10 -- 208 MHz 0b11 -- 78 MHz —... -
Page 167: Not Approved By Document Control. For Review Only
There is a complex protocol for changing the value of this field. For details on changing the DDR SDRAM frequency, Refer to the DMEMC (Dynamic Memory Controller) chapter for step-by-step instructions. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 168: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 7-6. ACCR Bit Definitions (Sheet 4 of 4) Physical Address BCCU 4134_0000 ACCR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 169: Application Subsystem Clock Status Register (Acsr)
SPDIS_S Power mode change PLL status change XPDIS_S Power mode change This is a read-only register. Ignore reads from reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 169... -
Page 170: Acsr Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 7-8. ACSR Bit Definitions (Sheet 1 of 2) Physical Address BCCU 4134_0004 ACSR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 171: Not Approved By Document Control. For Review Only
— reserved Run-Mode-to-Processor (13 MHz) Oscillator Ratio (XL) Status XL_S For the core PLL (Reset value = 0b0_1000 for XL = 8) Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 171... -
Page 172: Application Subsystem Interrupt Control/Status Register (Aicsr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 7.3.3 Application Subsystem Interrupt Control/Status Register (AICSR) The AICSR is used to enable/disable the frequency-change interrupt and to provide status to indicate if the core clocks are using the core PLL clocks following a frequency-change operation. Writing a 1 to any of the status bits resets them to 0. -
Page 173: D0 Mode Clock Enable Register A (D0Cken_A)
Dynamic Memory Controller Clock EN CKEN[23] UART3 Clock Enable CKEN[7] reserved CKEN[22] UART1 Clock Enable CKEN[6] reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 173 Not approved by Document Control. For review only. -
Page 174: D0 Mode Clock Enable Register B (D0Cken_B)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 7-11. D0CKEN_A: Clock Enable Mappings for CKEN Bits (Sheet 2 of 2) Name Description Name Description Monahans LV Processor CKEN[5]** MMC3 Clock Enable CKEN[21] UART2 Clock Enable... -
Page 175: D0Cken_B: Clock Enable Mappings For Cken Bits
Table 7-13 ignored. Use caution when programming software to control clocks using this register Note: D0CKEN_B[9] has to be set to “1” before any low power mode and D0CS entry. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 176: Ac '97 Clock Divisor Value Register (Ac97_Div)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 7.3.5.1 Clustering All peripherals typically receive both a unit clock and a bus clock. The unit (or functional) clock is specific to the requirements of each unit, and there could be more than one such clock per unit. The bus clock is common to all the units on that bus. -
Page 177: Coprocessor 14: Clock
• Frequency change sequence (See Section 7.2.2.2) This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 177... -
Page 178: Register Summary
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 7-16. XCLKCFG Bit Definitions Coprocessor 14 BCCU Register CR6 XCLKCFG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 179: Services Power Management Unit
MPMU power states (S0, S2, S3, and S4) and the BPMU power states (D0, D1, D2 and D4). See Section 8.7.2 for a brief descriptions of the BPMU power states. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 180: Differences Between The Pxa300 Processor And Pxa310 Processor
VCC_CI, VCC_LCD, VCC_CARD1, VCC_CARD2, VCC_USB(PXA300 Processor), VCC_ULPI(PXA310 processor), VCC_BIAS(PXA310 processor), VCC_IO1, and VCC_IO3. Differences Between the PXA300 Processor and PXA310 Processor There are no Services Power Management (PMU) differences between the PXA300 processor and the PXA310 processor. Features • Five system reset sources: power-on, hardware, GPIO, watchdog, and S3 low-power state exit •... -
Page 181: Signal Descriptions
PWR_CAP<1:0> Analog the S3 state. The PWR_OUT signal connects to an isolated external capacitor. PWR_OUT Analog Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 181 Not approved by Document Control. For review only. -
Page 182: Hardware Reset (Nreset)
The processor do not recognize any external events while the nRESET signal is asserted. nRESET typically is driven directly by an external power-management integrated circuit (PMIC). Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for information on the nRESET timing requirements. -
Page 183: Ext_Wakeup<1:0
If the core is in a low-power mode, it is woken up and then an interrupt sent to indicate the assertion of nBATT_FAULT. The status of the Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 184: System Power Enable (Sys_En)
(VCC_MVT, VCC_PLL, VCC_BG, VCC_OSC13M, VCC_MEM, VCC_DF, VCC_MSL, VCC_CI, VCC_LCD, VCC_CARD1, VCC_CARD2, VCC_USB(PXA300 Processor), VCC_BIAS(PXA310 processor), VCC_ULPI(PXA310 processor), VCC_IO1, and VCC_IO3.) can be removed. Note: The low-voltage power supplies (VCC_APPS and VCC_SRAM) are controlled via I commands or PWR_EN, and if not disabled prior to SYS_EN being de-asserted, must be disabled by the de-assertion of SYS_EN. -
Page 185: Power Management Supply Output (Pwr_Out)
VCC_BBATT drops below 2.4 V, which is the VCC_BBATT minimum voltage (refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for details), and remains asserted until a positive power-supply assertion is detected on the back-up battery pin VCC_BBATT . -
Page 186: Power-On Reset (Por)
VCC_BBATT. If all power supplies are powered-on and VCC_BBATT is powered off for more than 10 μs, the POR circuitry recognizes it as a power-on reset event (refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for details). Once the VCC_BBATT is powered on, all units are reset to the same known state as hardware reset;... -
Page 187: Hardware Reset
Thermal Specification for nRESET timing specifications. The sequence for hardware reset is: 1. The nRESET pin is asserted for a period of time described in the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification. The MPMU asserts nRESET_OUT and negates SYS_EN. -
Page 188: Gpio Reset
GPIO reset is treated as a wake-up event by the MPMU. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for nGPIO_RESETtiming requirements. In GPIO reset, all units in the processor subsystem are reset to their predefined reset states except... -
Page 189: Not Approved By Document Control. For Review Only
If the MPMU is in S0 state, GPIO reset is invoked when nGPIO_RESET is asserted low for a specified amount of time. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for this time duration. When GPIO reset is invoked, nRESET_OUT is asserted if the GP_ROD bit in the “Power Management Unit General Configuration Register (PCFR)”... -
Page 190: S3 Low-Power State Exit Reset
Note: The delay between the de-assertion of nGPIO_RESET and nRESET_OUT is described in the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification. Normal boot-up sequencing begins, with all units in the processor subsystems starting with their predefined reset... -
Page 191: Watchdog Reset
JCONR, All bits in PMCR except BIE and BIS MPMU PSR, PSPR, PCFR, PWER, PWSR, PECR, and BIE and BIS in PMCR MPMU DCSR Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 191 Not approved by Document Control. -
Page 192: Summary Of Reset Sequences
The MPMU asserts SYS_EN. • The external voltage regulators supply VCC_MVT first, followed by VCC_PLL, VCC_BG, VCC_OSC13M, VCC_MEM, VCC_DF, VCC_MSL, VCC_CI, VCC_LCD, VCC_CARD1, VCC_CARD2, VCC_USB(PXA300 Processor), VCC_BIAS(PXA310 processor), VCC_ULPI(PXA310 processor), VCC_IO1, and VCC_IO3 in any order, and POR MVT, PLL,... -
Page 193: Power Management Operation
The timekeeping oscillator is enabled and used as the clocking source for the MPMU, BPMU, and real-time clock. All subsystem clocks are disabled except for the BPMU clock as stated above. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 194: Power Domains
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual — In S2 state, PWR_EN is negated and PWR_I2C commands are sent to an external PMIC to power off the VCC_APPS external supply. The VCC_SRAM supply is powered off if no data is to be retained in the SRAMs. -
Page 195: Internal Power Domains
1.7–1.9 VCC_MVT VCC_PLL, VCC_BG, VCC_OSC13M, VCC_MEM, VCC_DF, VCC_MSL, VCC_CI, VCC_LCD, VCC_CARD1, VCC_CARD2, PD_PAD I/O pads 2.7–3.6 VCC_USB(PXA300 Processor), VCC_BIAS(PXA310 processor), VCC_ULPI(PXA310 processor), VCC_IO1, and VCC_IO3, PD_BPMU Application subsystem PMU and timer 1.7–1.9 VCC_MVT 0.8–1.49 VCC_APPS (adjustable) PD_BPER Application subsystem peripheral units 0.95–1.49... -
Page 196: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 8-5. External Power Supplies (Sheet 2 of 2) Default Name Associated Power Domain Enable Voltage (V) VCC_MEM PD_PAD SYS_EN VCC_USB (PXA300 PD_PAD SYS_EN Processor) VCC_ULPI (PXA310... -
Page 197: Power Domains Connection
Subsystem Services Unit APPS Dynamic Low volt. DC/DC SRAM Dynamic Low volt. LDO Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 197 Not approved by Document Control. For review only. -
Page 198: Services Unit Power Domains
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 8-4. Services Unit Power Domains T o P a d s U n it P D _ R T C P D _ R E G... -
Page 199: Processor Power Modes
The second sequence in the cascade is the hardware-watchdog reset sequence. This sequence occurs automatically after the start-of-day (SOD) sequence is completed. The MPMU enters the hardware-watchdog reset sequence directly with the assertion of hardware or watchdog reset. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 200: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • The third sequence in the cascade is the S3 low-power state exit reset sequence. This sequence occurs automatically after the hardware-watchdog reset sequence is completed. The MPMU enters the S3 low-power state exit reset sequence directly with the assertion of the S3 low-power state exit reset. -
Page 201: Sod Power-On Master Pmu State Sequence
If PCFR[SWDD] is set to ‘0’, the SYS_DEL counter will wait the entire count value and then proceed, regardless of the detected state of the high voltage supplies. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 202: Steps Taken By Master And Subsystem For Initial Power Up And Exit Of Reset
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 8-7. Steps Taken by Master and Subsystem for Initial Power Up and Exit of Reset VCC_BBATT turned on External power sequence supplies DC-DC enabled External signal... -
Page 203: S0 13-Mhz Clock Enable Sequence
BPMU to request a low-voltage power supply (VCC_APPS or VCC_SRAM). A similar sequence is used to disable the low-voltage supplies. The VCC_SRAM supply is disabled only when it is not needed. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 204: S0 Low Voltage Supply Enable Sequence
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 8-9. S0 Low Voltage Supply Enable Sequence Low-voltage supply requested by Subsystem PMU BPMU Action External Power C Commands to Supply Action enable low-voltage supplies Master PMU... -
Page 205: Not Approved By Document Control. For Review Only
SRAMs are programmed off. If PVCR[PVE] is cleared to 0, no voltage-change sequence commands are sent. If PVCR[PVE] is set to 1, the voltage-change sequence consists of the following which are automatically sent by the PWR_I2C unit: Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 206: Not Approved By Document Control. For Review Only
GPIO wake-up edge and to begin the wake-up sequence. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for these time durations. The assertion of nBATT_FAULT appears to the MPMU as a wake-up event. If nBATT_FAULT is asserted and the PCMR[BIE] bit is set, the MPMU sends an interrupt to the application core after S2 state exit completes. -
Page 207: Not Approved By Document Control. For Review Only
VCC_SRAM output voltage to the last setting prior to entering S2. c. Write to the Voltage Change Control register (VCC1) to select the ADTV1 and SDTV1 registers for the VCC_APPS and VCC_SRAM voltage settings and enable the voltage change. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 208: Not Approved By Document Control. For Review Only
MPMU takes up to a specified amount of time to acknowledge the external wake-up edge and to begin the wake-up sequence. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for these time durations.The MPMU is responsible for completing S3 exit sequence. -
Page 209: Not Approved By Document Control. For Review Only
MPMU transitions the rest of the processor architecture to S3 state. To complete S3 state entry, the MPMU completes the following: 1. The MPMU disables the core and system PLLs. 2. The MPMU disables the processor oscillator. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 210: Not Approved By Document Control. For Review Only
5. The MPMU de-asserts SYS_EN pin. The optimum external system responds to this assertion by disabling the power supplies (VCC_MVT, VCC_PLL, VCC_BG, VCC_OSC13M, VCC_MEM, VCC_DF, VCC_MSL, VCC_CI, VCC_LCD, VCC_CARD1, VCC_CARD2, VCC_USB(PXA300 Processor), VCC_BIAS(PXA310 processor), VCC_ULPI(PXA310 processor), VCC_IO1, and VCC_IO3 ). If any of these supplies is disabled, then VCC_APPS must also be disabled. 8.7.2.4.8... -
Page 211: Not Approved By Document Control. For Review Only
However, the receiving PMU takes up to a specified amount of time to acknowledge the external wake-up edge and to begin the wake-up sequence. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for these time durations. -
Page 212: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 2. The MPMU asserts PWR_EN, and the PWR_I2C sends I C commands to enable the VCC_APPS and VCC_SRAM power supplies. If PVE is set to 0, no voltage-change sequence commands are sent. If PVE is... -
Page 213: Voltage Management
The voltage manager consists of two primary components: • Dedicated I C module (PWR_I • Command sequencer Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 213 Not approved by Document Control. For review only. -
Page 214: Programming Restrictions For The Pwr_I2C
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual The dedicated I C module used by the voltage manager is nearly identical to the I C described in “I C Bus Interface Unit” chapter. The PWR_I C is located within the services unit and is optimized and dedicated for connection to the external voltage regulator only. -
Page 215: Not Approved By Document Control. For Review Only
SOD voltage setting. 3. Write 0x05 to Output Voltage Enable register 1 (OVER1) in the external regulator to enable the VCC_APPS and VCC_SRAM supplies to their programmed voltages. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 216: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Note: The ADTV1, SDTV1, and OVER1 are registers defined in the power-management integrated circuit (PMIC) used to interface to the processor. Note: If no PMIC is included in the system or can not respond to the control registers as specified in... -
Page 217: Not Approved By Document Control. For Review Only
Write to the external regulator VCC_APPS DVM Target Voltage 2 register (ADTV2) to set the VCC_APPS output voltage. b. Write to the external regulator VCC_SRAM DVM Target Voltage 2 register (SDTV2) to set the VCC_SRAM output voltage. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual c. Write to the Voltage Change Control register (VCC1) to select the ADTV2 and SDTV2 registers for the voltage settings and enable the voltage change. Note: The ADTV2, SDTV2, and VCC1 are registers defined in the power-management integrated circuit (PMIC) used to interface to the processor. -
Page 219: Not Approved By Document Control. For Review Only
Voltage Change Control register (OVER1) to select the ADTV1 and SDTV1 registers for the voltage settings and enable the voltage change. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 220: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Note: The ADTV1, SDTV1, and OVER1 are registers defined in the power-management integrated circuit (PMIC) used to interface to the processor. Note: When PVE and FVE bits are set to 1, the PWR_I... -
Page 221: Accessing Pi2C Registers Directly Through S/W
Note: PMER is a reserved system register and must not be witten to or read from outside the scope of the above defined PI2C S/W access. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 222: Register Descriptions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Register Descriptions 8.9.1 Power Management Unit Control Register (PMCR) PMCR, defined in Table 8-6, controls the MPMU interrupt generation and behavior when MPMU-based interrupt conditions occur. A write to the PMCR requires two 32-kHz clock cycles to complete. Wait for two 32-kHz clock cycles between writes to the PMCR or data corruption may occur. -
Page 223: Not Approved By Document Control. For Review Only
1 – Force an interrupt to the application core. This allows software entry into S3 state when nBATT_FAULT is asserted. † S3 low-power state exit reset does not clear this bit. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 224: Power Management Unit Status Register (Psr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 8.9.2 Power Management Unit Status Register (PSR) PSR, defined in Table 8-7, contains the following status flags: • Battery fault status (BFS) is set when the assertion of nBATT_FAULT invokes S3 state.It will also get set on nBATT_FAULT assertion while the system is already in S3 state. -
Page 225: Power Management Unit Scratch-Pad Register (Pspr)
See Table 8-8 for details. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 226: Power Management Unit General Configuration Register (Pcfr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 8-8. PSPR Bit Definitions Physical Address Services Unit 0x40F5_0008 PSPR Power Management Unit User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 †... -
Page 227: Pcfr Bit Definitions
0b1011 = 11 Power Supply Ramp Delay = 11 x (1/32.768 kHz) = ~ 0.336 ms 19:14 — — reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 227 Not approved by Document Control. For review only. -
Page 228: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 8-9. PCFR Bit Definitions (Sheet 2 of 2) Physical Address Services Unit 0x40F5_000C PCFR Power Management Unit User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 229: Power Manager Wake-Up Enable Register (Pwer)
— If a rising edge is to be detected on a signal, the signal must be held low for a minimum time, then high for a minimum time. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for this time duration. -
Page 230: Power Manager Wake-Up Status Register (Pwsr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 8.9.6 Power Manager Wake-Up Status Register (PWSR) PWSR, defined in Table 8-11, indicates which sources (enabled through the PWER) caused a wake up from S2 or S3 states. These bits can be set only by a rising edge, falling edge, or either on the given EXT_WAKEUP pin, depending on the settings in the PWER. -
Page 231: Pecr Bit Definitions
1 – A logic 1 value was read on EXT_WAKEUP<0> when configured as an input. † S3 low-power mode exit reset does not clear or set this bit. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 232: Power Manager Mask Event Register (Pmer)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 8.9.8 Power Manager Mask Event Register (PMER) PMER, defined in Table 8-13, is used to provide software control of the power manager event detection and execution. PMER provides control of the following events: •... -
Page 233: Not Approved By Document Control. For Review Only
This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. S/W workarounds may specifically ask the user to write and/or read certain fixed values to/from this register. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 234: Power Management Unit Voltage Change Control Register (Pvcr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 8-13. PMER Bit Definitions Physical Address Services Unit 0x40F5_0088 PMER Power Management Unit User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 235: Pvcr Bit Definitions
The seven-bit address of the external regulator’s I C module (default is Address 0x34). †† Low power mode exit does not clear or set this bit Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 235... -
Page 236: Register Summary
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 8.10 Register Summary Table 8-15 shows the registers associated with the power management unit and the physical addresses used to access them. Table 8-15. Power Management Unit Register Summary... -
Page 237: Slave Power Management Unit
Figure 9-1 shows the application subsystem power states. Table 9-1 lists each of the power states shown in Figure 9-1. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 237 Not approved by Document Control. For review only. -
Page 238: Application Subsystem Power States
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 9-1. Application Subsystem Power States SRAM Modules SRAM Modules D0 or D2 ( Deep Sleep) All Modulesin ( LCD Refresh ) Core ( Run and Turbo) -
Page 239: Differences Between Pxa300 Processor And Pxa310 Processor
9.1.1 Differences Between PXA300 Processor and PXA310 Processor There are no differences in the BPMU for the PXA300 processor and PXA310 processor. Operation The BPMU controls the operation of power states and reset signals for the units within the application subsystem. -
Page 240: Application Subsystem Reset Distribution
GPIO reset to the BPMU although software executing in application subsystem can initiate a GPIO reset. See Section 3.5.3, “GPIO Reset” for more information. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for timing requirements. 9.2.1.2.1 Behavior During GPIO Reset During GPIO reset, all units are held at their defined reset conditions. -
Page 241: Power Management
DDR SDRAM memories. The actions the BPMU takes depend on the power state of the PXA300 processor or PXA310 processor when the GPIO reset occurs. If the PXA300 processor or PXA310 processor is in a low power state before the GPIO reset occurs, the DDR SDRAM is already in self-refresh mode. -
Page 242: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • D0 state—All internal power domains and external power supplies may be fully powered and functional. In this state, all internal clocks can be running. The core can be in either C0 state or C1 state. In C1 state, the core clock is turned off. -
Page 243: Bpmu Power States
SRAM arrays that are required to be operational during D1 state. • The memory controller must be properly configured to ensure DDR SDRAM contents are maintained during D1 state. See the Memory Controller chapter for more details. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
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SRAM banks when accesses are made to SRAM banks that are in the low-power, state-retaining mode. Refer to the Internal Memory chapter in Vol. II: PXA300 Processor and PXA310 Processor Memory Configuration Developers Manual for details. Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright ©... -
Page 245: Not Approved By Document Control. For Review Only
SRAM banks when accesses are made to SRAM banks that are in the low-power, state-retaining mode. Refer to the Internal Memory chapter in Vol. II: PXA300 Processor and PXA310 Processor Memory Configuration Developers Manual for details. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • nBATT_FAULT asserted while BIE bit is set to 1. If nBATT_FAULT is asserted and the BIE bit is set to 0, the MPMU automatically transitions to S3 (with the application subsystem entering D4) state without providing a wake-up event to the BPMU to exit D1 state. -
Page 247: Not Approved By Document Control. For Review Only
The external and internal memory controllers complete all outstanding transactions in their buffers, and the DDR SDRAM memory controller places the DDR SDRAM in self-refresh mode. • Application subsystem MFPs are set for D2 state operation. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 248: Not Approved By Document Control. For Review Only
D2 state and sent to the BPMU. However, the receiving PMU takes up to a specified amount of time to acknowledge the GPIO wake-up edge and begin the wake-up sequence. Refer to the PXA300 and PXA310 Processor Electrical, Mechanical, and Thermal Specification for this time duration. If the same wake-up event is enabled in “Application Subsystem Wake-Up from D2 to D0 State Enable Register... -
Page 249: Not Approved By Document Control. For Review Only
Assertion of any enabled D2 state wake-up event selected in the “Application Subsystem Wake-Up from D2 to D1 State Enable Register (AD2D1ER)”. The following occurs after the assertion of a D2-to-D1-state wake-up event: Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 249 Not approved by Document Control. -
Page 250: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • If needed, BPMU initiates voltage change sequence for VCC_APPS and VCC_SRAM for D1 state. • The units selected by the D1 state unit operational bits exit a low-power state. -
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In D3 state, the core PLL is turned off. The ring oscillator is disabled. In D3 state, any pre-programmed D3 wake-up event can cause the BPMU power state to change to D0 state. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
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GPIO wake-up edge and begin the wake-up sequence. Refer to the PXA300 and PXA310 Processor Electrical, Mechanical, and Thermal Specification for this time duration. If the application subsystem is in D3 state and nBATT_FAULT is asserted, a wake-up event is generated to the BPMU, followed by an interrupt to the core if the BIE bit is set to 1. -
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D4 state is only possible with an external LCD panel with a built-in frame buffer. The clocks to all peripherals are stopped when D4 state is entered and they will not function normally. • Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
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GPIO wake-up edge and begin the wake-up sequence. Refer to the PXA300 and PXA310 Processor Electrical, Mechanical, and Thermal Specification for these time durations. If the application subsystem is in D4 state and nBATT_FAULT is asserted, the MPMU continues in S3 state (with the application subsystem staying in D4 state) with the result being the complete loss of state information in the application subsystem and the MPMU enable wake-ups being modified to only be . -
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Finally, if the PSPR in the MPMU was used for saving any general processor state during S3 state, the state can be recovered. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 256: Nbatt_Fault Occurrence
Due to synchronization across clock domains and other overhead, there is a finite time interval between the software write to “Core PWRMODE Register (CP14 Register 7)” to initiate a low-power state and the BPMU wake-detection window activation. This time is specified in the PXA300 and PXA310 Processor Electrical, Mechanical, and Thermal Specification. 9.2.5 Other Power Modes In addition to the 4 D-states discussed in this chapter, the “Core PWRMODE Register (CP14 Register 7)”... -
Page 257: Application Subsystem Power Status/Configuration Register (Ascr)
This bit is only ever written to 0 which releases the control; 1 implies that the RDH signal is asserted and this is done via hardware. 30:15 — — reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 257... -
Page 258: Application Subsystem Reset Status Register (Arsr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-3. ASCR Bit Definitions (Sheet 2 of 2) Physical Address Slave Power Management Unit 40F4_0000 ASCR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 259: Application Subsystem Wake-Up From D3 Enable Register (Ad3Er)
Chapter 4, “Pin Descriptions and Control” in Vol. I: System and Timer Configuration Developers Manual. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 260: Ad3Er Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-5. AD3ER Bit Definitions (Sheet 1 of 2) Physical Address Slave Power Management Unit 40F4_0008 AD3ER User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 261: Application Subsystem Wake-Up From D3 Status Register (Ad3Sr)
These bits are cleared by writing 0b1 to them. Writing 0b0 to any status bit has no effect. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 262: Ad3Sr Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-6. AD3SR Bit Definitions (Sheet 1 of 2) Physical Address Slave Power Management Unit 40F4_000C AD3SR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WS_GENERIC <13:0>... -
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WS_EXTERN clear 0 = No wake-up occurred due to external event[n] edge detect. 1 = Wake-up occurred due to external event[n] edge detect. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 263 Not approved by Document Control. -
Page 264: Application Subsystem Wake-Up From D2 To D0 State Enable Register (Ad2D0Er)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 9.3.5 Application Subsystem Wake-Up from D2 to D0 State Enable Register (AD2D0ER) AD2D0ER, defined in Table 9-7, selects whether or not the corresponding wake-up sources cause an application subsystem wake up from D2 to D0 state. -
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Wake-up options for USBOTG port from D2 to D0 state WEOTG 0 = Disable wake-up due to USBOTG port. 1 = Enable wake-up due to USBOTG port. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 266: Application Subsystem Wake-Up From D2 To D0 Status Register (Ad2D0Sr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-7. AD2D0ER Bit Definitions (Sheet 3 of 3) Physical Address Slave Power Management Unit 40F4_0010 AD2D0ER User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WE_GENERIC <13:0>... -
Page 267: Ad2D0Sr Bit Definitions
WSDMUX3 clear 0 = No wake-up occurred due to EDMUX3 port 1 = Wake-up occurred due to EDMUX3 port. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 267 Not approved by Document Control. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-8. AD2D0SR Bit Definitions (Sheet 2 of 2) Physical Address Slave Power Management Unit 40F4_0014 AD2D0SR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WS_GENERIC <13:0>... -
Page 269: Application Subsystem Wake-Up From D2 To D1 State Enable Register (Ad2D1Er)
D1 state. These bits are cleared by writing 0b1 to them. Writing 0b0 to any status bit has no effect. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 270: Application Subsystem Wake-Up From D1 To D0 State Enable Register (Ad1D0Er)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-10. AD2D1SR Bit Definitions Physical Address Slave Power Management Unit 40F4_001C AD2D1SR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 271: Ad1D0Er Bit Definitions
WEDMUX3 0 = Disable wake-up due to EDMUX3 port 1 = Enable wake-up due to EDMUX3 port. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 271 Not approved by Document Control. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-11. AD1D0ER Bit Definitions (Sheet 2 of 3) Physical Address Slave Power Management Unit 40F4_0020 AD1D0ER User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WE_GENERIC <13:0>... -
Page 273: Application Subsystem Wake-Up From D1 To D0 Status Register (Ad1D0Sr)
D0 state. These bits are cleared by writing 0b1 to them. Writing 0b0 to any status bit has no effect. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 274: Ad1D0Sr Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-12. AD1D0SR Bit Definitions (Sheet 1 of 3) Physical Address Slave Power Management Unit 40F4_0024 AD1D0SR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WS_GENERIC <13:0>... -
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15:2 clear 0 = No wake-up occurred due to generic event[n] edge detect. 1 = Wake-up occurred due to generic event[n] edge detect. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 275 Not approved by Document Control. -
Page 276: Application Subsystem D3 Configuration Register (Ad3R)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-12. AD1D0SR Bit Definitions (Sheet 3 of 3) Physical Address Slave Power Management Unit 40F4_0024 AD1D0SR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WS_GENERIC <13:0>... -
Page 277: Application Subsystem D2 Configuration Register (Ad2R)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved Reset ? Bits Access Name Description 31:2 — — reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 277 Not approved by Document Control. For review only. -
Page 278: Application Subsystem D1 Configuration Register (Ad1R)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-14. AD2R Bit Definitions (Sheet 2 of 2) Physical Address Slave Power Management Unit 40F4_0034 AD2R User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 279: Application Subsystem General Purpose Register (Agenp)
This bit is cleared once the RO is turned off/on. This bit indicates the status of the RO. RO_ST 0 = RO is turned off 1 = RO is turned on.. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 279 Not approved by Document Control. -
Page 280: Core Pwrmode Register (Cp14 Register 7)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-16. AGENP Bit Definitions (Sheet 2 of 2) Physical Address Slave Power Management Unit 40F4_002C AGENP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 281: Register Summary
AD2D1ER Application Subsystem D2 to D1 State Wake-Up Enable register 0x40F4_001C AD2D1SR Application Subsystem D2 to D1 State Wake-Up Status register Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 281... -
Page 282: Processor Power Management Unit Register Summary - Coprocessor Address
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 9-18. Processor Power Management Unit Register Summary - Physical Addresses (Sheet 2 of 2) Address Name Description Page 0x40F4_0020 AD1D0ER Application Subsystem D1 to D0 State Wake-Up Enable register... -
Page 283: 1-Wire Bus Master Interface
1-Wire Bus Master Interface 1-Wire Bus Master Interface This chapter describes how the PXA300 processor or PXA310 processor works with the 1-Wire* bus master interface controller and the related processor-supported registers. 10.1 Overview The 1-Wire bus master interface controller is designed to receive and transmit 1-Wire bus data and provides complete control of the 1-Wire bus through eight-bit commands. -
Page 284: Signal Descriptions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 10.2 Signal Descriptions Table 10-1 describes the functionality of the 1-Wire signal. Table 10-1. 1-Wire Signal Descriptions Name Direction Description 1-Wire Data Line This open-drain line is the 1-Wire bidirectional data bus signal. 1-Wire... -
Page 285: I/O Signaling
See the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for detailed timing information. The 1-Wire bus master controller transmits a reset pulse. The 1-Wire bus line is then pulled high by the external pullup resistor. -
Page 286: Wire Write Slots
The master ends the read slot after the required amount of time (see Figure 10-4). Refer the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for detailed timing information. Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright ©... -
Page 287: Register Descriptions
1-Wire Command register contains two bits to bypass the 1-Wire bus master interface controller features and control the 1-Wire bus directly. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 288: W1Cmdr Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 10-2. W1CMDR Bit Definitions Physical Address W1CMDR 1-Wire Interface 0x41B0_0000 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 289: 1-Wire Transmit/Receive Buffer (W1Trr)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved Reset ? Bits Access Name Description 31:5 — Reserved Reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 289 Not approved by Document Control. For review only. -
Page 290: 1-Wire Interrupt Enable Register (W1Ier)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 10-4. W1INTR Bit Definitions (Sheet 2 of 2) Physical Address W1INTR 1-Wire Interface 0x41B0_0008 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 291: 1-Wire Clock Divisor Register (W1Cdr)
1 = If the enable presence detect flag is set, an interrupt is generated whenever a 1-Wire reset is sent and the required amount of time has passed for a presence detect pulse to have occurred. Refer to the PXA300 Processor and PXA310 Processor Electrical, Mechanical, and Thermal Specification for timing information. 10.4.5 1-Wire Clock Divisor Register (W1CDR) This register divides the internal reference clock to generate the 1-Wire clock.This register must be programmed... -
Page 292: Register Summary
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 10-6. W1CDR Bit Definitions Physical Address W1CDR 1-Wire Interface 0x41B0_0010 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 293: Dma Controller
DMA Controller DMA Controller This chapter describes the PXA300 processor or PXA310 processor on-board DMA controller (DMAC). 11.1 Overview The processor contains a direct-memory access controller (DMAC) that transfers data to and from memory in response to requests generated by peripheral devices or companion chips. The peripheral devices and companion chips do not directly supply addresses and commands to the memory controller. -
Page 294: Operation
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • Supports flow-control bits to process requests from peripheral devices. Requests are not processed unless the flow-control bit is set. Table 11-1. DMA Support Matrix Internal External... -
Page 295: Dma Channels
Higher than 3. Lower than 0 and 1. 1 / 8 12, 13, 14, 15, 28, 29, 30, 31 Lowest 1 / 8 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 295 Not approved by Document Control. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 11.3.1.2 Channel States The following states apply to the DMA channels: • Uninitialized — occurs after a reset. DCSRx[STOPINTR] is set when uninitialized. • Not running — occurs when either a valid descriptor has been loaded into the DDADRx register during a descriptor-fetch transfer or valid DSADRx, DTADRx, and DCMDx registers have been programmed during a no-descriptor-fetch transfer, but the corresponding run bit, DCSRx[RUN], is not set. -
Page 297: Dma Descriptors
Word [0] contains a value for the DDADRx register and a single flag bit (STOP). • Word [1] contains a value for the DSADRx register. • Word [2] contains a value for the DTADRx register. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 297 Not approved by Document Control. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • Word [3] contains a value for the DCMDx register. The DMAC can be operated in two distinct modes based on the DCSRx[NODESCFETCH] bit: • DCSRx[NODESCFETCH] = 0 - Descriptor-fetch transfer •... -
Page 299: Descriptor-Fetch Transfer Channel State Diagram
DDADRx register + 32 bytes). If either of the bits is cleared, DMAC fetches the next descriptor from the address in the DDADRx register. DDADRx[BREN] is relevant only for descriptor-fetch transfers (DCSRx[NODESCFETCH] is cleared). Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 300: Flow Chart For Descriptor Branching
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 11-4. Flow Chart for Descriptor Branching End of current Descriptor DDADRx[BREN]=1& Next descriptor = DCSRx[CM PST]=1 DDADRx + 32 bytes DDADRx[STO P]=1 Stop descriptor, Trigger interrupt, if enabled Next descriptor = DDADRx 11.3.2.2... -
Page 301: No-Descriptor-Fetch Transfer Channel State Diagram
≠ DCMDx[LEN] 0 & DCMDx[FLOWSRC] = 0 & DCMDx[LEN] DCMDx[FLOWTRG] = 0 Stopped Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 301 Not approved by Document Control. For review only. -
Page 302: Transferring Data
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 11.3.3 Transferring Data The on-chip peripherals connected to the DMA via the peripheral bus operate as flowthrough transfers (For details, refer to Section 11.3.3.1.1). Although the source or destination of a DMA transfer is usually a peripheral intended to be used as a source or sink of DMA data, the DMAC can transfer data to or from any memory location through memory-to-memory moves. -
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DSADRx[SRCADDR]= memory address DTADRx[TRGADDR]= memory address DCMDx[INCSRCADDR] = 1 DCMDx[INCTRGADDR] = 1 DCMDx[FLOWSRC] = 0 DCMDx[FLOWTRG] = 0 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 303 Not approved by Document Control. For review only. -
Page 304: Programming Tips
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 11.3.4 Programming Tips This section provides information concerning software requirements, instruction ordering, and misaligned memory accesses. 11.3.4.1 Software Management Requirements The information that must be maintained on a per-stream basis (for example, the memory address, the peripheral address, the transfer count, and the implied direction of data flow) is maintained in descriptor registers in the DMAC. -
Page 305: How Dma Handles Trailing Bytes
On-chip-peripheral-to-memory transfers: Special handshaking signals and interrupts are employed for transferring trailing bytes from an on-chip peripheral to memory. The conditions that use the handshaking signals and interrupts are explained below: Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual — End of Packet (EOP) — the peripheral receives its last data sample from an external CODEC and detects an EOP based on its receive protocol. Any remaining data samples in the peripheral receive FIFO are treated as trailing bytes. -
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• UART1, UART2, UART3 • SSP1, SSP2, SSP3, SSP4 • USB device controller (UDC) Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 307 Not approved by Document Control. For review only. -
Page 308: Quick Reference To Dma Programming
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • Mobile Scalable Link (MSL) • USIM • MMC1 and SDIO1 • MMC2 and SDIO2 11.3.6 Quick Reference to DMA Programming Table 11-4, Table 11-5, Table 11-6, and... -
Page 309: Configuration For Memory-To-Memory Data Transfers
48 bytes of data from memory to the system bus peripheral in bursts of 32 bytes, the DMAC increments the target address by 32 after the first burst and then by 16 after the second burst. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 310: Configuration For Companion Chip (Cc) Related Data Transfers
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-7. Configuration for Companion Chip (CC) Related Data Transfers DCMD DCMD Source Target DCMD [INCSR- [INCTR- Source Target Alignment Alignment [WIDTH] CADDR] GADDR] (bytes) (bytes) (binary) -
Page 311: Not Approved By Document Control. For Review Only
1 or 4 01 or 11 32 or trailing Target 0x4000_1178 0x4200_0144 (width=4 bytes) Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 311 Not approved by Document Control. For review only. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-8. DMA Quick Reference for On-Chip Peripherals (Sheet 3 of 5) DCMDx Width Burst Size Source or Unit Function FIFO Address Width DRCMRx (bytes) (bytes) Target... -
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Transmit 0x4190_0010 01, 10, or 11 8, 16, 32 or trailing Target 0x4000_110C Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 313 Not approved by Document Control. For review only. -
Page 314: Examples
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-8. DMA Quick Reference for On-Chip Peripherals (Sheet 5 of 5) DCMDx Width Burst Size Source or Unit Function FIFO Address Width DRCMRx (bytes) (bytes) Target... -
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(dynamically modified) descriptor and uses the devices I_DATA_OFFS address to process the requested transfer. When the data transfer is complete, the DMAC steps back to the first descriptor and the process repeats. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Example 11-3. Adding a Descriptor to End-of-Descriptor List (Channel Running) Note: The following example assumes that a descriptor-fetch transfer is active. DMA descriptor lists are used as queues of full buffers for network transmitters and as queues of empty buffers for network receivers. -
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//FullEmpty table updating descriptor desc[3].ddadr = &desc[4]; desc[3].dsadr = FEUPDT; desc[3].dtadr = FETBL0; desc[3].dcmd = Len=4 bytes; Second Descriptor Set Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 317 Not approved by Document Control. For review only. -
Page 318: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual First Descriptor //Compare and Branch Descriptor modes enabled. //No data transferred by this descriptor. //Source is indirectly addressed and target is directly addressed //On a successful compare of &FETBL1 with 0x0000, // Descriptor chain branches to desc[5] + 4*32bits, i.e desc[6]. -
Page 319: Register Descriptions
This bit can also be used to mask the request. 0 = Request is unmapped 1 = Request is mapped to a valid channel indicated by DRCMRx[4:0] — Reserved Reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 319... -
Page 320: Dma Descriptor Address Registers (Ddadrx)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-9. DRCMR0–63, DRCMR64–99 Bit Definitions (Sheet 2 of 2) Physical Address 0x4000_0100–0x4000_01FC DRCMR0–DRCMR63 DMA Controller 0x4000_1100–0x4000_118C DRCMR64–DRCMR99 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 321: Dma Source Address Register (Dsadrx)
Other restrictions on byte boundary alignment can apply for special DMA operations (see Section 11.3.4.4). These are read/write registers. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 322: Dma Target Address Registers (Dtadrx)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-11. DSADR0–31 Bit Definitions Physical Address DSADR0–DSADR31 DMA Controller 0x4000_02x4–0x4000_03x4 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 323: Dma Command Registers (Dcmdx)
(Table 11-13) are for descriptor-fetch transfers and read/write for no-descriptor-fetch transfers. These are read/write registers. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 323 Not approved by Document Control. -
Page 324: Dcmd0–31 Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-13. DCMD0–31 Bit Definitions (Sheet 1 of 4) Physical Address DCMD0–DCMD31 DMA Controller 0x4000_02xC–0x4000_03xC User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
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0 = Interrupt not triggered after descriptor is loaded 1 = Set interrupt bit for that channel in the DINT[CHLINTR] when the descriptor (4 words) for the channel is loaded Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-13. DCMD0–31 Bit Definitions (Sheet 3 of 4) Physical Address DCMD0–DCMD31 DMA Controller 0x4000_02xC–0x4000_03xC User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 327: Dreq Status Register (Drqsr0)
For a write to an external peripheral, the DMAC decreases the counter after it completes the write. • For a read from an external peripheral, the DMAC decreases the counter after it sends the corresponding read request to the memory controller. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 328: Dma Channel Control/Status Registers (Dcsrx)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual The external companion chip must not have more than 31 pending requests at a given time. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. -
Page 329: Dcsr0–31 Bit Definitions
DDADRx register, when the byte count for the current transfer reaches zero. 0 = Descriptor-fetch transfer 1 = No-descriptor-fetch transfer Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 329 Not approved by Document Control. -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-15. DCSR0–31 Bit Definitions (Sheet 2 of 6) Physical Address 0x4000_0000 DCSR0–DCSR31 DMA Controller –0x4000_007C User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
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1 = Set interrupt bit for that channel in the DINT[CHLINTR] when a peripheral asserts a DMA request after the channel has stopped. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
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PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-15. DCSR0–31 Bit Definitions (Sheet 4 of 6) Physical Address 0x4000_0000 DCSR0–DCSR31 DMA Controller –0x4000_007C User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 333: Not Approved By Document Control. For Review Only
RASINTR 1 = Interrupt caused due to a request made by the peripheral after the respective channel stopped This bit is reset by writing a ‘1’ Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 333 Not approved by Document Control. -
Page 334: Descriptor Behavior On End-Of-Receive (Eor)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-15. DCSR0–31 Bit Definitions (Sheet 6 of 6) Physical Address 0x4000_0000 DCSR0–DCSR31 DMA Controller –0x4000_007C User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 335: Not Approved By Document Control. For Review Only
Interrupt triggered if DCSRx[StopIrqEn] = 1 Note: Fetching the NextDescriptor can be different if branching mode is enabled. Refer to the DDADRx[BREN] description for further details. A9379-01 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 335 Not approved by Document Control. -
Page 336: Dma Interrupt Register (Dint)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 11.4.8 DMA Interrupt Register (DINT) Read-only register DINT (Table 11-16) logs the interrupt information for each channel. An interrupt is generated if any of the following conditions occurs: •... -
Page 337: Dma Programmed I/O Control Status Register (Dpcsr)
A read transaction on the system bus is completed only after the DMA bridge receives the data from across the peripheral bus. There are no split responses, split completions, or retries in this mode. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 338: Dma Register Summary
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Note (1):If software requires that a write complete on the peripheral bus before continuing, then software must write the address, then immediately read the same address, which will guarantee that the address has been updated before allowing the core to continue execution. -
Page 339: Dma Controller Registers
0x4000_00A4 DPCSR DMA Programmed IO control status register 0x4000_00E0 DRQSR0 DMA DREQ Status register Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 339 Not approved by Document Control. For review only. -
Page 340: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-19. DMA Controller Registers (Sheet 2 of 7) Address Name Description Page 0x4000_00E4 — Reserved — 0x4000_00E8 — Reserved — 0x4000_00F0 DINT DMA Interrupt register Request to Channel Map register for DREQ... -
Page 341: Not Approved By Document Control. For Review Only
0x4000_0208 DTADR0 DMA Target Address register channel 0 0x4000_020C DCMD0 DMA Command Address register channel 0 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 341 Not approved by Document Control. For review only. -
Page 342: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-19. DMA Controller Registers (Sheet 4 of 7) Address Name Description Page 0x4000_0210 DDADR1 DMA Descriptor Address register channel 1 0x4000_0214 DSADR1 DMA Source Address register channel 1... -
Page 343: Not Approved By Document Control. For Review Only
0x4000_0328 DTADR18 DMA Target Address register channel 18 0x4000_032C DCMD18 DMA Command Address register channel 18 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 343 Not approved by Document Control. For review only. -
Page 344: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 11-19. DMA Controller Registers (Sheet 6 of 7) Address Name Description Page 0x4000_0330 DDADR19 DMA Descriptor Address register channel 19 0x4000_0334 DSADR19 DMA Source Address register channel 19... -
Page 345: Not Approved By Document Control. For Review Only
Request to Channel Map register for NAND interface command transmit 0x4000_118C DRCMR99 — request Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 345 Not approved by Document Control. For review only. -
Page 346: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 12/13/06 Marvell Page 346 Document Classification: Proprietary Information December 13, 2006 Not approved by Document Control. For review only. -
Page 347: Interrupt Controller
Interrupt Controller Interrupt Controller This chapter describes the PXA300 processor or PXA310 processor interrupt controller, explains its modes of operation, and defines the registers associated with it. The interrupt controller controls the interrupt sources available to the processor and contains the location of the interrupt source to allow software to determine the first-level source of all interrupts. -
Page 348: Signal Descriptions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 12.3 Signal Descriptions No external I/O signals are associated with the interrupt controller. 12.4 Operation The Interrupt Controller Pending register (ICPR) has a bit for each of the peripherals (primary interrupt sources). -
Page 349: Accessing Interrupt Controller Registers
Table 12-1 shows the Interrupt Controller registers and the coprocessor register numbers that correspond to them. The registers are mapped to the register space of Coprocessor 6. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am,... -
Page 350: Enabling Coprocessor Access
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual † Table 12-1. Interrupt Controller Register Mapping Coprocessor 6 Register Access Name Description Number Mode ICIP Interrupt Controller IRQ Pending register ICMR Interrupt Controller Mask register ICLR... -
Page 351: Bit Positions And Peripheral Ids
Consumer Infrared Consumer Infrared IP[33] Quick Capture Interface Quick Capture Interface Interrupt IP[32] Not used Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information Page 351 Preliminary Not approved by Document Control. For review only. -
Page 352: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-2. Summary of Bit Positions for Primary Sources (Sheet 2 of 2) Peripher Source Module Bit Field Description Position al ID RTC equals alarm register (from the Services RTC IP[31] controller RTSR). -
Page 353: Register Descriptions
1 = DMA Channel service request has occurred. SSP 1 SSP1 0 = SSP 1 has NOT requested service. 1 = SSP 1 has requested service. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information... -
Page 354: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-3. ICPR Bit Definitions (Sheet 2 of 4) Physical Address: 0x40D0_0010 ICPR Interrupt Controller Coprocessor Register: CP6, CR4 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 355: Not Approved By Document Control. For Review Only
USB Host 2 USBH2 0 = USB Host interrupt 2 has NOT occurred. 1 = USB Host interrupt 2 has occurred. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information... -
Page 356: Icpr2 Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-3. ICPR Bit Definitions (Sheet 4 of 4) Physical Address: 0x40D0_0010 ICPR Interrupt Controller Coprocessor Register: CP6, CR4 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 357: Not Approved By Document Control. For Review Only
0 = The Intel® Quick-Capture Interface Controller has NOT requested service. 1 = The Intel® Quick-Capture Interface Controller has requested service. — — reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information Page 357 Preliminary... -
Page 358: Interrupt Controller Irq Pending Registers (Icip And Icip2)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Several units have more than one source per interrupt signal. When one of these units signals an interrupt, the interrupt-service routine identifies the interrupt through the registers (ICPR and ICPR2) or by reading the ICHP that contains the peripheral ID with the interrupt that has highest active, unmasked priority. -
Page 359: Not Approved By Document Control. For Review Only
UART3 1 = A transmit or receive error has occurred in UART3, interrupt level<20> = 0, and either mask bit<20> = 1 or DIM bit = 0. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am,... -
Page 360: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-5. ICIP Bit Definitions (Sheet 3 of 5) Physical Address: 0x40D0_0000 ICIP Interrupt Controller Coprocessor Register: CP6, CR0 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 361: Not Approved By Document Control. For Review Only
USBH2 1 = USB host interrupt 2 interrupt has occurred, interrupt level<2> = 0, and either mask bit<2> = 1 or DIM bit = 0. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am,... -
Page 362: Icip2 Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-5. ICIP Bit Definitions (Sheet 5 of 5) Physical Address: 0x40D0_0000 ICIP Interrupt Controller Coprocessor Register: CP6, CR0 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 363: Not Approved By Document Control. For Review Only
1 = interrupt occurs and ((mask bit(0) = 0b1) OR (DIM bit = 0b0)) and (interrupt level (38) = 0b0) — — reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information... -
Page 364: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-6. ICIP2 Bit Definitions (Sheet 3 of 3) Physical Address 0x40D0_009C ICIP2 Interrupt Controller Coprocessor Register: CP6, CR6 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 365: Interrupt Controller Fiq Pending Registers (Icfp And Icfp2)
0 = No interrupt notification DMAC 1 = DMA Channel service request has occurred, interrupt level<25> = 1, and either mask bit<25> = 1 or DIM bit = 0. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am,... -
Page 366: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-7. ICFP Bit Definitions (Sheet 2 of 4) Physical Address 0x40D0_000C ICFP Interrupt Controller Coprocessor Register: CP6, CR3 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 367: Not Approved By Document Control. For Review Only
0 = No interrupt notification GPIO_0 1 = GPIO<0> detected an edge, interrupt level<8> = 1, and either mask bit<8> = 1 or DIM bit = 0. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am,... -
Page 368: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-7. ICFP Bit Definitions (Sheet 4 of 4) Physical Address 0x40D0_000C ICFP Interrupt Controller Coprocessor Register: CP6, CR3 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 369: Icfp2 Bit Definitions
1 = interrupt occurs and ((mask bit(0) = 0b1) OR (DIM bit = 0b0)) and (interrupt level (41) = 0b1) — — reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information... -
Page 370: Interrupt Controller Mask Registers (Icmr And Icmr2)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-8. ICFP2 Bit Definitions (Sheet 2 of 2) Physical Address 0x40D0_00A8 ICFP2 Interrupt Controller Coprocessor Register: CP6, CR9 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 371: Icmr Bit Definitions
1 = MultiMediaCard interrupt is not to be masked. UART1 UART1 0 = Masked. 1 = UART1 interrupt is not to be masked. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information... -
Page 372: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-9. ICMR Bit Definitions (Sheet 2 of 3) Physical Address 0x40D0_0004 ICMR Interrupt Controller Coprocessor Register: CP6, CR1 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 373: Not Approved By Document Control. For Review Only
1 = MSL interrupt is not to be masked. SSP 3 SSP3 0 = Masked. 1 = SSP 3 service request interrupt is not to be masked. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information... -
Page 374: Icmr2 Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-10. ICMR2 Bit Definitions (Sheet 1 of 2) Physical Address 0x40D0_00A0 ICMR2 Interrupt Controller Coprocessor Register: CP6, CR7 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 375: Interrupt Controller Level Registers (Iclr And Iclr2)
ICLR and the ICLR2. The ICLR and the ICLR2 registers are initialized to all zeros at reset and software must configure them to reflect the correct value for normal operation. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 376: Iclr Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-11. ICLR Bit Definitions (Sheet 1 of 3) Physical Address 0x40D0 0008 ICLR Interrupt Controller Coprocessor Register: CP6, CR2 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 377: Not Approved By Document Control. For Review Only
1 = PML interrupt creates an FIQ. USB Client USBC 0 = USB client interrupt creates an IRQ. 1 = USB client interrupt creates an FIQ. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information... -
Page 378: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-11. ICLR Bit Definitions (Sheet 3 of 3) Physical Address 0x40D0 0008 ICLR Interrupt Controller Coprocessor Register: CP6, CR2 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 379: Iclr2 Bit Definitions
1 = Service request interrupt creates a FIQ. — — reserved — — reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information Page 379 Preliminary Not approved by Document Control. For review only. -
Page 380: Interrupt Controller Control Register (Iccr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-12. ICLR2 Bit Definitions (Sheet 2 of 2) Physical Address 0x40D0 00A4 ICLR2 Interrupt Controller Coprocessor Register: CP6, CR8 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17... -
Page 381: Interrupt Priority Registers 0 To 52
Where multiple-priority values are assigned to one peripheral, the hardware uses the highest priority value only and ignores the others. Table 12-14 shows the format for IPR registers. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am,... -
Page 382: Interrupt Control Highest Priority Register (Ichp)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual This is a read/write register. Ignore reads from reserved bits. Reserved bits must be written with zeros. Table 12-14. IPR0/52 Bit Definitions Physical Addresses 0x40D0_001C-0098 (IPR 0–31) IPR0–IPR5x... -
Page 383: Register Summary
Interrupt Controller Mask register 0x40D0_0008 ICLR Interrupt Controller Level register 0x40D0_000C ICFP Interrupt Controller FIQ Pending register Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 10:46 am, Document Classification: Proprietary Information Page 383 Preliminary Not approved by Document Control. For review only. -
Page 384: Interrupt Controller Register Summary - Coprocessor Addresses
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 12-16. Interrupt Controller Register Summary - Physical Addresses (Sheet 2 of 2) Physical Address Name Description Page 0x40D0_0010 ICPR Interrupt Controller Pending register 0x40D0_0014 ICCR Interrupt Controller Control register... -
Page 385: Real-Time Clock (Rtc)
13.1 Overview This chapter describes the PXA300 processor or PXA310 processor real-time clock (RTC) controller. The RTC is a general-purpose, real-time reference for use by the system. The timer, wristwatch, stopwatch, periodic interrupt, and the trimmer modules provide the basic functionality of the RTC controller. -
Page 386: Signal Description
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • Trimmer feature (See Section 13.5.5) — User-programmable Trimmer register to generate a precise 1-Hz clock for the timer and wristwatch modules 13.4 Signal Description Table 13-1 describes the signal associated with the RTC controller. -
Page 387: Rtc Block Diagram
Figure 13-2 shows the operational flow of one of these four identical modules of the RTC controller. All RTC modules are described in detail in subsequent sections. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 388: Operational Flow Of The Rtc Modules
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 13-2. Operational Flow of the RTC Modules Is the counter register value equal to the alarm register value? (Compared at the rising edge of the corresponding clock signal) -
Page 389: Timer Module
13.5.2 Wristwatch Module The wristwatch module of the RTC controller consists of its two sub-modules, counters and alarms, as shown in Figure 13-3. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 389 Not approved by Document Control. -
Page 390: Block Diagram Of Wristwatch Module
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Figure 13-3. Block Diagram of Wristwatch Module Wristwatch Controller Alarms Counters RDCR RYCR Alarm 1 Alarm 2 RYAR1 RYAR2 RDAR1 RDAR2 RDCR = RTC Day Counter Register... -
Page 391: Valid And Invalid Data For The Wristwatch Register Fields
Refer to Table 13-4 (DOM) Month 1 to 12 0,13,14,15 Year 0 to 4095 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 391 Not approved by Document Control. For review only. -
Page 392: Valid Data For Day Of Month (Dom) Field In Rycr
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Note: The Day-of-Month (DOM) field is a special case. Depending on the month and the type of year, the validity of the data in this field varies. -
Page 393: Not Approved By Document Control. For Review Only
If zero is written into any of these fields, it is ignored while generating the alarm. For example, if a zero is written into a DOW field, the alarm is set every day at the time that is written in the Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 394: Stopwatch Module
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Hours, Minutes, and Seconds field. If zeroes are written into all the fields of the alarm register, the alarm occurs at 0:00:00 hours every day. If the same data is written (as given in the previous item) in all fields except for the Month field, where a zero was entered, the hardware sets the alarm every month. -
Page 395: Periodic Interrupt Module
Periodic Interrupt Alarm register. The general use of this alarm is to generate interrupts and wakeups to the PXA300 processor or PXA310 processor in all low-power modes, including S0/D1/C2, S0D2/C2, S2/D3/C4 and S3/D4/C4. Therefore, a valid value (non-zero) must be written into PIAR. -
Page 396: Trimmer Module
1-Hz clock period. The PXA300 processor or PXA310 processor, through the RTTR, allows the 1-Hz timebase to be trimmed to an accuracy of +/- 5 seconds per month through the use of the RTC controller’s trimming mechanism. The trimming procedure... -
Page 397: Not Approved By Document Control. For Review Only
This trim setting leaves an error of 0.16 cycles per 1023 seconds. Equation 13-2.describes the error calculation, which yields results in parts-per-million (ppm). Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 397 Not approved by Document Control. -
Page 398: Register Descriptions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Equation 13-2. Error Calculation for Measured Value With a Fractional Component 0.16 cycles 1 sec 4773 Error -------------------------- - ------------------------------ - 1023 sec 32768 cycles 13.5.5.2.3 Maximum Error Calculation Versus Real-Time Clock Accuracy As seen from the trim results, the maximum possible error approaches 1 clock per 2 -1 seconds. -
Page 399: Rtc Trim Register (Rttr)
Core Developer’s Manual for more information about the MMU. Because of the asynchronous nature of the 1-Hz clock relative to the PXA300 processor or PXA310 processor clock, writes to these registers are controlled by a hardware mechanism that delays the actual write until the data can be synchronized properly. -
Page 400: Rtc Status Register (Rtsr)
The alarm-detect bits are reset by writing 0b1 to the bit(s) to be cleared. When the PXA300 processor or PXA310 processor is in a low-power mode, the alarm-detect bit in the RTSR is updated if an RTC alarm is detected and the corresponding alarm-enable bit in the RTSR is set. -
Page 401: Not Approved By Document Control. For Review Only
Wristwatch Alarm Enable for wristwatch alarm 1 : RDALE1 0 – Wristwatch alarm 1 is not enabled. 1 – Wristwatch alarm 1 is enabled. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 401 Not approved by Document Control. -
Page 402: Rtc Alarm Register (Rtar)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 13-6. RTSR Bit Definitions (Sheet 3 of 3) Physical Address RTC Controller 0x4090_0008 RTSR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 403: Wristwatch Day Alarm Registers (Rdarx)
Match value for day of week 16:12 HOURS Match value for hours 11:6 MINUTES Match value for minutes Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 403 Not approved by Document Control. For review only. -
Page 404: Wristwatch Year Alarm Registers (Ryarx)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 13-8. RDARx Bit Definitions (Sheet 2 of 2) Physical Address 0x4090_0018 RDAR1 RTC Controller 0x4090_0020 RDAR2 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 405: Stopwatch Alarm Registers (Swarx)
Note: Zero is a non-valid value for the PIAR and yields unpredictable results. The maximum value that can be written is 65535. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 406: Rtc Counter Register (Rcnr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 13-11. PIAR Bit Definitions Physical Address RTC Controller 0x4090_0038 PIAR User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 407: Rtc Year Counter Register (Rycr)
Day of month — starting with 1. Zero is not allowed. The maximum count varies, based on the month and the type of year. Table 13-4 lists the allowable values. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 408: Stopwatch Counter Register (Swcr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 13.6.11 Stopwatch Counter Register (SWCR) SWCR, defined in Table 13-15, contains the elapsed time of the stopwatch in hours, minutes, seconds, and hundredths of a second. SWCR increments only when the count-enable bit (RTSR[SWCE]) is set. While RTSR[SWCE] is set, the counter continuously counts. -
Page 409: Register Summary
Stopwatch Alarm register 2 0x4090_0034 RTCPICR Periodic Interrupt Counter register 0x4090_0038 PIAR Periodic Interrupt Alarm register Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 409 Not approved by Document Control. For review only. -
Page 410: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 12/13/06 Marvell Page 410 Document Classification: Proprietary Information December 13, 2006 Not approved by Document Control. For review only. -
Page 411: Operating System Timers
The operating-system timers block provides a set of timer channels that allow software to generate timed interrupts (or wake-up events). In the PXA300 processor or PXA310 processor, these interrupts are generated by two sets of timer channels. The first set, which provides one counter and four Match registers, is clocked from a 3.25-MHz clock. -
Page 412: Signal Descriptions
OSCRx is the same as the value in OSMRx. A match triggers an interrupt if the corresponding bit is set in the OIER register shown in Table 14-7. This module is compatible with the Marvell PXA27x processor and partially compatible with the Marvell PXA25x processor, as described in Section 14.4.3. -
Page 413: Compares And Matches
For these channels, when OMCRx[C] is set, a write to the corresponding OSCRx register starts the channel. For channel 4 and channel 8 only, counter operation is as if OMCRx[C] is always set. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 414: Marvell Pxa25X Processor Compatibility
Marvell PXA25x processor. The watchdog-reset functionality is also carried over. However, the input clock used to increment the OSCR0 counter has changed. For the Marvell PXA25x processor, this clock was 3.6864 MHz. For the PXA300 processor or PXA310 processor, the clock frequency is 3.25 MHz. Recalculate any time periods that must be exact. -
Page 415: External Synchronization (Ext_Sync<1:0>)
OSCRx matches the value programmed in OSMRx. Once this match occurs, the counter OSCRx resets to 0x0000_0000 and stops incrementing. The corresponding CHOUTx output pin is held low. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... -
Page 416: Snapshot Mode
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual • If OMCRx[R] is cleared, and OMCRx[P] is set, the counter starts at 0x0000_0000 and increments at the frequency of the channel clock until OSCRx matches the value programmed in OSMRx. Upon finding this match, CHOUTx is inverted, and the counter OSCRx continues counting. -
Page 417: Os Match Control Registers (Omcrx)
0b11 = reserved Reset OSCRx on Match 0 = OSCRx does not reset when a match occurs. 1 = OSCRx does reset when a match occurs. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 417 Not approved by Document Control. -
Page 418: Omcr8/10 Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 14-2. OMCR4/5/6/7 Bit Definitions (Sheet 2 of 2) 0x40A0_00C0 OMCR4 0x40A0_00C4 OMCR5 OS TImers 0x40A0_00C8 OMCR6 0x40A0_00CC OMCR7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 419: Not Approved By Document Control. For Review Only
0b11 = reserved Reset OSCRx on Match 0 = OSCRx does not reset when a match occurs. 1 = OSCRx does reset when a match occurs. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 419 Not approved by Document Control. -
Page 420: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 14-3. OMCR8/10 Bit Definitions (Sheet 3 of 3) 0x40A0_00D0 OMCR8 OS TImers 0x40A0_00D8 OMCR10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 421: Omcr9/11 Bit Definitions
0b11 = reserved Reset OSCRx on Match 0 = OSCRx does not reset when a match occurs. 1 = OSCRx does reset when a match occurs. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 421 Not approved by Document Control. -
Page 422: Os Timer Match Registers (Osmrx)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 14-4. OMCR9/11 Bit Definitions (Sheet 2 of 2) 0x40A0_00D4 OMCR9 OS TImers 0x40A0_00DC OMCR11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 423: Os Timer Watchdog Match Enable Register (Ower)
(hardware, sleep, watchdog, or GPIO). Writing a zero to the enable bit after it has been set has no effect. Table 14-6 shows the bit locations for the OWER register. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006... -
Page 424: Os Timer Interrupt Enable Register (Oier)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Table 14-6. OWER Bit Definitions 0x40A0_0018 OWER Register OS Timers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 425: Os Timer Count Registers (Oscr4-Oscr11)
OIER register. If a non-zero match value is loaded that equals the value of the corresponding OS Counter register, or a Counter register is loaded with non-zero a value that equals the Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 426: Os Timer Snapshot Register (Osnr)
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual corresponding Match register, the status bit is set immediately before the next rising clock edge for the counters if the respective OIER(x) is set to 1. The OSSR bits are cleared by writing a one to the proper bit position. -
Page 427: Register Summary
0x40A0_00C0 OMCR4 OS Match Control register 4 0x40A0_00C4 OMCR5 OS Match Control register 5 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 427 Not approved by Document Control. For review only. -
Page 428: Not Approved By Document Control. For Review Only
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 14-12. OS Timers Register Summary (Sheet 2 of 2) Physical Name Description Page Address 0x40A0_00C8 OMCR6 OS Match Control register 6 0x40A0_00CC OMCR7 OS Match Control register 7... -
Page 429: Performance Monitoring And Debug
15.1.1 Differences Between the PXA300 Processor and PXA310 Processor There are no significant differences between the PXA300 processor or PXA310 processor that relate to the Performance Monitoring Unit. 15.2 Features These performance monitoring and debug features are supported: •... -
Page 430: Operation
The following events are produced and can be connected to the eight event signals supplied to the core. These events are connected to performance monitoring event numbers 0x80 - 0x87 of the processor core. Table 15-1. PXA300 Processor and PXA310 Processor Performance Monitor Events (Sheet 1 of 4) - Page 431 Performance Monitoring and Debug Table 15-1. PXA300 Processor and PXA310 Processor Performance Monitor Events (Sheet 2 of 4) Event Event Description Number Reserved Dynamic memory queue occupied (number of cycles when the dynamic memory controller queue is not empty) Dynamic memory queue occupied by more than one request (number of cycles when the...
- Page 432 PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 15-1. PXA300 Processor and PXA310 Processor Performance Monitor Events (Sheet 3 of 4) Event Event Description Number Reserved Reserved Reserved System Bus 1 bus request Length of time that at least one bus request is asserted on System Bus 1...
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Page 433: Debug Functionality
Performance Monitoring and Debug Table 15-1. PXA300 Processor and PXA310 Processor Performance Monitor Events (Sheet 4 of 4) Event Event Description Number System Bus 1 to dynamic/static memory read/write latency measurement Amount of time when System Bus 1 to dynamic/static memory has more than two read/write... -
Page 434: Register Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual There are several different parts to the system whose detection of an event can be combined to form an overall operation. ® • Intel XScale core abrupt-stop event (XCS) ®... -
Page 435: Pxa300 Processor And Pxa310 Processor Debug Unit (Mdu) Configuration Registers
NUMBER PML_ESEL_1 refers to input 1, and so on) 15.5.2 PXA300 Processor and PXA310 Processor Debug Unit (MDU) Configuration Registers One register is provided for each destination event. All registers are identical, even though some combinations may not provide useful function. -
Page 436: Mdu_Xscale_Bp Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 15-3. MDU_XSCALE_BP Bit Definitions Physical Address 0x4600_FF40 MDU_XSCALE_BP PML/MDU Module User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 437: Mdu_2Dg_Event Bit Definitions
0 – Not allowed EVENT 1 – Allows a 2-D graphics subsystem debug event to provoke the output — Reserved Reserved Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 437... -
Page 438: Register Summary
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 15.5.2.3 MDU CW Match Signal Register (MDU_CW_MATCH) Table 15-5. MDU_CW_MATCH Bit Definitions Physical Address MDU_CW_MATCH PML/MDU Module 0x4600_FF58 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... - Page 439 MDU CW Match Signal register 0x4600_FF58 — Reserved — 0x4600_FF5C — Reserved — 0x4600_FF80 — Reserved — Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 439 Not approved by Document Control. For review only.
- Page 440 PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 12/13/06 Marvell Page 440 Document Classification: Proprietary Information December 13, 2006 Not approved by Document Control. For review only.
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Page 441: System Bus Arbiters
The arbitration for bus access is performed by the arbiter, which is programmable through the ARB_CNTRL_2 register. 16.1.1 Differences Between PXA300 Processor or PXA310 Processor There are no differences between the PXA300 processor and PXA310 processor in this section. 16.2 Features • Programmable client weights •... -
Page 442: Programmable Weights
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 16.4.1 Programmable Weights The lower bits of the Arbiter Control registers (as shown in Table 16-1 Table 16-2) determine the arbitration priority of the clients on the bus. The values programmed in the weight fields of the ARB_CNTRL_x registers configure the relative importance of the programmable clients on the bus. -
Page 443: Bus Parking
System Bus Arbiters Note: Unlike the Marvell PXA27x processor family, there is no need to force the core to have high performance relative to the other devices. The main core path to memory is now via the switch, and the core accesses on the system buses are mainly software-configuration commands. -
Page 444: System Considerations: System Bus Access Latency
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 16.4.4 System Considerations: System Bus Access Latency ® The system has seven masters (switch (core), DMA, LCD, Intel Quick Capture Camera Interface, USB 1.1 full speed host, 2-D graphics, and USB 2.0 high speed client) on the two system buses (see Figure 16-1). -
Page 445: Register Descriptions
System Bus Arbiters Figure 16-1. PXA300 Processor or PXA310 Processor Block Diagram PC-Card / Sync / Async XCVR CompactFlas Flash Sensor UTMI Panel Driscoll Intel XScale® VLIO NAND Intel® Core Wireless (32K I$, 32K D$) 16-Bit MMX™ USB2.0 High Data Flash Interface... -
Page 446: Arb_Cntrl_1 Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 16-1. ARB_CNTRL_1 Bit Definitions Physical Address ARB_CNTRL_1 Internal Bus Arbiter 0x4600_FE00 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... - Page 447 Values in this field determine the relative priority of the switch (core) SWITCH_WT ® requests for the bus vis-a-vis DMA, Intel Quick Capture interface, and LCD requests. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 447...
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Page 448: Arb_Cntrl_2 Bit Definitions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 16-2. ARB_CNTRL_2 Bit Definitions (Sheet 1 of 2) Physical Address ARB_CNTRL_2 Internal Bus Arbiter 0x4600_FE04 User Settings 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 449: Register Summary
0x4600_FE00 ARB_CNTRL_1 System Bus #1 Bus Arbiter Control register 0x4600_FE04 ARB_CNTRL_2 System Bus #2 Bus Arbiter Control register Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 449 Not approved by Document Control. For review only. - Page 450 PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-TBD-00 Rev. A CONFIDENTIAL Copyright © 12/13/06 Marvell Page 450 Document Classification: Proprietary Information December 13, 2006 Not approved by Document Control. For review only.
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Page 451: Jtag
17.1 Overview This chapter describes all supported JTAG features for the PXA300 processor or PXA310 processor. JTAG provides a way of driving and sampling the external pins of the device regardless of the core state. This enables test of both the device electrical connections to the circuit board and (in conjunction with other devices on the circuit board having a similar interface) the integrity of the circuit board connections between devices. -
Page 452: Features
The JTAG interface includes a TAP controller state machine. To force the TAP controller into the correct state at powerup, the nTRST pin can be asserted low, or the TMS pin can be held high for five TCK cycles. Marvell recommends that nTRST be driven from low to high either before or at the same time as the hardware nRESET Doc. -
Page 453: Instruction Register
TMS high for five TCK cycles or asynchronously via nTRST. This is described further in Section 17.4.4.1. In the case where JTAG is not used, Marvell recommends that a reset IC be used to cause a reset on nTRST at powerup. See the PXA300 Processor Design Guide and the ARM* application note, Multi-ICE System Design Considerations, Application Note 72 for more details. -
Page 454: Test Data Registers
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 17-2. JTAG Instruction Description (Sheet 2 of 2) Instruction Opcode Description / Requisite The sample/preload instruction performs two functions: • When the TAP controller is in the Capture-DR state, the sample instruction occurs on the rising edge of TCK and provides a snapshot of the component’s normal... - Page 455 As such, no JTAG instructions using the BSR can be performed with nBATT_FAULT or nRESET_IN at 0x0, or with the device in deep sleep (D4/S3). In addition, Marvell recommends that the nRESET_OUT pin be allowed to de-assert to active high state (0x1) before proceeding with any instructions that use the BSR. This is an indication that the part has powered up correctly.
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Page 456: Tap Controller
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 17-3. JTAG Device Identification Register JTAG Device Identification (ID) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9... -
Page 457: Tap Controller State Diagram
TAP controller is in this state. The Instruction register and all test data registers retain their current state. When TMS is high on the rising edge of TCK, the TAP controller moves to the select-DR-scan state. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A... - Page 458 PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual 17.4.4.3 Select-DR-Scan State The select-DR-scan state is a temporary TAP controller state. The test-data registers selected by the current instruction retain their previous state. If TMS is held low on the rising edge of TCK when the TAP controller is in this state, the TAP controller moves into the capture-DR state and a scan sequence for the selected test-data register is initiated.
- Page 459 TDI and TDO and shifts data one bit position nearer to its serial output on each rising edge of TCK. The test-data register selected by the current instruction retains its previous value during this state. The instruction does not change. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A...
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Page 460: Register Descriptions
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual If TMS is held high on the rising edge of TCK, the TAP controller enters the exit1-IR state. If TMS is held low on the rising edge of TCK, the TAP controller remains in the shift-IR state. -
Page 461: Memory Map
18.2 Differences Between the PXA300 Processor and PXA310 Processor The difference between the PXA300 processor and the PXA310 processor memory map is the addition of the video accelerator (0x5600_0000) and MMC/SD/SDIO controller (0x4250_0000) address space on the PXA310 processor. Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. -
Page 462: Memory Map (Part 1) — From 0X0000_0000 To 0X7Fff_Ffff
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 18-1. Memory Map (Part 1) — From 0x0000_0000 to 0x7FFF_FFFF (Sheet 1 of 2) Memory Map 0x7C00_0000 Reserved (64 MB) 0x7800_0000 Reserved (64 MB) 0x7400_0000 Reserved (64 MB) -
Page 463: Memory Map (Part Two) — From 0X8000_0000 To 0Xffff Ffff
0xDC00_0000 Note: MDCNFG[DMAP] must be set. 0xD800_0000 0xD400_0000 0xD000_0000 0xCC00_0000 0xC800_0000 0xC400_0000 0xC000_0000 Copyright © 12/13/06 Marvell CONFIDENTIAL Doc. No. MV-TBD-00 Rev. A December 13, 2006 Document Classification: Proprietary Information Page 463 Not approved by Document Control. For review only. -
Page 464: Memory-Mapped Registers Summary
Table 18-3 gives a summary of the memory map area from 0x4000_0000 to 0x5BFF_FFFF. This area contains memory-mapped registers stored within the various units and peripherals in the PXA300 processor or PXA310 processor. Table 18-3. Register Address Summary for the PXA300 or PXA310 Processor (Sheet 1 of 3) - Page 465 Memory Map Table 18-3. Register Address Summary for the PXA300 or PXA310 Processor (Sheet 2 of 3) Unit Address OS Timer 0x40A0_0000 PWM0 and PWM2 0x40B0_0000 PWM1 and PWM3 0x40C0_0000 Interrupt Control 0x40D0_0000 GPIO Controller 0x40E0_0000 Slave Power Manager (BPMU) and...
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Page 466: Boot Rom Space
PXA300 Processor and PXA310 Processor Vol. I: System and Timer Configuration Developers Manual Table 18-3. Register Address Summary for the PXA300 or PXA310 Processor (Sheet 3 of 3) Unit Address Performance Monitoring and Debug 0x4600_FF00 - 0x4600_FFFF Reserved 0x4601_0000 - 0x480F_FFFF... - Page 467 THIS PAGE INTENTIONALLY LEFT BLANK...
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