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OMAP OMAP5912 Reference Manual

Multimedia processor real-time clock and split power
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OMAP5912 Multimedia Processor
Real-Time Clock and Split Power
Reference Guide
Literature Number: SPRU782A
March 2004

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Summary of Contents for OMAP OMAP5912

  • Page 1 OMAP5912 Multimedia Processor Real-Time Clock and Split Power Reference Guide Literature Number: SPRU782A March 2004...
  • Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

  • Page 3: Read This First

    OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference Guide (literature number SPRU749) introduces and briefly defines the main features of the OMAP3.2 subsystem of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit- erature number SPRU750) describes the OMAP5912 multimedia proc- essor DSP subsystem.
  • Page 4 (DPLL) and the analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (litera- ture number SPRU752) describes the reset architecture, the configura- tion, the initialization, and the boot ROM of the OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management in the OMAP5912 multimedia processor.
  • Page 5 OMAP5912 USB function controller, and other OMAP5912 peripherals allow a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing SPRU782A...
  • Page 6 When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
  • Page 7 The external devices are mapped into local, physical address space and ap- pear as if they are on the internal bus of the OMAP 5912. The external devices must also have a VLYNQ interface. The VLYNQ module serial-...
  • Page 8 (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit- erature number SPRUxxx) describes the real-time clock of the OMAP5912 multimedia processor. The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface.

  • Page 9: Table Of Contents

    ....Resets for OMAP5912 Device With Split Power Feature Not Used ....
  • Page 10 ..........ON to OFF With SPLIT POWER = 1 for OMAP5912 RESET_MODE = 0 .
  • Page 11 ........SPRU782A OMAP5912...

  • Page 12: Overview

    Real Time Clock (RTC) Overview The real-time clock (RTC) block is an embedded real-time clock module directly accessible from the TIPB bus interface. The basic functions of RTC block are: Time information (seconds/minutes/hours) directly in binary coded decimal (BCD) code Calendar information (day/month/year/day of the week) directly in BCD code up to the year 2099 Interrupt generation, periodically (1s/1m/1h/1d period) or at a precise time...

  • Page 13: Split Power Overview

    Split Power Overview Figure 1. Real-Time Clock 32 kHz 32-kHz Compensation Control Week counter days Seconds Minutes Hours Days Months Years IRQ_ALARM Alarm Interrupt IRQ_ALARM IRQ_TIMER Split Power Overview To achieve minimum consumption in the OFF state in device equipment, some active logic elements are supplied.

  • Page 14: Internal Level Shifters

    Internal Level Shifters Figure 2. Split Power System in OMAP5912 OMAP5912 CVDDRTC Split power ring level shifters DVDDRTC RESERWRON_CORE POWERDOWN RESET_MODE Split power logic RTC_ON_NOFF control RTC_WAKE_INT PWRON_RESET CLK32K_OUT 32 kHz reset and select XO32K conf CLK32K_IN CLK32K registers XO32K...

  • Page 15: Split Power Block

    Split Power Block UC470: Powered by the secondary power supply. Because of the differential signals, A and AZ (given by UC469), it creates the signal Y that is equivalent to the input of UC469 but in the second core supply domain. This cell has a PWRDN signal so that when power supply of UC469 does not exist (input signals A and AZ are ambiguous), this cell does not have any through-current and the output is set to 0.

  • Page 16: Interface Block

    Output Control Figure 4. Split Power Block Diagram CLK_32kHz_CORE UC470 UC469 UC469 pwrdn UC470 pwrdn UC469 UC470 pwrdn UC469 UC470 pwrdn UC469 UC470 pwrdn UC469 UC470 TIPB pwrdn Backup block Interface block Interface Block This block separates the backup elements and the ASIC core. It also contains the UC469 and some logic.

  • Page 17: Backup Signal Management

    OMAP5912 ASIC gates. Resets for OMAP5912 Device With Split Power Feature Not Used For OMAP5912 devices that are forced during reset in reset mode 1, PWRON_RESET_CORE is logically equal to PWRON_RESET and only to PWRON_RESET.

  • Page 18: Rtc_Wake_Int

    The RTC_CTRL_REG.SPLIT_POWER signal generates RTC_WAKE_INT to avoid an RTC_WAKE_INT in ON mode for the ABB. Figure 7 shows the generation of the RTC_WAKE_INT. In the OMAP5912 core, IRQ_SET is not used and is set to 0. RTC_WAKE_INT is used only for the ABB. SPRU782A...

  • Page 19: Using Split Power

    ULPD : IRQ_SET Using Split Power ABB Functions Incompatible With Split Power Do not use split power. The power cannot be cut in the core. Figure 8. OMAP5912 in RESET_MODE = 1 or RTC_CTRL_REG.SPLIT_POWER = 0 Power on Reset release CLK32K_IN Unknown...

  • Page 20: Abb Functions Compatible With Split Power

    Using Split Power ABB Functions Compatible With Split Power Figure 9. Startup With RTC_CTRL_REG.SPLIT_POWER = 1 for OMAP5912 RESET_MODE = 0 Main battery Start of the core insertion 32 kHz clock CLK_32_OUT RTC_ON_NOFF RESPWRON_CORE CLK32K_CORE RESET_MODE = 0 Figure 9 assumes that backup battery is already inserted, only the RTC power domain is powered and that the RTC is isolated from the core (RTC_ON_NOFF ball is held low, and SPLIT_POWER bit in RTC is set to 1).

  • Page 21: On To Off Description

    Using Split Power ON to OFF Description Figure 10. ON to OFF With SPLIT POWER = 1 for OMAP5912 RESET_MODE = 0 Switch off event Internal RTC 32kHz Clock PWRON_RESET RTC_ON_NOFF RESPWRON_CORE CLK32K_CORE POWERDOWN RESET_MODE_0 On a switch-off event, RTC_ON_NOFF is set to 0. The 32-kHz clock is not fed to OMAP5912 core anymore, and PWRON_RESET_CORE is set to 0 to indicate that the device goes into OFF state.

  • Page 22: Off To On Description

    Using Split Power OFF to ON Description Figure 11. OFF to ON With RTC_CTRL_REG.SPLIT_POWER = 1 for OMAP5912 RESET_MODE = 0 Switch on Event Start of the 32-kHz Core Clock Internal CLK_32 PWRON_RESET RTC_ON_NOFF RESPWRON_CORE CLK32K_CORE POWERDOWN RESET_MODE_0 On a switch-on event, the ASIC LDO regulators are enabled. The DBB core is also supplied and reset by PWRON_RESET_CORE until RTC_ON_NOFF is set to 1.

  • Page 23: Alarm Interrupt

    Using Split Power The IT_TIMER bit of the interrupt register enables this interrupt. It is a negative edge-sensitive interrupt (low-level pulse duration = 15 µs). The RTC_STATUS_REG[5:2] are only updated at each new interrupt and show the events that have occurred, according to Table 1. Table 1.

  • Page 24: Oscillator Drift Compensation

    Using Split Power Figure 13. Alarm Interrupt CLK_32kHz CPT_32kHz 32767 BUSY Alarm TC register = TC register IRQ_ALARM Write 1 into STATUS[6] Oscillator Drift Compensation To compensate for any inaccuracy of the 32-kHz oscillator, the MPU can perform a calibration of the oscillator frequency, calculate the drift compensation versus one-hour period, and load the compensation registers with the drift compensation value.

  • Page 25: Split Power Compatibility

    Using Split Power Figure 14. Oscillator Drift Compensation No compensation Clk 32 kHz Timer counter 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 0000 0001 Second update Negative compensation: COMP_REG = +2 Clk 32 kHz Timer counter 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 0002 0003...

  • Page 26: Rtc Registers

    Using Split Power A power-down signal has been added to set the outputs to 0 in OFF. RTC Registers There are three types of registers: Time and calendar, and time and calendar alarm General Compensation These three types have their own access constraints. 11.1 Time and Calendar Registers and Time and Calendar Alarm Registers...

  • Page 27: General Registers

    Using Split Power Figure 15. Time and Calendar Register and Time and Calendar Alarm Register Access Read BUSY bit Forbidden TC register access Available TC regiter access Available TC regiter access Available TC regiter access 15 µs 15 µs 15 µs STROBE Any Read/Write TC register access BUSY...

  • Page 28: Setting Time And Calendar Information

    Using Split Power Figure 16. Compensation Scheduling HOURS SECONDS Load comp registers Compensation event Compensation event HOURS COMP_EN SECONDS BUSY Hour event Load comp registers Compensation event Setting Time and Calendar Information 12.1 Modify Time and Calendar Registers To modify the current time, the MPU writes the new time into time and calendar registers to fix the time/calendar information.

  • Page 29: Rounding Seconds

    Using Split Power 12.2 Rounding Seconds Time can be rounded to the closest minute by setting the ROUND_30S bit of the control register. When this bit is set, time and calendar values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when rounding time is performed.

  • Page 30: Time And Calendar Registers

    Using Split Power Table 2. RTC Registers (Continued) Base Address = 0xFFFB 4800 Name Description Address Offset RESERVED Reserved 0x3C RTC_CTRL_REG RTC control 0x40 RTC_STATUS_REG RTC status 0x44 RTC_INTERRUPTS_REG RTC interrupt 0x48 RTC_COMP_LSB_REG RTC compensation LSB 0x4C RTC_COMP_MSB_REG RTC compensation MSB 0x50 RTC_OSC_REG RTC oscillator...

  • Page 31: Seconds Register (Seconds_Reg)

    Using Split Power Table 3. Time and Calendar Register Time Units (Continued) Minutes 00 to 59 Seconds 00 to 59 Table 4. Seconds Register (SECONDS_REG) Base Address = 0xFFFB 4800, Offset = 0x00 Name Function Reset SEC1 digit of seconds 0000 Range is 0 to 5.

  • Page 32: Months Register (Months_Reg)

    Using Split Power Table 7. Days Register (DAYS_REG) (Continued) Base Address = 0xFFFB 4800, Offset = 0x0C Name Function Reset DAY1 digit of days 0000 Range is 0 to 3. DAY0 digit of days 0001 Range is 0 to 9. Table 8.

  • Page 33: Weeks Register (Weeks_Reg)

    Using Split Power Table 10. Weeks Register (WEEKS_REG) Base Address = 0xFFFB 4800, Offset = 0x18 Name Function Reset WEEK digit of days in a week 0000 Range is 0 to 6. Table 11. Reserved Base Address = 0xFFFB 4800, Offset = 0x1C Name Function Reset...

  • Page 34: Alarm Hours Register (Alarm_Hours_Reg)

    Using Split Power Table 14. Alarm Hours Register (ALARM_HOURS_REG) Base Address = 0xFFFB 4800, Offset = 0x28 Name Function Reset ALARM_PM_AM Only used in PM_AM mode (otherwise 0) 0: AM 1: PM ALARM_HOUR1 digit of hours Range is 0 to 2. ALARM_HOUR0 digit of hours 0000...

  • Page 35: Rtc Control Register (Rtc_Ctrl_Reg)

    Using Split Power Table 17. Alarm Years Register (ALARM_YEARS_REG) (Continued) Base Address = 0xFFFB 4800, Offset = 0x34 Name Function Reset ALARM_YEAR0 digit of years 0000 Range is 0 to 9. Table 18. RTC Control Register (RTC_CTRL_REG) Base Address = 0xFFFB 4800, Offset = 0x40 Name Function Reset...

  • Page 36: Rtc Status Register (Rtc_Status_Reg)

    Using Split Power MODE_12_24: It is possible to switch between the two modes at any time without disturbing the RTC. Read or write is always performed with the current mode. Table 19. RTC Status Register (RTC_STATUS_REG) Base Address = 0xFFFB 4800, Offset = 0x44 Name Function Reset...

  • Page 37: Rtc Interrupts Register (Rtc_Interrupts_Reg)

    Using Split Power Table 20. RTC Interrupts Register (RTC_INTERRUPTS_REG) Base Address = 0xFFFB 4800, Offset = 0x48 Name Function Reset IT_ALARM Enables one interrupt when the alarm value is reached (time and calendar alarm registers) by the time and calendar registers IT_TIMER Enable periodic interrupt 0: Interrupt disabled...

  • Page 38: Rtc Compensation Msb Register (Rtc_Comp_Msb_Reg)

    Using Split Power Table 22. RTC Compensation MSB Register (RTC_COMP_MSB_REG) Base Address = 0xFFFB 4800, Offset = 0x50 Name Function Reset RTC_COMP_MSB Indicates number of 32-kHz 0x00 periods to be added into the 32-kHz counter every hour Table 23. RTC Oscillator Register (RTC_OSC_REG) Base Address = 0xFFFB 4800, Offset = 0x54 Name Function...
  • Page 39 Real-Time Clock (RTC) SPRU782A...
  • Page 40 Index Index registers 27 setting time and calendar information 29 split power 14 Internal level shifters 15 split power block 16 split power compatibility 26 using split power 20 related documentation from Texas Instruments 3 notational conventions 3 RTC interrupt management 23 RTC oscillator drift compensation 25 RTC output control 17 RTC registers 27...

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