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SONIX SN8P2711A User Manual

8-bit micro-controller
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SN8P2711A
USER'S MANUAL
Version 0.1
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
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Page 1
8-Bit Micro-Controller
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Version 0.1
SN8P2711A

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  • Page 1 SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur.

  • Page 2: Amendent History

    SN8P2711A 8-Bit Micro-Controller AMENDENT HISTORY Version Date Description VER 0.1 Jun. 2007 First issue. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 2...

  • Page 3: Table Of Contents

    IMMEDIATE ADDRESSING MODE ..................34 2.2.2 DIRECTLY ADDRESSING MODE ..................34 2.2.3 INDIRECTLY ADDRESSING MODE ................... 34 STACK OPERATION........................35 2.3.1 OVERVIEW..........................35 2.3.2 STACK REGISTERS....................... 36 2.3.3 STACK OPERATION EXAMPLE..................37 RESET ............................. 38 Version 0.1 SONiX TECHNOLOGY CO., LTD Page 3...
  • Page 4 OVERVIEW..........................59 5.3.2 WAKEUP TIME ........................59 INTERRUPT........................... 60 OVERVIEW............................. 60 INTEN INTERRUPT ENABLE REGISTER................... 61 INTRQ INTERRUPT REQUEST REGISTER ................62 GIE GLOBAL INTERRUPT OPERATION ..................63 PUSH, POP ROUTINE ........................64 Version 0.1 SONiX TECHNOLOGY CO., LTD Page 4...
  • Page 5 TCnIRQ and PWM Duty......................100 8.4.3 PWM Duty with TCnR Changing ..................101 8.4.4 PWM PROGRAM EXAMPLE ....................102 5+1 CHANNEL ANALOG TO DIGITAL CONVERTER............103 OVERVIEW........................... 103 ADM REGISTER ........................... 104 ADR REGISTERS.......................... 105 Version 0.1 SONiX TECHNOLOGY CO., LTD Page 5...
  • Page 6 13.2 SOP 14 PIN............................. 128 13.3 SSOP 16 PIN........................... 129 MARKING DEFINITION....................130 14.1 INTRODUCTION .......................... 130 14.2 MARKING INDETIFICATION SYSTEM..................130 14.3 MARKING EXAMPLE ......................... 131 14.4 DATECODE SYSTEM ........................131 Version 0.1 SONiX TECHNOLOGY CO., LTD Page 6...

  • Page 7: Product Overview

    SN8P2711A 8-Bit Micro-Controller PRODUCT OVERVIEW SN8P2711A is modified from SN8P2711. Good internal high RC frequency 16MHz±2%. Good high noisy protecting performance for household application. SN8P2711 is compatible to SN8P2711A. Better IHRC performance from 16MHz±5% to 16MHz±2%. Good brown out reset production.
  • Page 8 0xnnFF ROM address. 32KHz oscillator mode Not support. Support 32KHz mode. SN8P2711 SN8 file can program into SN8P2711A SN8 file (e.g. Re-compile SN8P2711A OTP directly by EZ/MP SN8P2711 source code with declaring Firmware comparison writer. S8P2711A, SN8P2711A new code... ) can't program into SN8P2711 OTP directly by EZ/MP writer.

  • Page 9: System Block Diagram

    TIMING GENERATOR PWM 0 PWM0 BUZZER 0 BUZZER0 PWM 1 PWM1 BUZZER 1 BUZZER1 SYSTEM REGISTERS 12-BIT ADC AIN0~AIN4 Internal Reference INTERRUPT Internal ADC CONTROL TIMER & COUNTER Channel for Battery Detect Version 0.1 SONiX TECHNOLOGY CO., LTD Page 9...

  • Page 10: Pin Assignment

    SN8P2711AS (SOP 14 pins) P0.3/XIN P4.4/AIN4 P0.2/XOUT P4.3/AIN3 P0.4/RST/VPP P4.2/AIN2 P5.3/BZ1/PWM1 P4.1/AIN1 P5.4/BZ0/PWM0 P4.0/AIN0/VREFH P0.1/INT1 P0.0/INT0 SN8P2711AP SN8P2711AS SN8P2711AX (SSOP 16 pins) P0.3/XIN P4.4/AIN4 P0.2/XOUT P4.3/AIN3 P0.4/RST/VPP P4.2/AIN2 P5.3/BZ1/PWM1 P4.1/AIN1 P5.4/BZ0/PWM0 P4.0/AIN0/VREFH P0.1/INT1 P0.0/INT0 SN8P2711AX Version 0.1 SONiX TECHNOLOGY CO., LTD Page 10...

  • Page 11: Pin Descriptions

    TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin. Port 5.4 bi-direction pin. Schmitt trigger structure as input mode. P5.4/BZ0/PWM0 Built-in pull-up resisters. TC0 ÷ 2 signal output pin for buzzer or PWM0 output pin. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 11...

  • Page 12: Pin Circuit Diagrams

    Input Bus Output Output Bus Latch Int. Osc. Port 0.4 structure: Ext. Reset Code Option Int. Bus Int. Rst Port 0, 5 structure: Pull-Up PnM, PnUR Input Bus Output Output Bus Latch Version 0.1 SONiX TECHNOLOGY CO., LTD Page 12...
  • Page 13 Pull-Up P4CON PnM, PnUR EVHENB Input Bus Output Output Bus Latch GCHS Int. ADC Int. VERFH Port 4 structure: Pull-Up P4CON PnM, PnUR Input Bus Output Output Bus Latch GCHS Int. ADC Version 0.1 SONiX TECHNOLOGY CO., LTD Page 13...

  • Page 14: Central Processor Unit (Cpu)

    Jump to user start address 0001H General purpose area 0007H 0008H User interrupt vector Interrupt vector 0009H User program 000FH 0010H 0011H General purpose area 03FCH End of user program 03FDH Reserved 03FEH 03FFH Version 0.1 SONiX TECHNOLOGY CO., LTD Page 14...

  • Page 15: Reset Vector (0000H)

    Example: Defining Reset Vector ; 0000H START ; Jump to user program address. … START: ; 0010H, The head of user program. … ; User program … ENDP ; End of program Version 0.1 SONiX TECHNOLOGY CO., LTD Page 15...

  • Page 16: Interrupt Vector (0008H)

    RETI ; End of interrupt service routine … START: ; The head of user program. … ; User program … START ; End of user program … ENDP ; End of program Version 0.1 SONiX TECHNOLOGY CO., LTD Page 16...
  • Page 17 ENDP ; End of program. Note: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.

  • Page 18: Look-Up Table Description

    Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Example: INC_YZ macro. INC_YZ MACRO INCMS ; Z+1 ; Not overflow INCMS ; Y+1 ; Not overflow ENDM Version 0.1 SONiX TECHNOLOGY CO., LTD Page 18...
  • Page 19 ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 … TABLE1: 0035H ; To define a word (16 bits) data. 5105H 2012H … Version 0.1 SONiX TECHNOLOGY CO., LTD Page 19...

  • Page 20: Jump Table Description

    ; ACC = 3, jump to A3POINT SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
  • Page 21 SN8P2711A 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A ; The number of the jump table listing is five. A0POINT ; ACC = 0, jump to A0POINT A1POINT ;...

  • Page 22: Checksum Calculation

    ; If Not jump to checksum calculate CHECKSUM_END ; If Yes checksum calculated is done. Y_ADD_1: INCMS ; Increase Y ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end Version 0.1 SONiX TECHNOLOGY CO., LTD Page 22...

  • Page 23: Code Option Table

    If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog” automatically. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the Fosc is internal low clock). Version 0.1 SONiX TECHNOLOGY CO., LTD Page 23...

  • Page 24: Data Memory (Ram)

    General purpose area “ “ “ 03Fh BANK 0 080h 080h~0FFh of Bank 0 store system registers (128 bytes). “ “ System register “ “ “ 0FFh End of bank 0 area Version 0.1 SONiX TECHNOLOGY CO., LTD Page 24...

  • Page 25: System Register

    TC1R = TC1 auto-reload data buffer. STKP = Stack pointer buffer. PnUR = Port n pull-up resister control register. @YZ = RAM YZ indirect addressing index pointer. STK0~STK3 = Stack 0 ~ stack 3 buffer. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 25...

  • Page 26: Bit Definition Of System Register

    2. All of register names had been declared in SN8ASM assembler. 3. One-bit name had been declared in SN8ASM assembler with “F” prefix code. 4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 26...

  • Page 27: Accumulator

    “PUSH”, “POP” save and load ACC, PFLAG data into buffers. Example: Protect ACC and working registers. INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector Version 0.1 SONiX TECHNOLOGY CO., LTD Page 27...

  • Page 28: Program Flag

    1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero. Note: Refer to instruction set table for detailed information of C, DC and Z flags. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 28...

  • Page 29: Program Counter

    If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS A, #12H ; To skip, if ACC = 12H. C0STEP ; Else jump to C0STEP. … … C0STEP: Version 0.1 SONiX TECHNOLOGY CO., LTD Page 29...
  • Page 30 DECS BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: DECMS instruction: DECMS BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: Version 0.1 SONiX TECHNOLOGY CO., LTD Page 30...
  • Page 31 ; If ACC = 0, jump to A0POINT A1POINT ; ACC = 1, jump to A1POINT A2POINT ; ACC = 2, jump to A2POINT A3POINT ; ACC = 3, jump to A3POINT … … Version 0.1 SONiX TECHNOLOGY CO., LTD Page 31...

  • Page 32: Y, Z Registers

    ; Clear @YZ to be zero DECMS ; Z – 1, if Z= 0, finish the routine CLR_YZ_BUF ; Not zero END_CLR: ; End of clear general purpose data memory area of bank 0 … Version 0.1 SONiX TECHNOLOGY CO., LTD Page 32...

  • Page 33: R Registers

    Bit 3 Bit 2 Bit 1 Bit 0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 Read/Write After reset Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 33...

  • Page 34: Addressing Mode

    ; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 34...

  • Page 35: Stack Operation

    High Byte Low Byte STKP = 3 STK3H STK3L STKP + 1 STKP - 1 STKP = 2 STK2H STK2L STKP = 1 STK1H STK1L STKP STKP STKP = 0 STK0H STK0L Version 0.1 SONiX TECHNOLOGY CO., LTD Page 35...

  • Page 36: Stack Registers

    Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0 STKnL Read/Write After reset STKn = STKnH , STKnL (n = 3 ~ 0) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 36...

  • Page 37: Stack Operation Example

    (PC) to the program counter registers. The Stack-Restore operation is as the following table. STKP Register Stack Buffer Stack Level Description STKPB2 STKPB1 STKPB0 High Byte Low Byte STK3H STK3L STK2H STK2L STK1H STK1L STK0H STK0L Free Free Version 0.1 SONiX TECHNOLOGY CO., LTD Page 37...

  • Page 38: Reset

    High Detect Low Detect Watchdog Overflow Watchdog Normal Run Watchdog Reset Watchdog Stop System Normal Run System Status System Stop Power On External Watchdog Delay Time Reset Delay Reset Delay Time Time Version 0.1 SONiX TECHNOLOGY CO., LTD Page 38...

  • Page 39: Power On Reset

    Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the watchdog timer function. Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 39...

  • Page 40: Brown Out Reset

    DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 40...

  • Page 41: The System Operating Voltage Decsription

    2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The structure can improve noise effective and get good EFT characteristic. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 41...
  • Page 42 Delay Time The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU.
  • Page 43 IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 43...

  • Page 44: External Reset

    The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference. Note: The reset circuit is no any protection against unusual power or brown out reset. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 44...

  • Page 45: Diode & Rc Reset Circuit

    PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 45...

  • Page 46: Voltage Bias Reset Circuit

    When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 46...

  • Page 47: External Reset Ic

    The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 47...

  • Page 48: System Clock

    Fcpu = Fhosc / N, N = 1 ~ 16, Select N by Fcpu code option. Slow Mode (Low Clock): Fcpu = Flosc/4. SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well. 4.2 CLOCK BLOCK DIAGRAM...

  • Page 49: Oscm Register

    Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Version 0.1 SONiX TECHNOLOGY CO., LTD Page 49...

  • Page 50: System High Clock

    High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length. 4MHz Crystal 32768Hz Crystal 4MHz Ceramic Version 0.1 SONiX TECHNOLOGY CO., LTD Page 50...

  • Page 51: Crystal/Ceramic

    “R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin. Note: Connect the R and C as near as possible to the VDD pin of micro-controller. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 51...

  • Page 52: External Clock Signal

    XIN pin. XOUT pin is general purpose I/O pin. External Clock Input XOUT Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 52...

  • Page 53: System Low Clock

    ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1 (32K, watchdog disable) bits of OSCM register. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 53...

  • Page 54: System Clock Measurement

    ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC frequency. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 54...
  • Page 55 SN8P2711A 8-Bit Micro-Controller Version 0.1 SONiX TECHNOLOGY CO., LTD Page 55...

  • Page 56: System Operation Mode

    All active Wakeup source P0, TC0 Reset P0, Reset EHOSC: External high clock IHRC: Internal high clock (16M RC oscillator) ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 56...

  • Page 57: System Mode Switching Example

    ; Set CPUM1 = 1. Note: If TC0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 57...
  • Page 58 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TC1X8 TC0X8 TC0GN Read/Write After reset Bit 1 TC0GN: TC0 green mode wake-up function control bits. 0 = Disable. 1 = Enable. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 58...

  • Page 59: Wakeup

    The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz) The total wakeup time = 0.512ms + oscillator start-up time Version 0.1 SONiX TECHNOLOGY CO., LTD Page 59...

  • Page 60: Interrupt

    Interrupt Vector Address (0008H) TC0IRQ 5-Bit Enable TC0 Time Out TC1IRQ TC1 Time Out Global Interrupt Request Signal Latchs Gating ADCIRQ ADC Converting Successfully Note: The GIE bit must enable during all interrupt operation. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 60...

  • Page 61: Inten Interrupt Enable Register

    TC1IEN: TC1 timer interrupt control bit. 0 = Disable TC1 interrupt function. 1 = Enable TC1 interrupt function. Bit 7 ADCIEN: ADC interrupt control bit. 0 = Disable ADC interrupt function. 1 = Enable ADC interrupt function. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 61...

  • Page 62: Intrq Interrupt Request Register

    TC1IRQ: TC1 timer interrupt request flag. 0 = None TC1 interrupt request. 1 = TC1 interrupt request. Bit 7 ADCIRQ: ADC interrupt request flag. 0 = None ADC interrupt request. 1 = ADC interrupt request. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 62...

  • Page 63: Gie Global Interrupt Operation

    0 = Disable global interrupt. 1 = Enable global interrupt. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 63...

  • Page 64: Push, Pop Routine

    Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed. START INT_SERVICE START: … INT_SERVICE: PUSH ; Save ACC and PFLAG to buffers. … … ; Load ACC and PFLAG from buffers. RETI ; Exit interrupt service vector … ENDP Version 0.1 SONiX TECHNOLOGY CO., LTD Page 64...

  • Page 65: Int0 (P0.0) Interrupt Operation

    A, #18H B0MOV PEDGE, A ; Set INT0 interrupt trigger as bi-direction edge. B0BSET FP00IEN ; Enable INT0 interrupt service B0BCLR FP00IRQ ; Clear INT0 interrupt request flag B0BSET FGIE ; Enable GIE Version 0.1 SONiX TECHNOLOGY CO., LTD Page 65...
  • Page 66 ; P00IRQ = 0, exit interrupt vector B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.1 SONiX TECHNOLOGY CO., LTD Page 66...

  • Page 67: Int1 (P0.1) Interrupt Operation

    ; P01IRQ = 0, exit interrupt vector B0BCLR FP01IRQ ; Reset P01IRQ … ; INT1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.1 SONiX TECHNOLOGY CO., LTD Page 67...

  • Page 68: Tc0 Interrupt Operation

    A, #74H B0MOV TC0C, A ; Reset TC0C. … ; TC0 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.1 SONiX TECHNOLOGY CO., LTD Page 68...

  • Page 69: Tc1 Interrupt Operation

    A, #74H B0MOV TC1C, A ; Reset TC1C. … ; TC1 interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.1 SONiX TECHNOLOGY CO., LTD Page 69...
  • Page 70 SN8P2711A 8-Bit Micro-Controller Version 0.1 SONiX TECHNOLOGY CO., LTD Page 70...

  • Page 71: Adc Interrupt Operation

    ; ADCIRQ = 0, exit interrupt vector B0BCLR FADCIRQ ; Reset ADCIRQ … ; ADC interrupt service routine … EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.1 SONiX TECHNOLOGY CO., LTD Page 71...

  • Page 72: Multi-Interrupt Operation

    ; Jump to exit of IRQ B0BTS0 FADCIRQ ; Check ADCIRQ INTADC ; Jump to ADC interrupt service routine INT_EXIT: … ; Pop routine to load ACC and PFLAG from buffers. RETI ; Exit interrupt vector Version 0.1 SONiX TECHNOLOGY CO., LTD Page 72...

  • Page 73: I/O Port

    ; Set all ports to be output mode. B0MOV P0M, A B0MOV P4M,A B0MOV P5M, A B0BCLR P4M.0 ; Set P4.0 to be input mode. B0BSET P4M.0 ; Set P4.0 to be output mode. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 73...

  • Page 74: I/O Pull Up Register

    Note: P0.4 is input only pin and without pull-up resister. The P0UR.4 keeps “1”. Example: I/O Pull up Register A, #0FFH ; Enable Port0, 4, 5 Pull-up register, B0MOV P0UR, A B0MOV P4UR,A B0MOV P5UR, A Version 0.1 SONiX TECHNOLOGY CO., LTD Page 74...

  • Page 75: I/O Port Data Register

    Example: Write one bit data to output port. B0BSET P4.0 ; Set P4.0 and P5.3 to be “1”. B0BSET P5.3 B0BCLR P4.0 ; Set P4.0 and P5.3 to be “0”. B0BCLR P5.3 Version 0.1 SONiX TECHNOLOGY CO., LTD Page 75...

  • Page 76: Port 4 Adc Share Pin

    Note: For P4.n general purpose I/O function, users should make sure of P4.n’s ADC channel is disabled, or P4.n is automatically set as ADC analog input when GCHS = 1 and CHS[2:0] point to P4.n. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 76...
  • Page 77 ; Set P4.1 output buffer to avoid glitch. B0BSET P4.1 ; Set P4.1 buffer as “1”. ; or B0BCLR P4.1 ; Set P4.1 buffer as “0”. ; Enable P4.1 output mode. B0BSET P4M.1 ; Set P4.1 as input mode. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 77...
  • Page 78 ;If CHS[2:0] don’t point to P4.0 (CHS[2:0] ≠ 000B), don’t care GCHS status. ; Clear P4CON. B0BCLR P4CON.0 ; Enable P4.0 digital function. ; Enable P4.0 input mode. B0BCLR P4M.0 ; Set P4.0 as input mode. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 78...
  • Page 79 ; Set P4.0 output buffer to avoid glitch. B0BSET P4.0 ; Set P4.0 buffer as “1”. ; or B0BCLR P4.0 ; Set P4.0 buffer as “0”. ; Enable P4.0 output mode. B0BSET P4M.0 ; Set P4.0 as input mode. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 79...

  • Page 80: Timers

    Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: A,#5AH ; Clear the watchdog timer. B0MOV WDTR,A … CALL SUB1 CALL SUB2 … … … MAIN Version 0.1 SONiX TECHNOLOGY CO., LTD Page 80...
  • Page 81 ; I/O and RAM are correct. Clear watchdog timer and ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … MAIN Version 0.1 SONiX TECHNOLOGY CO., LTD Page 81...
  • Page 82 SN8P2711A 8-Bit Micro-Controller Version 0.1 SONiX TECHNOLOGY CO., LTD Page 82...

  • Page 83: Timer/Counter 0 (Tc0)

    TC0 Rate TC0R Reload ALOAD0, TC0OUT (Fcpu/2~Fcpu/256) Data Buffer TC0X8 PWM0OUT Fcpu Compare TC0CKS TC0ENB Load Fosc TC0C 8-Bit Binary Up TC0 Time Out Counting Counter TC0 Rate (Fosc/1~Fosc/128) CPUM0,1 INT0 (Schmitter Trigger) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 83...

  • Page 84: Tc0M Mode Register

    0 = Disable TC0 timer. 1 = Enable TC0 timer. Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0). Version 0.1 SONiX TECHNOLOGY CO., LTD Page 84...

  • Page 85: Tc1X8, Tc0X8, Tc0Gn Flags

    0x00~0xFF 00000000b~11111111b Overflow per 256 count (Fosc/1~ 0x00~0x3F xx000000b~xx111111b Overflow per 64 count Fosc/128) 0x00~0x1F xxx00000b~xxx11111b Overflow per 32 count 0x00~0x0F xxxx0000b~xxxx1111b Overflow per 16 count 0x00~0xFF 00000000b~11111111b Overflow per 256 count Version 0.1 SONiX TECHNOLOGY CO., LTD Page 85...
  • Page 86 2 us 62.5 ms 488.281 us Fosc/4 0.256 ms 1 us 31.25 ms 244.141 us Fosc/2 0.128 ms 0.5 us 15.625 ms 122.07 us Fosc/1 0.064 ms 0.25 us 7.813 ms 61.035 us Version 0.1 SONiX TECHNOLOGY CO., LTD Page 86...

  • Page 87: Tc0R Auto-Load Register

    TC0R initial value = N - (TC0 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Version 0.1 SONiX TECHNOLOGY CO., LTD Page 87...

  • Page 88: Tc0 Clock Frequency Output (Buzzer)

    ; Enable TC0 output to P5.4 and disable P5.4 I/O function B0BSET FALOAD1 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer Note: Buzzer output is enable, and “PWM0OUT” must be “0”. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 88...

  • Page 89: Tc0 Timer Operation Sequence

    ; 0~63. B0BSET FALOAD0 ; ALOAD0, TC0OUT = 10, PWM cycle boundary is B0BCLR FTC0OUT ; 0~31. B0BSET FALOAD0 ; ALOAD0, TC0OUT = 11, PWM cycle boundary is B0BSET FTC0OUT ; 0~15. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 89...
  • Page 90 ; Enable TC0 interrupt function. B0BSET FTC0OUT ; Enable TC0OUT (Buzzer) function. B0BSET FPWM0OUT ; Enable PWM function. B0BSET FTC0GN ; Enable TC0 green mode wake-up function. Enable TC0 timer. B0BSET FTC0ENB ; Enable TC0 timer. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 90...

  • Page 91: Timer/Counter 1 (Tc1)

    TC1 Rate TC1R Reload ALOAD1, TC1OUT (Fcpu/2~Fcpu/256) Data Buffer TC1X8 PWM1OUT Fcpu Compare TC1CKS TC1ENB Load Fosc TC1C 8-Bit Binary Up TC1 Time Out Counting Counter TC1 Rate (Fosc/1~Fosc/128) CPUM0,1 INT1 (Schmitter Trigger) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 91...

  • Page 92: Tc1M Mode Register

    0 = TC1 internal clock source is Fcpu. TC1RATE is from Fcpu/2~Fcpu/256. 1 = TC1 internal clock source is Fosc. TC1RATE is from Fosc/1~Fosc/128. Note: Under TC1 event counter mode (TC1CKS=1), TC1X8 bit and TC1RATE are useless. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 92...

  • Page 93: Tc1C Counting Register

    TC1C initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Version 0.1 SONiX TECHNOLOGY CO., LTD Page 93...
  • Page 94 2 us 62.5 ms 488.281 us Fosc/4 0.256 ms 1 us 31.25 ms 244.141 us Fosc/2 0.128 ms 0.5 us 15.625 ms 122.07 us Fosc/1 0.064 ms 0.25 us 7.813 ms 61.035 us Version 0.1 SONiX TECHNOLOGY CO., LTD Page 94...

  • Page 95: Tc1R Auto-Load Register

    TC1R initial value = N - (TC1 interrupt interval time * input clock) = 256 - (10ms * 4MHz / 4 / 64) = 256 - (10 * 4 * 10 / 4 / 64) = 100 = 64H Version 0.1 SONiX TECHNOLOGY CO., LTD Page 95...

  • Page 96: Tc1 Clock Frequency Output (Buzzer)

    ; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer Note: Buzzer output is enable, and “PWM1OUT” must be “0”. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 96...

  • Page 97: Tc1 Timer Operation Sequence

    ; ALOAD1, TC1OUT = 01, PWM cycle boundary is 0~63. B0BSET FTC1OUT B0BSET FALOAD1 ; ALOAD1, TC1OUT = 10, PWM cycle boundary is 0~31. B0BCLR FTC1OUT B0BSET FALOAD1 ; ALOAD1, TC1OUT = 11, PWM cycle boundary is 0~15. B0BSET FTC1OUT Version 0.1 SONiX TECHNOLOGY CO., LTD Page 97...
  • Page 98 Set TC1 timer function mode. B0BSET FTC1IEN ; Enable TC1 interrupt function. B0BSET FTC1OUT ; Enable TC1OUT (Buzzer) function. B0BSET FPWM1OUT ; Enable PWM function. Enable TC1 timer. B0BSET FTC1ENB ; Enable TC1 timer. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 98...

  • Page 99: Pwm Mode

    125K Overflow per 16 count The Output duty of PWM is with different TCnR. Duty range is from 0/256~255/256. …… …… …… …… TCn Clock TCnR=00H High TCnR=01H High TCnR=80H High TCnR=FFH Version 0.1 SONiX TECHNOLOGY CO., LTD Page 99...

  • Page 100: Tcnirq And Pwm Duty

    PWMn Output (Duty Range 0~63) TCn Overflow, TCnIRQ = 1 0xFF TCnC Value 0x00 PWMn Output (Duty Range 0~31) TCn Overflow, TCnIRQ = 1 0xFF TCnC Value 0x00 PWMn Output (Duty Range 0~15) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 100...

  • Page 101: Pwm Duty With Tcnr Changing

    2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 101...

  • Page 102: Pwm Program Example

    TC0R, A INCMS BUF0 ; Get the new TC0R value from the BUF0 buffer defined by ; programming. B0MOV A, BUF0 B0MOV TC0R, A Note: The PWM can work with interrupt request. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 102...

  • Page 103: 5+1 Channel Analog To Digital Converter

    ADC circuit will set EOC bit to “1” and final 12-bits value output in ADB and ADR low-nibble registers. AIN0/P4.0 AIN1/P4.1 AIN2/P4.2 CONVERTER AIN3/P4.3 (ADC) 12-Bits AIN4/P4.4 AIN5 (Internal 1/4 VDD) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 103...

  • Page 104: Adm Register

    Note: If ADENB = 1, users should set P4.n/AINn as input mode without pull-up. System doesn’t set automatically. If P4CON.n is set, the P4.n/AINn’s digital I/O function including pull-up is isolated. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 104...

  • Page 105: Adr Registers

    ADCKS1, ADCKS0: ADC clock source selection. ADCKS1 ADCKS0 ADC Clock Source Fcpu/16 Fcpu/8 Fcpu Fcpu/2 Bit[3:0] ADB[3:0]: ADC low-nibble data buffer of 12-bit ADC resolution. Note: ADC buffer ADR [3:0] initial value after reset is unknown. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 105...

  • Page 106: Adb Registers

    ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 8-bit 9-bit 10-bit 11-bit 12-bit O = Selected, x = Delete Note: ADC buffer ADB initial value after reset is unknown. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 106...

  • Page 107: P4Con Registers

    1 = P4.n is pure analog input, can’t be a digital I/O pin. Note: When Port 4.n is general I/O port not ADC channel, P4CON.n must set to “0” or the Port 4.n digital I/O signal would be isolated. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 107...

  • Page 108: Vrefh Registers

    1 = Disable ADC internal VREFH function, P4.0/AIN0/VREFH pin is external VREFH input pin. Note: If EVHENB = 1, P4.0/AIN0 pin is external VREFH input pin and P4.0 I/O and AIN0 functions are isolated. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 108...

  • Page 109: Adc Converting Time

    1/( ( 4MHz / 16 ) / /4 ) x16= 2048 us Fosc/ 16 Fcpu 1/( ( 4MHz / 16 ) / /4 ) x16= Fcpu/2 1/( ( 4MHz / 16 ) / /4 ) x16= Version 0.1 SONiX TECHNOLOGY CO., LTD Page 109...

  • Page 110: Adc Routine Example

    ; To get AIN0 input data bit11 ~ bit4 B0MOV Adc_Buf_Hi, A B0MOV A, ADR ; To get AIN0 input data bit3 ~ bit0 A, 0FH B0MOV Adc_Buf_Low, A End_ADC: B0BCLR FADENB ; Disable ADC circuit Version 0.1 SONiX TECHNOLOGY CO., LTD Page 110...
  • Page 111 ; To get AIN0 input data bit11 ~ bit4 B0MOV Adc_Buf_Hi, A B0MOV A, ADR ; To get AIN0 input data bit3 ~ bit0 A, 0FH B0MOV Adc_Buf_Low, A B0BCLR FADENB ; Disable ADC circuit ADC_INT_EXIT: RETI Version 0.1 SONiX TECHNOLOGY CO., LTD Page 111...

  • Page 112: Adc Circuit

    Reference High Voltage Input 47uF 0.1uF ADC reference high voltage is from external voltage and AIN0/P4.0 is VERFH input. The capacitor (47uF) between VREFH and VSS is necessary to stable VERFH voltage. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 112...

  • Page 113: Instruction Table

    Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1. 2. If branch condition is true then “S = 1”, otherwise “S = 0”. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 113...

  • Page 114: Electrical Characteristic

    AIN0 ~ AIN5 input voltage Vani Vdd = 5.0V Vrefh1~5 ADC enable time Tast Ready to start convert after set ADENB = “1” Vdd=5.0V ADC current consumption Vdd=3.0V ADC Clock Frequency VDD=5.0V ADCLK Version 0.1 SONiX TECHNOLOGY CO., LTD Page 114...
  • Page 115 Typical Temperature = 25°C. Typical Internal 16MHz Oscillator RC Type Frequency = 16MHz. Testing Temperature Range = –40°C ~ + 90°C 17.50 17.00 16.50 Typ. 25ºC 16.00 15.50 15.00 14.50 14.00 13.50 13.00 Temperature (ºC) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 115...
  • Page 116 Testing Power Voltage Range (VDD) = 3V~5.5V. Testing Machine Cycle Range (Fcpu) = Fhosc/1~Fhosc/16. 16.40 16.30 16.20 3.5V 16.10 Typ. Fcpu=Fhosc/4 4.5V 16.00 15.90 5.5V 15.80 15.70 15.60 15.50 Fhosc/16 Fhosc/4 Fhosc/1 Machine Cycle (Fcpu) Version 0.1 SONiX TECHNOLOGY CO., LTD Page 116...

  • Page 117: Development Tool Version

    OTP programming is controlled by ICE without firmware upgrade suffers. Please refer easy writer user manual for detailed information. In SN8P2711A OTP programming by Easy Writer, the crystal of ICE must be 16MHz. Connect Easy Writer to ICE through a 60-pin cable which shipping with Easy Writer.

  • Page 118: Sn8P2711 Ev Kit

    12.4 SN8P2711 EV KIT 12.4.1 PCB DESCRIPTION SONIX provides SN8P2711 EV Kit Ver. A for function emulation. For Sn8P2711 ICE emulation, the EV kit provides ADC internal reference voltage and LVD 2.4V/3.6V selection circuits. CON1: I/O port and ADC reference input. Connect to SN8ICE 2K CON1.
  • Page 119 P4.0 VREFH R36, P37: R36=300K ohm, R37= 100K ohm. The bias voltage is equal to 1/4 VDD and emulates SN8P2711A internal 1/4 VDD voltage for low battery detector by ADC channel 5. C9~C14: Connect 47uF capacitors to AIN0~AIN5 input which are ADC channel 0~5 bypass capacitors.

  • Page 120: Sn8P2711 Ev Kit Connect To Sn8Ice 2K

    The connection from SN8P2711 EV KIT to SN8ICE 2K is as following. The ADC reference voltage is supplied by SN8P2711 EV KIT. The AVREFH/VDD jump pin of SN8ICE 2K must be removed. Version 0.1 SONiX TECHNOLOGY CO., LTD Page 120...

  • Page 121: Transition Board For Otp Programming

    12.5 TRANSITION BOARD FOR OTP PROGRAMMING 12.5.1 SN8P2711 V3 TRANSITION BOARD SN8P2711 V3 transition board is for SN8P2711A OTP programming including P-DIP 14 pin, SOP 14 pin and SSOP 16 pin sockets connection. JP2: Connect to EZ or EZ_MP writer.

  • Page 122: Sn8P2711 Mp028A Transition Board For Ez/Mpez Writer

    U3: Set SSOP 16 pin socket for SN8P2711AX programming (using SSOP 20 pin socket : TX-SSOP20PIN). 12.5.2 SN8P2711 MP028A TRANSITION BOARD FOR EZ/MPEZ WRITER SN8P2711 MP028A transition board is for EZ and MPEZ writer supported SN8P2711A OTP programming. Version 0.1 SONiX TECHNOLOGY CO., LTD...

  • Page 123: Sn8P2711 Mp028A Connect To Ez_Mp Writer

    SN8P2711A 8-Bit Micro-Controller 12.5.3 SN8P2711 MP028A CONNECT TO EZ_MP WRITER 12.5.4 SN8P2711 MP028A CONNECT TO EZ WRITER Version 0.1 SONiX TECHNOLOGY CO., LTD Page 123...

  • Page 124: Sn8P2711 V3 Connect To Ez Writer

    SN8P2711A 8-Bit Micro-Controller 12.5.5 SN8P2711 V3 CONNECT TO EZ WRITER 12.5.6 SN8P2711 V3 CONNECT TO EZ_MP WRITER Version 0.1 SONiX TECHNOLOGY CO., LTD Page 124...

  • Page 125: Otp Programming Pin

    JP2 for Writer V3.0 transition board DIP14 DIP35 DIP15 DIP34 DIP16 DIP33 DIP17 DIP32 DIP18 DIP31 DIP19 DIP30 DIP20 DIP29 DIP21 DIP28 DIP22 DIP27 DIP23 DIP26 DIP24 DIP25 JP3 for MP transition board Version 0.1 SONiX TECHNOLOGY CO., LTD Page 125...

  • Page 126: Programming Pin Mapping

    SN8P2711A 8-Bit Micro-Controller 12.6.2 PROGRAMMING PIN MAPPING: Programming Information of SN8P2711A Series Chip Name SN8P2711AP,S SN8P2711AX EZ Writer OTP IC / JP3 Pin Assigment Connector Number Name Number Number P4.0 P4.0 P4.4 P4.4 P4.1 P4.1 ALSB/PDB P0.2 P0.2 Note:Use M2IDE V1.06 (or after version) to simulation.

  • Page 127: Package Information

    0.775 18.669 1.905 19.685 0.300 7.62 0.245 0.250 0.255 6.223 6.35 6.477 0.115 0.130 0.150 2.921 3.302 3.810 ｅ 0.335 0.355 0.375 8.509 9.017 9.525 θ° 0° 7° 15° 0° 7° 15° Version 0.1 SONiX TECHNOLOGY CO., LTD Page 127...

  • Page 128: Sop 14 Pin

    0.2490 0.336 0.341 0.344 8.5344 8.6614 8.7376 0.150 0.154 0.157 3.81 3.9116 3.9878 0.050 1.27 0.228 0.236 0.244 5.7912 5.9944 6.1976 0.015 0.025 0.050 0.381 0.635 1.27 θ° 0° 8° 0° 8° Version 0.1 SONiX TECHNOLOGY CO., LTD Page 128...

  • Page 129: Ssop 16 Pin

    0.010 0.1778 0.254 0.007 0.009 0.1778 0.2286 0.189 0.197 4.8006 5.0038 0.150 0.157 3.81 3.9878 0.228 0.244 5.7912 6.1976 0.016 0.050 0.4064 1.27 0.025 BASIC 0.635 BASIC θ° 0° 8° 0° 8° Version 0.1 SONiX TECHNOLOGY CO., LTD Page 129...

  • Page 130: Marking Definition

    Marking Definition 14.1 INTRODUCTION There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit MCU for order or obtain information. This definition is only for Blank OTP MCU. 14.2 MARKING INDETIFICATION SYSTEM SN8 X PART No.

  • Page 131: Marking Example

    ..9=09 A=10 B=11 ..1=January Month 2=February ..9=September A=October B=November C=December 03= 2003 Year 04= 2004 05= 2005 06= 2006 ..Version 0.1 SONiX TECHNOLOGY CO., LTD Page 131...
  • Page 132 SONIX product could create a situation where personal injury or death may occur.

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