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LPC84x User manual

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Page 1 UM11029 LPC84x User manual Rev. 1.0 — 16 June 2017 User manual Document information Info Content LPC84x, LPC84x UM, LPC84x user manual Keywords LPC84x User manual Abstract...
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For sales office addresses, please send an email to: salesaddresses@nxp.com UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 2 of 515...
Page 3: Chapter 1: Lpc84X Introductory Information
1.1 Introduction The LPC84x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and 16 KB of SRAM. The peripheral complement of the LPC84x includes a CRC engine, four I...
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Chapter 1: LPC84x Introductory information – On-chip ROM APIs for integer divide. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 4 of 515...
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Cs support data rates up to 400 kbit/s on standard digital pins. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 5 of 515...
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• Available in LQFP64, LQFP48, HVQFN48, and HVQFN33 packages UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 6 of 515...
Page 7: Ordering Options
The core includes a single-cycle multiplier and a system tick timer (SysTick). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
Page 8: Block Diagram
Note: Yellow shaded blocks support general purpose DMA Fig 1. LPC84x block diagram aaa-022793 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 8 of 515...
Page 9: Chapter 2: Lpc84X Memory Mapping
Rev. 1.0 — 16 June 2017 User manual 2.1 How to read this chapter The memory mapping is identical for all LPC84x parts. Different LPC84x parts support different flash and SRAM memory sizes. 2.2 General description The LPC84x incorporates several distinct memory regions.
Page 10: Table Of Contents
0x4000 0000 aaa-027479 Fig 2. LPC84x Memory mapping 2.2.2 Micro Trace Buffer (MTB) The LPC84x supports the ARM Cortex-M0+ Micro Trace Buffer. See Section 31.5.4. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Page 11: Chapter 3: Lpc84X Boot Process
PIO0_22 is SPI0 SSEL0 PIO0_26 is SPI0 MISO PIO0_27 is SPI0 MOSI UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 11 of 515...
Page 12: General Description
USART, I2C slave, or SPI slave bus. The LPC84x device must be connected to a host system that provides the UART, I C or SPI master connections.
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Ptr to Function n aaa-026624 Fig 3. Boot ROM structure UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 13 of 515...
Page 14: Functional Description
512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 14 of 515...
Page 15: Boot Process
Fig 4. Boot process flowchart UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 15 of 515...
Page 16: How To Read This Chapter
The functions of FAIM bits are described in the following tables. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 16 of 515...
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ISP clock pin select (SPI SCK) PIOnPIOn_0 PIOn_1 0x1F PIOn_31 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 17 of 515...
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Pull-down Pull-up Repeater PIO1_14. See description of bits 1:0. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 18 of 515...
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PIO0_17. See description of bits 1:0. 31:30 PIO0_16. See description of bits 1:0. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 19 of 515...
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PIO0_1. See description of bits 1:0. 31:30 PIO0_0. See description of bits 1:0. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 20 of 515...
Page 21: How To Read This Chapter
User manual 5.1 How to read this chapter All LPC84x devices include ROM-based services for programming and reading the flash memory in addition to other functions. In-System Programming works on an unprogrammed or previously programmed device using one from a selection of hardware interfaces.
Page 22: Flash Content Protection Mechanism
Chapter 5: LPC84x ISP and IAP 5.3.3 Flash content protection mechanism The LPC84x is equipped with the Error Correction Code (ECC) capable Flash memory. The purpose of an error correction module is twofold. Firstly, it decodes data words read from the memory into output data words. Secondly, it encodes data words to be written to the memory.
Page 23: Code Read Protection (Crp)
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 13. LPC82x flash configuration <tbd> Sector Sector Page number Address range 16 KB 32 KB number size [KB] flash flash 96 - 111 0x0000 1800 - 0x0000 1BFF 112 - 127...
Page 24: Isp Entry Protection
5.3.6.2 ISP entry configuration and detection The LPC84x UART/I2C/SPI ISP mode allows programming and reprogramming of the internal FLASH via a set of commands on the UART, I2C slave, or SPI slave buses. Two bits of the FAIM flash are used for ISP mode selection.
Page 25: Isp Interrupt And Sram Use
If FAIM content is invalid, the default ISP selection is USART/I2C/SPI or auto detection mode. In auto detection mode, the LPC84x enables all three interfaces on the fixed GPIO port and pins, and selects the first one that has either a successful auto baud detection on USART or a valid probe message response on I2C or SPI.
Page 26: Usart Isp Communication Protocol
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.4 USART ISP communication protocol All USART ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR>...
Page 27: Usart Isp Commands
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.5 USART ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
Page 28: Unlock
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 16. ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 (no entry in ISP mode allowed) Erase sector(s) yes; sector 0 can only be erased when all yes;...
Page 29: Echo
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.5.3 Echo Table 19. USART ISP Echo command Command Input Setting: ON = 1 | OFF = 0 Return Code CMD_SUCCESS | PARAM_ERROR Description The default setting for echo command is ON. When ON the ISP command handler sends the received serial data back to the host.
Page 30: Prepare Sectors For Write Operation
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.5.6 Prepare sectors for write operation This command makes flash write/erase operation a two-step process. Table 22. USART ISP Prepare sectors for write operation command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 23. USART ISP Copy command Command Input Flash Address(DST): Destination flash address where data bytes are to be written. The destination address should be a 64 byte boundary. RAM Address(SRC): Source RAM address from where data bytes are to be read.
Page 32: Erase Sectors
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.5.9 Erase sectors Table 25. USART ISP Erase sector command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number. Return Code CMD_SUCCESS |...
Page 33: Read Part Identification Number
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.5.12 Read Part Identification number Table 28. USART ISP Read Part Identification command Command Input None. Return Code CMD_SUCCESS followed by part identification number (see Table 29). Description This command is used to read the part identification number.
Page 34: Readuid
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.5.15 ReadUID Table 32. USART ReadUID command Command Input None Return Code CMD_SUCCESS followed by four 32-bit words of a unique serial number in ASCII format. The word sent at the lowest address is sent first.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 34. USART ISP Read flash signature command Command Input Start address: Start of flash address. Default = 0. Must be 0 when CRP1 is enabled. End address: End of flash address.
Page 36: Read/Write Faim Page
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.5.18 Read/write FAIM page This command is used to read/write FAIM page. Table 35. USART ISP Read/Write FAIM Page command Command Input FAIM access: 0 = FAIM Page read 1 = FAIM Page write...
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 36. ISP/IAP Error codes Return Error code Description Code ADDR_NOT_MAPPED Address is not mapped in the memory map. Count value is taken into consideration where applicable. CMD_LOCKED Command is locked.
Page 38: Iap Commands
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.6 IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. The result of the IAP command is returned in the result table pointed to by register r1. The user can reuse the command table for result by passing the same pointer in registers r0 and r1.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP The flash memory is not accessible during a write or erase operation. IAP commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution.
Page 40: Prepare Sector(S) For Write Operation
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.6.1 Prepare sector(s) for write operation This command makes flash write/erase operation a two step process. Table 38. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation...
Page 41: Erase Sector(S)
UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.6.3 Erase Sector(s) Table 40. IAP Erase Sector(s) command Command Erase Sector(s) Input Command code: 52 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.6.6 Read Boot code version number Table 43. IAP Read Boot Code version number command Command Read boot code version number Input Command code: 55 (decimal) Parameters: None Status code CMD_SUCCESS Result Result0: 2 bytes of boot code version number.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.6.9 ReadUID Table 46. IAP ReadUID command Command Compare Input Command code: 58 (decimal) Status code CMD_SUCCESS Result Result0: The first 32-bit word (at the lowest address). Result1: The second 32-bit word.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.6.12 Read FAIM Page Table 49. IAP Read FAIM page command Command Read FAIM page Input Command code: 80 (decimal) Param0: FAIM page number. Param1: Memory address to store the value read from FAIM.
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Once the host interface sends the first probe command via I2C or SPI interface, and it is accepted by the LPC84x, then the interface is detected, the ISP pin switches to an output high as ISP_IRQ.
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Typical host system and LPC84x transaction 5.7.3 I2C ISP mode transaction protocol The LPC84x will respond to a host system on I2C addresses 0x18, 0x1C, 0x30, and 0x38. The host system’s I2C master clock rate can be as high as 1MHz. The LPC84x may extend the I2C clock to delay the I2C master if it needs more time to perform an operation.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.7.5 I2C/SPI operations allowed for CRP systems If CRP is enabled (CRP1, CRP2, or CRP3) then the I2C/SPI commands may be limited in functionality. See Table 51 for limitations of I2C/SPI ISP commands when CRP is enabled.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.8 I2C/SPI ISP mode commands, data, and responses All of the supported commands, associated structures and data formats for those commands, and responses are explained in this section Table 52. I2C/SPI ISP command summary...
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP 5.8.2 SH_CMD_RESET (0xA2) command This command can be used to reset the LPC84x. This command has no response. Table 55. Command packet Field Offset Size (bytes) Value Description command 0xA2 'Reset' command identifier 5.8.3 SH_CMD_BOOT (0xA3) command...
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‘Re-invoke ISP’ IAP command will be active for the optional probe command. The host system should repeatedly send the probe command to the LCP84x via one of the supported interfaces until the LPC84x asserts the ISP1_IRQ pin LOW. Table 60.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 63. Command packet Field Offset Size (bytes) Value Description command 0xA6 ‘Write block’ command identifier crcCheck 0 – Do CRC check for this packet 1 - Ignore CRC field for this packet blockNum Flash block number in which the appended data to be programmed.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 68. Response packet (error) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xA7 Processed command identifier length Length of the response packet. 0x4 = failure errorCode Error code Error code specified in error.h...
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 74. Response packet (error) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xA9 Processed command identifier length Length of the response packet. 0x4 = failure errorCode Error code Error code specified in error.h parameters...
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The write sub-block command is used for queuing data for a full flash block write. It is used when the host system cannot send the entire data block to the LPC84x in a single I2C transfer using the ‘Write block’ command. When using this command, multiple sub-blocks are sent to the LPC84x in sequential order for the block.
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The read sub-block command is used for reading partial data from a full flash block write. It is used when the host system cannot receive the entire data block to the LPC84x in a single I2C transfer using the ‘Read block’ command.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 87. Command packet Field Offset Size (bytes) Value Description command 0xAE ‘Bulk erase’ command identifier reserved startSec Starting sector number to erase endsec End sector number to erase Table 88.
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 92. Response packet (error) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xB0 Processed command identifier length Length of the response packet. 0x4 = failure errorCode Error code Error code specified in error.h parameters...
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP Table 97. Response packet (error) Field Offset Size (bytes) Value Description 0x55 Start of packet identifier command 0xBE Processed command identifier length Length of the response packet. 0x4 = failure errorCode Error code Error code specified in error.h...
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP #define SH_CMD_CHECK_IMAGE 0xA4 #define SH_CMD_PROBE 0xA5 #define SH_CMD_WRITE_BLOCK 0xA6 #define SH_CMD_READ_BLOCK 0xA7 #define SH_CMD_SECTOR_ERASE 0xA8 #define SH_CMD_PAGE_ERASE 0xA9 #define SH_CMD_PAGE_WRITE 0xAA #define SH_CMD_PAGE_READ 0xAB #define SH_CMD_WRITE_SUBBLOCK 0xAC #define SH_CMD_READ_SUBBLOCK 0xAD #define SH_CMD_BULK_ERASE 0xAE...
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UM11029 NXP Semiconductors Chapter 5: LPC84x ISP and IAP typedef struct { uint8_t cmd; /*!< Command ID */ uint8_t reserved; /*!< Should be zero. */ uint16_t sec_nr; /*!< Sector number.*/ } CmdEraseSectorParam_t; /** Structure describing Bulk erase command packet format. */ typedef struct { uint8_t cmd;...
Page 61: X4008
Chapter 6: LPC84x Flash signature generator Rev. 1.0 — 16 June 2017 User manual 6.1 How to read this chapter The flash signature generator is identical on all LPC84x parts. 6.2 Features • Controls flash access time. Provides registers for flash signature generation.
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 62 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 63 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 64 of 515...
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= f_Q[address][31] XOR sign[0] XOR sign[10] XOR sign[30] XOR sign[31] sign = nextSign signature32 = sign UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 65 of 515...
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(NVIC) Rev. 1.0 — 16 June 2017 User manual 7.1 How to read this chapter The NVIC is identical on all LPC84x parts. 7.2 Features Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+. • Tightly coupled interrupt controller provides low interrupt latency.
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 108. Connection of interrupt sources to the NVIC Interrupt Name Description Flags number UART0_IRQ USART0 interrupt Table 326 “USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C (USART0),...
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 108. Connection of interrupt sources to the NVIC Interrupt Name Description Flags number PININT0_IRQ Pin interrupt 0 or pattern PSTAT - pin interrupt status match engine slice 0...
Page 69: X1000
UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) 7.4 Register description The NVIC registers are located on the ARM private peripheral bus. Table 109. Register overview: NVIC (base address 0xE000 E000) Name Access Address Description Reset Reference...
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) 7.4.1 Interrupt Set Enable Register 0 register The ISER0 register allows to enable peripheral interrupts or to read the enabled state of those interrupts. Disable interrupts through the ICER0 (Section 7.4.2).
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) 7.4.2 Interrupt clear enable register 0 The ICER0 register allows disabling the peripheral interrupts, or for reading the enabled state of those interrupts. Enable interrupts through the ISER0 registers (Section 7.4.1).
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 111. Interrupt clear enable register 0 (ICER0, address 0xE000 E180) …continued Symbol Description Reset value ICE_PININT5 or Interrupt disable for both pinint5 and ICE_DAC1 DAC1. ICE_PININT6 or Interrupt disable for both pinint6 and ICE_USART3 USART3.
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 112. Interrupt set pending register 0 register (ISPR0, address 0xE000 E200) bit description …continued Symbol Description Reset value ISP_PININT0 Interrupt pending set. ISP_PININT1 Interrupt pending set. ISP_PININT2 Interrupt pending set.
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 113. Interrupt clear pending register 0 register (ICPR0, address 0xE000 E280) bit description …continued Symbol Function Reset value ICP_ADC_OVR Interrupt pending clear. ICP_SDMA Interrupt pending clear. ICP_I2C2 Interrupt pending clear.
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 114. Interrupt Active Bit Register 0 (IABR0, address 0xE000 E300) bit description …continued Symbol Function Reset value IAB_WKT Interrupt active. IAB_ADC_SEQA Interrupt active. IAB_ADC_SEQB Interrupt active. IAB_ADC_THCMP Interrupt active.
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 116. Interrupt Priority Register 1 (IPR1, address 0xE000 E404) bit description Symbol Description 15:14 IP_UART2 Interrupt Priority. 0 = highest priority. 3 = lowest priority. 21:16 - These bits ignore writes, and read as 0.
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 119. Interrupt Priority Register 4 (IPR4, address 0xE000 E410) bit description Symbol Description These bits ignore writes, and read as 0. IP_ADC_SEQA Interrupt Priority. 0 = highest priority. 3 = lowest priority.
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UM11029 NXP Semiconductors Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) Table 122. Interrupt Priority Register 7 (IPR7, address 0xE000 E41C) bit description Symbol Description These bits ignore writes, and read as 0. IP_PININT4 Interrupt Priority. 0 = highest priority. 3 = lowest priority.
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Chapter 8: LPC84x System configuration (SYSCON) Rev. 1.0 — 16 June 2017 User manual 8.1 How to read this chapter The system configuration block is identical for all LPC84x parts. 8.2 Features • Clock control – Configure the system PLL.
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PDRUNCFG register: Section 8.6.47 “Power configuration register” 2. Select the fro_oscout (30 MHz/24 MHz/18 MHz) using the set_fro_frequency API call: Chapter 9 “LPC84x FRO API ROM routine” Figure 9 “UM11029 clock generation (continued)”. 3. The FROOSCCTRL register can be used to select direct fro_oscout or divided fro_oscout for fro clock.
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Section 8.6.22 “System clock control 1 register” 8.3.4 Set up the system oscillator using XTALIN and XTALOUT To use the system oscillator with the LPC84x, assign the XTALIN and XTALOUT pins, which connect to the external crystal, through the fixed-pin function in the switch matrix.
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Remark: The main clock frequency is limited to 100 MHz. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 82 of 515...
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: synchronized multiplexer, see register desriptions for details. aaa-027480 Fig 7. LPC84x clock generation UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 83 of 515...
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FRO oscillator aaa-026591 Fig 8. UM11029 clock generation (continued) UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 84 of 515...
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Section 8.6.2 “System PLL control register” Section 8.6.5 “Watchdog oscillator control register” UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 85 of 515...
Page 86: X0001
SYSPLLCLKUEN 0x044 System PLL clock source update enable 8.6.10 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 86 of 515...
Page 87: X4003
FRG1CLKSEL 0x0E8 FRG1 clock source select 8.6.31 0x0EC Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 87 of 515...
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Start logic 1 interrupt wake-up enable register 0 8.6.44 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 88 of 515...
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Remark: The divider values for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 89 of 515...
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15 - 25 MHz frequency range 31:2 Reserved 0x00 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 90 of 515...
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4.2 MHz 4.4 MHz 4.6 MHz 31:9 Reserved 0x00 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 91 of 515...
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Enable FRO clock source update. No change Update clock source 31:1 Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 92 of 515...
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System PLL clock source External clock Watchdog oscillator FRO DIV 31:2 Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 93 of 515...
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Enable main clock source update. No change Update clock source 31:1 Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 94 of 515...
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1: Divide by 1. … 255: Divide by 255. 31:8 Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 95 of 515...
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SCT module. The SCT clock can be shut down completely by setting the DIV field to zero. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 96 of 515...
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Disable Enable I2C0 Enables clock for I2C0. Disable Enable UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 97 of 515...
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Enable IOCON Enables clock for IOCON block. Disable Enable UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 98 of 515...
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Disable Enable UART3 Enable clock for UART3 Disable Enable UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 99 of 515...
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SCT reset control Assert the SCT reset. Clear the SCT reset. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 100 of 515...
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Assert the I C2 reset. Clear the I C2 reset. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 101 of 515...
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Assert the DAC1 reset. Clear the DAC1 reset. Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 102 of 515...
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Assert the FRG1 reset. Clear the FRG1 reset. 31:5 Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 103 of 515...
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FRG0CLK. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 104 of 515...
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Section 17.3.1 “Configure the USART clock and baud rate”. Section 17.7.1 “Clocking and baud rates”. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 105 of 515...
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Section 17.3.1 “Configure the USART clock and baud rate”. Section 17.7.1 “Clocking and baud rates”. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 106 of 515...
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The FRG1CLKSEL register selects the frg1_src clock, which can be the FRO, main clock, or sys_pll. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 107 of 515...
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1: Divide by 1. … 255: Divide by 255. 31:8 Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 108 of 515...
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(IOCONFILTR_PCLK) to the IOCON programmable glitch filter. The clocks can be shut down by setting the DIV bits to 0x0. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 109 of 515...
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Both the BOD interrupt and the BOD reset, depending on the value of bit BODRSTENA in this register, can wake-up the chip from sleep, deep-sleep, and power-down modes. See the LPC84x data sheet for the BOD reset and interrupt levels. Table 163. BOD control register (BODCTRL, address 0x4004 8150) bit description...
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Non-Maskable and a normal interrupt. This can be avoided by disabling the normal interrupt in the NVIC. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 111 of 515...
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Enabled PINT2 GPIO pin interrupt 2 wake-up Disabled Enabled UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 112 of 515...
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USART0 interrupt wake-up. Configure USART in synchronous slave mode. Disabled Enabled UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 113 of 515...
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USART3 interrupt wake-up Disabled Enabled USART4 USART4 interrupt wake-up Disabled Enabled UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 114 of 515...
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Powered down FLASH_PD Flash wake-up configuration Powered Powered down UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 115 of 515...
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FRO. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 116 of 515...
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Reserved. Always write these bits as 0b011 0b011 DAC0 DAC0 power down Powered Powered down UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 117 of 515...
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NVIC or issues a reset, depending on the value of the BODRSTENA bit in the BOD control register (Table 163). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 118 of 515...
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If the BOD reset is enabled, the forced BOD reset can wake up the chip from Deep-sleep or Power-down mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 119 of 515...
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UM11029 NXP Semiconductors Chapter 8: LPC84x System configuration (SYSCON) 8.7.3 System PLL functional description The LPC84x uses the system PLL to create the clocks for the core and peripherals. fro_osc_clk sys_osc_clk FCLKIN FCLKOUT FCCO CLKIN SYSPLLCLKSEL LOCK LOCK DETECT analog section MSEL <...
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System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see Section 8.6.2). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 121 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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UM11029 Chapter 9: LPC84x FRO API ROM routine Rev. 1.0 — 16 June 2017 User manual 9.1 How to read this chapter The ROM-based set fro_oscout API call is available on all parts. 9.2 Features • Select desired on-chip fro_oscout (30 MHz/24 MHz/18 MHz) 9.3 General description...
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UM11029 NXP Semiconductors Chapter 9: LPC84x FRO API ROM routine Ptr to IAP IAP calls 0x0F001FF1 Ptr to ROM Driver table 0x0F001FF8 ROM Driver Table +0x0 Reserved +0x4 Reserved +0x8 Device API 1 set_fro_frequency FRO API function table +0xC Reserved...
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UM11029 NXP Semiconductors Chapter 9: LPC84x FRO API ROM routine 9.4 API description The FRO API provides a function to configure the fro_oscout. The FRO API can be called in the application code through a simple API call. An example is provided with the code bundle software package on nxp.com.
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Chapter 10: LPC84x Switch matrix (SWM) Rev. 1.0 — 16 June 2017 User manual 10.1 How to read this chapter The switch matrix is identical for all LPC84x parts. 10.2 Features • Flexible assignment of digital peripheral functions to pins Enable/disable of analog functions •...
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Table 178 or in the data sheet. 2. Use the LPC84x data sheet to decide which pin x on the LPC84x package to connect the pin function to. 3. Use the pin description table to find the default GPIO function PIO0_n or PIO1_(n-32) assigned to package pin x.
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The switch matrix enables functions that can only be assigned to one pin. Examples are analog inputs, all GPIO pins, and the debug SWD pins. If you want to assign a GPIO pin to a pin on any LPC84x package, disable any special •...
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PERIPHERAL Fig 13. Functional diagram of the switch matrix UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 129 of 515...
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Table 183 SPI0_SCK Serial clock for SPI0. PINASSIGN3 Table 183 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 130 of 515...
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Table 193 T0_MAT2 Timer Match channel 2 PINASSIGN13 Table 193 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 131 of 515...
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– If a fixed-pin analog function is selected, its assigned pin cannot be used for any other function. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 132 of 515...
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0xFFFF FFFF Table 192 functions UART3_RXD, UART3_SCLK, UART4_TXD, UART4_RXD. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 133 of 515...
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PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (= 0x20) to PIO1_21(= 0x35). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 134 of 515...
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PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (= 0x20) to PIO1_21(= 0x35). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 135 of 515...
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PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (= 0x20) to PIO1_21(= 0x35). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 136 of 515...
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PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (= 0x20) to PIO1_21(= 0x35). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 137 of 515...
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PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (= 0x20) to PIO1_21(= 0x35). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 138 of 515...
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PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (= 0x20) to PIO1_21(= 0x35). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 139 of 515...
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PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (= 0x20) to PIO1_21(= 0x35). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 140 of 515...
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ACMP_I1 function select. ACMP_I1 enabled on pin PIO0_00. ACMP_I1 disabled. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 141 of 515...
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I2C0_SCL function select. I2C0_SCL enabled on pin PIO0_10. I2C0_SCL disabled. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 142 of 515...
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DACOUT0 function select. DACOUT0 enabled on pin PIO0_17. DACOUT0 disabled. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 143 of 515...
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Remark: In analog mode, the internal pull-up must be disabled via the IOCON register UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Rev. 1.0 — 16 June 2017 User manual 11.1 How to read this chapter The IOCON block is identical for all LPC84x parts. Registers for pins that are not available on a specific package are reserved. Table 196. Pinout summary...
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The MODE bit in the IOCON register allows enabling or disabling an on-chip pull-up resistor for each pin. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 146 of 515...
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Input pulses of one filter clock cycle longer may also be rejected: T ´ (S_MODE + 1) pulse PCLKn UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 147 of 515...
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I/O configuration for pin PIO0_8/XTALIN FAIM value dependent Table 212 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 148 of 515...
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I/O configuration for pin PIO0_30/ACMP_I5 FAIM value dependent Table 248 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 149 of 515...
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Table 248 PIO0_31 0x08C Table 232 PIO1_0 0x090 Table 233 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 150 of 515...
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Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. Hysteresis. Disable. Enable. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 151 of 515...
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Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 152 of 515...
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Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 153 of 515...
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Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 154 of 515...
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Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 155 of 515...
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Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 156 of 515...
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Inactive (no pull-down/pull-up resistor enabled). Pull-down resistor enabled. Pull-up resistor enabled. Repeater mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 157 of 515...
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Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 158 of 515...
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Standard GPIO functionality. Requires external pull-up for GPIO output function. Fast-mode Plus I2C Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 159 of 515...
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Open-drain mode enabled. Remark: This is not a true open-drain mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 160 of 515...
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Open-drain mode enabled. Remark: This is not a true open-drain mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 161 of 515...
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Open-drain mode enabled. Remark: This is not a true open-drain mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 162 of 515...
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1 clock cycle. Input pulses shorter than one filter clock are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 165 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 166 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 167 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 168 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 169 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 170 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 171 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 172 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 173 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 174 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 175 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 176 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 177 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 178 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 179 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 180 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 181 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 182 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 183 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 184 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 185 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 186 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 187 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 188 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 189 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 190 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 191 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 192 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 193 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 194 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 195 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 196 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 197 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 198 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 199 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 200 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 201 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 202 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 203 of 515...
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3 clock cycles. Input pulses shorter than three filter clocks are rejected. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 204 of 515...
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IOCONCLKDIV0. IOCONCLKDIV1. IOCONCLKDIV2. IOCONCLKDIV3. IOCONCLKDIV4. IOCONCLKDIV5. IOCONCLKDIV6. 31:16 Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 205 of 515...
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UM11029 Chapter 12: LPC84x General Purpose I/O (GPIO) Rev. 1.0 — 16 June 2017 User manual 12.1 How to read this chapter All GPIO registers refer to 32 pins on each port. Depending on the package type, not all pins are available, and the corresponding bits in the GPIO registers are reserved.
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UM11029 NXP Semiconductors Chapter 12: LPC84x General Purpose I/O (GPIO) Table 254. Register overview: GPIO port (base address 0xA000 0000) Name Access Address Description Reset Width Reference offset value B0 to B31 0x0000 to 0x001F Byte pin registers port 0...
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UM11029 NXP Semiconductors Chapter 12: LPC84x General Purpose I/O (GPIO) Table 255. GPIO port byte pin registers (B[0:53], addresses 0xA000 0000 (B0) to 0xA000 0035 (B53)) bit description Symbol Description Reset Access value PBYTE Read: state of the pin PIO0m_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0.
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UM11029 NXP Semiconductors Chapter 12: LPC84x General Purpose I/O (GPIO) 12.5.4 GPIO port mask registers These registers affect writing and reading the MPORT registers. Zeroes in these registers enable reading and writing; ones disable writing and result in zeros in corresponding positions when reading.
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UM11029 NXP Semiconductors Chapter 12: LPC84x General Purpose I/O (GPIO) 12.5.7 GPIO port set registers Output bits can be set by writing ones to these registers, regardless of MASK registers. Reading from these register returns the port’s output bits, regardless of pin directions.
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UM11029 NXP Semiconductors Chapter 12: LPC84x General Purpose I/O (GPIO) 12.5.10 GPIO port direction set registers Direction bits can be set by writing ones to these registers. Table 264. GPIO port direction set register (DIRSET[0:1], address 0xA000 2380 (DIRSET0) to...
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UM11029 NXP Semiconductors Chapter 12: LPC84x General Purpose I/O (GPIO) The state of multiple pins in a port can be read as a byte, halfword, or word from a • PORT register. The state of a selected subset of the pins in a port can be read from a Masked Port •...
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UM11029 NXP Semiconductors Chapter 12: LPC84x General Purpose I/O (GPIO) More efficiently, software can dedicate a semaphore to the MASK registers, and set/capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers, and release the semaphore after the last operation that uses the MPORT or MASK registers.
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Chapter 13: LPC84x Pin interrupts/pattern match engine Rev. 1.0 — 16 June 2017 User manual 13.1 How to read this chapter The pin interrupt generator and the pattern match engine are available on all LPC84x parts. 13.2 Features • Pin interrupts –...
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Follow these steps to configure pins as pin interrupts: 1. Determine the pins that serve as pin interrupts on the LPC84x package. See the data sheet for determining the GPIO port pin number associated with the package pin. 2. For each pin interrupt, program the GPIO port pin number into one of the eight PINTSEL registers in the SYSCON block.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine 13.5.1 Pin interrupts From all available GPIO pins, up to eight pins can be selected in the system control block to serve as external interrupt pins (see Table 167). The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine to IN7 slice n - 1 from slice n -1 (tied HIGH for slice 0) to IN0 slice n - 1 SYSCON slice n endpoint configured? PMCFG bit n = 1...
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine The detect logic of each slice can detect the following events on the selected input: Edge with memory (sticky): A rising edge, a falling edge, or a rising or falling edge that •...
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine The pattern match logic continuously monitors the eight inputs and generates interrupts when any one or more minterms (product terms) of the specified boolean expression is matched. A separate interrupt request is generated for each individual minterm.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine The ORed result of all three minterms asserts the RXEV request to the CPU and the • GPIO_INT_BMAT output. That is, if any of the three minterms are true, the output is asserted.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine 13.6.2 Pin interrupt level or rising edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 8.6.42), one bit in the IENR register enables the interrupt depending on the pin interrupt mode configured in the ISEL register: •...
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 272. Pin interrupt level or rising edge interrupt clear register (CIENR, address 0xA000 400C) bit description Symbol Description Reset Access value CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 274. Pin interrupt active level or falling edge interrupt set register (SIENF, address 0xA000 4014) bit description Symbol Description Reset Access value SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine 13.6.9 Pin interrupt falling edge register This register contains ones for pin interrupts selected in the PINTSELn registers (see Section 8.6.42) on which a falling edge has been detected. Writing ones to this register clears falling edge detection.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Remark: Set up the pattern-match configuration in the PMSRC and PMCFG registers before writing to this register to enable (or re-enable) the pattern-match functionality. This eliminates the possibility of spurious interrupts as the feature is being enabled.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 280. Pattern match bit-slice source register (PMSRC, address 0xA000 402C) bit description Symbol Value Description Reset value 10:8 SRC0 Selects the input source for bit slice 0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 280. Pattern match bit-slice source register (PMSRC, address 0xA000 402C) bit description Symbol Value Description Reset value 16:14 SRC2 Selects the input source for bit slice 2 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 280. Pattern match bit-slice source register (PMSRC, address 0xA000 402C) bit description Symbol Value Description Reset value 22:20 SRC4 Selects the input source for bit slice 4 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 280. Pattern match bit-slice source register (PMSRC, address 0xA000 402C) bit description Symbol Value Description Reset value 28:26 SRC6 Selects the input source for bit slice 6 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Sticky: A rising edge, a falling edge, or a rising or falling edge that is detected at any • time after the edge-detection mechanism has been cleared. The input qualifies as detected (the detect logic output remains HIGH) until the pattern match engine detect logic is cleared again.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 281. Pattern match bit slice configuration register (PMCFG, address 0xA000 4030) bit description …continued Symbol Value Description Reset value PROD_EN Determines whether slice 5 is an endpoint. DPTS5 No effect. Slice 5 is not an endpoint.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 281. Pattern match bit slice configuration register (PMCFG, address 0xA000 4030) bit description …continued Symbol Value Description Reset value 13:11 CFG1 Specifies the match contribution condition for bit slice 1.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 281. Pattern match bit slice configuration register (PMCFG, address 0xA000 4030) bit description …continued Symbol Value Description Reset value 19:17 CFG3 Specifies the match contribution condition for bit slice 3.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 281. Pattern match bit slice configuration register (PMCFG, address 0xA000 4030) bit description …continued Symbol Value Description Reset value 25:23 CFG5 Specifies the match contribution condition for bit slice 5.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine Table 281. Pattern match bit slice configuration register (PMCFG, address 0xA000 4030) bit description …continued Symbol Value Description Reset value 31:29 CFG7 Specifies the match contribution condition for bit slice 7.
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine 13.7.2 Pattern Match engine example Suppose the desired boolean pattern to be matched is: (IN1) + (IN1 * IN2) + (~IN2 * ~IN3 * IN6fe) + (IN5 * IN7ev) with:...
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine – Bit0: Setting this bit will select pattern matches to generate the pin interrupts in place of the normal pin interrupt mechanism. For this example, pin interrupt 0 will be asserted when a match is detected on the first product term (which, in this case, is just a high level on input 1).
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UM11029 NXP Semiconductors Chapter 13: LPC84x Pin interrupts/pattern match engine system clock slice 0 (IN0) SRC0 = 0, CFG0 = 0x4, PROD_ENPTS0 = 0x0 (high level detection) slice 1 (IN1ev) minterm (IN0)(IN1ev) pin interrupt raised on rising edge of IN1 during...
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UM11029 Chapter 14: LPC84x Input multiplexing and DMA trigger multiplexing (INPUT MUX, DMA TRIGMUX) Rev. 1.0 — 16 June 2017 User manual 14.1 How to read this chapter SCT input multiplexing and DMA input multiplexing is available for all parts.
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UM11029 NXP Semiconductors Chapter 14: LPC84x Input multiplexing and DMA trigger multiplexing 14.5.1 SCT input multiplexing switch matrix SCT_PIN[0:3] inputs ADC_THCMP_IRQ ACMP_O T0_MAT2 GPIOINT_BMATCH ARM_TXEV DEBUG_HALTED SCT0 switch matrix SCT_PIN[0:3] ADC_THCMP_IRQ ACMP0_OUT T0_MAT2 GPIOINT_BMATCH ARM_TXEV DEBUG_HALTED Fig 21. SCT input multiplexing 14.5.2 DMA trigger input multiplexing...
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UM11029 NXP Semiconductors Chapter 14: LPC84x Input multiplexing and DMA trigger multiplexing 14.6 Register description All input multiplexer registers reside on word address boundaries. Details of the registers appear in the description of each function. All address offsets not shown in Table 284 are reserved and should not be written to.
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UM11029 NXP Semiconductors Chapter 14: LPC84x Input multiplexing and DMA trigger multiplexing Table 284. Register overview: Input multiplexing (base address 0x4002 C000) …continued Name Access Offset Description Reset Reference value DMA_ITRIG_INMUX11 R/W 0x06C Input mux register for trigger inputs 0 to 12 connected to...
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UM11029 NXP Semiconductors Chapter 14: LPC84x Input multiplexing and DMA trigger multiplexing By default, none of the triggers are selected. Table 285. DMA input trigger input mux input registers 0 to 1 (DMA_INMUX_INMUX[0:1], address 0x4002 C000 (DMA_INMUX_INMUX0) to 0x4002 C004...
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UM11029 NXP Semiconductors Chapter 14: LPC84x Input multiplexing and DMA trigger multiplexing Table 287. DMA input trigger Input mux registers 0 to 24 (DMA_ITRIG_INMUX[0:24], address 0x4002 C040 (DMA_ITRIG_INMUX0) to 0x4002 C0A0 (DMA_ITRIG_INMUX24)) bit description Symbol Value Description Reset value Trigger input number (decimal value) for DMA channel 0x0F n (n = 0 to 12).
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Rev. 1.0 — 16 June 2017 User manual 15.1 How to read this chapter The LPC84x provides an on-chip API in the boot ROM to optimize power consumption in active and sleep modes. See Section 16.1. Read this chapter to configure the reduced power modes deep-sleep mode, power-down mode, and deep power-down mode.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management Table 288. System control register (SCR, address 0xE000 ED10) bit description Symbol Description Reset value Reserved. SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = do not sleep when returning to Thread mode.
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Chapter 15: LPC84x Reduced power modes and power management 15.5 General description Power on the LPC84x is controlled by the PMU, by the SYSCON block, and the ARM Cortex-M0+ core. The following reduced power modes are supported in order from highest to lowest power consumption: 1.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management For configuring the self-wake-up timer: Section 23.5 • • For a list of all wake-up sources: Table 289 “Wake-up sources for reduced power modes” Table 289. Wake-up sources for reduced power modes...
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management 15.6 Register description Table 290. Register overview: PMU (base address 0x4002 0000) Name Access Address Description Reset Reference offset value PCON 0x000 Power control register Table 291 GPREG0...
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management Table 291. Power control register (PCON, address 0x4002 0000) bit description …continued Symbol Value Description Reset value DPDFLAG Deep power-down flag Not deep power-down. Read: deep power-down mode not entered.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management Table 293. Deep power down control register (DPDCTRL, address 0x4002 0014) bit description …continued Symbol Value Description Reset value WAKEPAD_ WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be DISABLE used for other purposes.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management Remark: Do not set bit 1 and bit 7 if you intend to use a pin to wake up the part from deep power-down mode. You can only disable both wake-up pins if the self-wake-up timer is enabled and configured.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management 15.7 Functional description 15.7.1 Power management The part supports a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management 15.7.3.1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices: • The SYSAHBCLKCTRL register controls which memories and peripherals are...
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management 15.7.4.3 Wake-up from sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management – BOD interrupt using the deep-sleep interrupt wake-up register 1 (Table 169). The BOD interrupt must be enabled in the NVIC. The BOD interrupt must be selected in the BODCTRL register.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management 15.7.6.2 Programming power-down mode The following steps must be performed to enter power-down mode: 1. The PM bits in the PCON register must be set to 0x2 (Table 291).
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6. Use the ARM WFI instruction. 15.7.7.3 Wake-up from deep power-down mode using the WAKEUP pin or RESET Pulling the WAKEUP pin or RESET pin LOW wakes up the LPC84x from deep power-down, and the part goes through the entire reset process.
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UM11029 NXP Semiconductors Chapter 15: LPC84x Reduced power modes and power management 1. Enable the low-power oscillator to run in deep power-down mode by setting bits 2 and 3 in the DPDCTRL register to 1 (see Table 293) 2. Ensure that bit 3 in the PCON register (Table 291) is cleared.
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Table 287 for a list of possible trigger input sources. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 260 of 515...
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DMA_ITRIG_INMUX8 USART4_TX_DMA DMA_ITRIG_INMUX9 SPI0_RX_DMA DMA_ITRIG_INMUX10 SPI0_TX_DMA DMA_ITRIG_INMUX11 SPI1_RX_DMA DMA_ITRIG_INMUX12 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 261 of 515...
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16.4 Pin description The DMA controller has no configurable pins. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 262 of 515...
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RAM buffers. The amount of data moved by a single trigger event UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Table 297. Reload descriptors Offset Description + 0x0 Transfer configuration. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 264 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 265 of 515...
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To use channel chaining, first configure DMA channels x and y as if no channel chaining would be used. Then: For channel x: • UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 266 of 515...
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SRAM address of the channel configuration table. Table 303 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 267 of 515...
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Control and status register for DMA channel 6. Table 319 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 268 of 515...
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Control and status register for DMA channel 16. Table 319 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 269 of 515...
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Transfer configuration register for DMA channel 24. Table 320 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 270 of 515...
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18 channels, the table must begin on a 512 byte boundary. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 271 of 515...
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Enables are cleared by writing to ENABLECLR0. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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(but still active), allowing confirmation that there are no remaining operations in progress for that channel. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 273 of 515...
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The INTENCLR0 register is used to clear interrupt enable bits in INTENSET0. The register is write-only. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 274 of 515...
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Section 16.6.17 for a description of the VALID bit. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 275 of 515...
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1 = aborts DMA operations on channel n. 31:25 - Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 276 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 277 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 278 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 279 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 280 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 281 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 282 of 515...
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Configure the USART pin functions through the switch matrix. • UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 283 of 515...
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3. In synchronous mode: The serial clock is Un_SCLK = FCLK/(BRGVAL+1). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 284 of 515...
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USART block receives no clocks from the UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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USART receive/transmit protocol. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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PINASSIGN12 Table 181 Receiver input for USART3. to pin UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 287 of 515...
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Remark: The fractional value and the USART peripheral clock are shared between all USARTs. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 288 of 515...
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Fig 25. USART block diagram-need to modify in eps UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 289 of 515...
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0x02C Address register for automatic address matching. Table 334 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 290 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 291 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 292 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 293 of 515...
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Un_RxD independently from transmission on Un_TXD). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 294 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 295 of 515...
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RO = Read-only, W1 = write 1 to clear. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 296 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 297 of 515...
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Remark: Reading this register changes the status flags in the RXDATSTAT register. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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TXDAT. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 299 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 300 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 301 of 515...
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FRG. See Figure UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 302 of 515...
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USART output. Any of the USARTs on the LPC84x device can use either FRG0 or FRG1. See Table 151 “Fractional generator 0 divider value register (FRG0DIV, address 0x4004 80D0) bit description”...
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RXDAT and RXDATSTAT registers, allowing software to double-check for the expected character. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 304 of 515...
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Generally speaking, it is recommended to use the highest oversampling where the rate error is acceptable in the system. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 305 of 515...
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The peripheral clock for both SPIs is the system clock (see Figure 7 “LPC84x clock • generation”). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 306 of 515...
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NVIC and in the SPI’s INTENSET register, can then wake up the core. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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SPI functions to pins on the part. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 308 of 515...
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PINASSIGN6 Table 186 Slave Select 1. to pin UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 309 of 515...
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1 to that bit position UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 310 of 515...
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Reverse. Data is transmitted and received in reverse order (LSB first). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 311 of 515...
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Timing details are shown in: Section 18.7.2.1 “Pre_delay and Post_delay” Section 18.7.2.2 “Frame_delay” UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 312 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 313 of 515...
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Stalled status flag. This indicates whether the SPI is currently in a stall condition. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 314 of 515...
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An interrupt will be generated if the transmitter underruns. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 315 of 515...
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For details on the slave select process, see Section 18.7.4. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 316 of 515...
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Reserved, the value read from a reserved bit is not defined. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 317 of 515...
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Remark: The active state of the SSEL3 pin is configured by bits in the CFG register. SSEL3 asserted. SSEL3 not asserted. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 318 of 515...
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TXDAT. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 319 of 515...
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For details on clocking, see Section 18.7.3 “Clocking and data rates”. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 320 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 321 of 515...
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MISO Data frame Fig 29. Basic SPI operating modes UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 322 of 515...
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Pre_delay Data frame Post_delay Fig 30. Pre_delay and Post_delay UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 323 of 515...
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First data frame Frame_delay Second data frame Fig 31. Frame_delay UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 324 of 515...
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First data frame Transfer _delay Second data frame Fig 32. Transfer_delay UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 325 of 515...
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RXSSEL_N field of the RXDAT register. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 326 of 515...
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Stalls are reflected in the STAT register by the Stalled status flag, which indicates the current SPI status. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 327 of 515...
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Second data frame Fig 33. Examples of data stalls UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 328 of 515...
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The peripheral clock for the I2C is the system clock (see Figure 34). • UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 329 of 515...
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Table 207 “PIO0_10 register (PIO0_10, address 0x4004 4020) bit description”. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 330 of 515...
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The result is an SCL clock of 375 kHz. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 331 of 515...
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I2C blocks to pins through the switch matrix. See Table 349. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 332 of 515...
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5. Acknowledge (“ack”) the data by setting SLVCONTINUE = 1 in the slave control register. See Table 363. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 333 of 515...
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Table 169 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description”. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 334 of 515...
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The architecture of the I2C-bus interface is shown in Figure UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 335 of 515...
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I2Cn_SDA Time-out I2Cn_SCL Fig 35. I2C block diagram UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 336 of 515...
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C slave function is disabled. Enabled. The I C slave function is enabled. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 337 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 338 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 339 of 515...
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Deep-sleep or Power-down mode could be entered at this time. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 340 of 515...
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Active. The Monitor function considers the I C bus to be active. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 341 of 515...
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Send a Stop or Repeated Start. Slave NACKed transmitted data. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 342 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 343 of 515...
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Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes should be written to them. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 344 of 515...
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EVENTTIMEOUTEN bit in the INTENSET register. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 346 of 515...
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MSTSTART and MSTSTOP are not self-clearing flags. ORing in new data following a Start or Stop may cause undesirable side effects. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 347 of 515...
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Master function. These include the clock (SCL) high and low times, repeated Start setup time, and transmitted data setup time. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 348 of 515...
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9 clocks. Minimum SCL low time is 9 clocks of the I clock pre-divider. Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 349 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 350 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 351 of 515...
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The SLVQUAL0 register can alter how Slave Address 0 is interpreted. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 352 of 515...
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C pins, and adds indication of Start, Repeated Start, and data NACK. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 353 of 515...
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400 KHz clock rate. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 354 of 515...
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F6), or just one. In the case of Slave Receiver mode, data is received in the normal UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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DMA. The DMA supports three DMA requests: data transfer in master mode, slave mode, and monitor mode. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 356 of 515...
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Chapter 20: LPC84x Standard counter/timer (CTIMER) Rev. 1.0 — 16 June 2017 User manual 20.1 How to read this chapter The standard timer is available on all LPC84x devices. 20.2 Features • 32-bit counter/timer with a programmable 32-bit prescaler. The timer includes external capture and match pin connections.
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Figure 36 shows the block diagram for the timer. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 358 of 515...
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Chapter 20: LPC84x Standard counter/timer (CTIMER) Fig 36. 32-bit counter/timer block diagram UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 359 of 515...
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Note that match conditions may be used internally without the use of a device pin. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 360 of 515...
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TC is reset to zero. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 361 of 515...
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Reset Value reflects the data stored in used bits only. It does not include reserved bits content. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Symbol Description Reset value 31:0 TCVAL Timer counter value. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 363 of 515...
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Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 364 of 515...
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000, but capture and/or interrupt can be selected for the other 3 CAP inputs. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 365 of 515...
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(Section 20.8.1 “Rules for single edge controlled PWM outputs” on page 371). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 366 of 515...
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Reserved. Read value is undefined, only zero should be written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 367 of 515...
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Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 368 of 515...
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Match. CTIMER_MAT2 is controlled by EM2. PWM. PWM mode is enabled for CTIMER_MAT2. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 369 of 515...
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Reset value 31:0 SHADOW Timer counter match shadow value. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 370 of 515...
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PWM signal is HIGH already, then the PWM signal will be cleared with the start of the next PWM cycle. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 371 of 515...
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DMA requests. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 372 of 515...
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Chapter 21: LPC84x SCTimer/PWM Rev. 1.0 — 16 June 2017 User manual 21.1 How to read this chapter The SCTimer/PWM is available on all LPC84x devices. Remark: For a detailed description of SCTimer/PWM applications and code examples, Ref. 5 “AN11538”.
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SCT clock select SCTCLKSEL[1:0] aaa-xxxxxx Fig 40. SCTimer/PWM clocking UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 374 of 515...
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Table 188 SCT match and PWM to pin output. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 375 of 515...
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State Machine engine. Events identify the UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Capability of selecting a “greater-than-or-equal-to” match condition for the purpose of • event generation. Fig 42. SCTimer/PWM block diagram UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 377 of 515...
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SCT control register low counter 16-bit 0x0004 0004 21.6.3 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 378 of 515...
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7; high counter 16-bit; REGMODE0_H to REGMODE7_H = 0 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 379 of 515...
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0x514 SCT output 2 clear register 0x0000 0000 21.6.27 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 380 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 381 of 515...
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CAPCTRL[7:0] Fig 44. SCTimer/PWM event configuration and selection registers UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 382 of 515...
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In the dual-counter mode, the events can be selected independently for each counter. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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The SCTimer/PWM output register to set or clear any of the SCTimer/PWM outputs or • to read the state of the outputs. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 384 of 515...
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This bit applies to both the higher and lower registers when the UNIFY bit is set. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 385 of 515...
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CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 386 of 515...
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If such an event matches the mask in the Start register, this bit is cleared and counting resumes. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 387 of 515...
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LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 388 of 515...
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I/O event or an event generated by the other counter can restart the counter. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 389 of 515...
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(event 0 = bit 16, event 1 = bit 17, event 7 = bit 23). 31:24 - Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 390 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 391 of 515...
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Input 4 state. Input 4 state on the last SCTimer/PWM clock edge. 15:5 Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 392 of 515...
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1 = register operates as capture registers. 31:24 - Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 393 of 515...
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Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Clear output (or set based on the SETCLR1 field). Toggle output. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 395 of 515...
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Event-triggered DMA requests are particularly useful for launching DMA activity to or from other peripherals under the control of the SCTimer/PWM. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 396 of 515...
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SCTimer/PWM interrupt request if all enabled flag register bits are zero. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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A Match can only occur in a clock in which the counter is running (STOP and HALT are both 0). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 398 of 515...
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In either case, reloading does not occur if the corresponding NORELOAD bit is set in the CFG register. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 399 of 515...
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0), setting bit 0 permanently enables this event. Conversely, clearing bit 0 will disable the event. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 400 of 515...
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1x. In this case the clock input is an implicit ingredient of every event. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Each bit of an output set register is associated with a different event (bit 0 with event 0, etc.). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 402 of 515...
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See the OUTPUTCTRL register. 31:8 Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 403 of 515...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 404 of 515...
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The event can write a new state value. • UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 405 of 515...
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However, a limit event caused by a Match only clears a non-zero prescaler in one special case as described Section 21.7.8. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 406 of 515...
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RISE or FALL Event can occur whenever HALT = 0 (A). UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 407 of 515...
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L and H 16-bit counters are used. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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– Set the corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCTimer/PWM interrupt. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 409 of 515...
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– When the counters are halted, software can set any SCTimer/PWM output HIGH or LOW directly by writing to the OUT register. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 410 of 515...
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6 events and match 0 used with autolimit function • 2 states • UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 411 of 515...
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MAT2 is associated with event 1. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 412 of 515...
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Set STATEMSK5 bit 1 to 1. Set all other bits to 0. Event 5 is enabled event 5 is enabled in state 1. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 413 of 515...
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Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) Rev. 1.0 — 16 June 2017 User manual 22.1 How to read this chapter The watchdog timer is identical on all LPC84x parts. 22.2 Features • Internally resets chip if not reloaded during the programmable time-out period.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) WWDT SYSCON system clock WWDT registers SYSAHBCLKCTRL (WWDT clock enable) 503 kHz watchdog oscillator 24-bit timer PDRUNCFG (enable watchdog oscillator WDTOSC_PD) Fig 51. WWDT clocking 22.4 Pin description The WWDT has no external pins.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) When the Watchdog Timer is configured so that a watchdog event will cause a reset and the counter reaches zero, the CPU will be reset, loading the stack pointer and program counter from the vector table as for an external reset.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) The synchronization logic between the two clock domains works as follows: When the MOD and TC registers are updated by APB operations, the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) 22.6 Register description The Watchdog Timer contains the registers shown in Table 415. The reset value reflects the data stored in used bits only. It does not include the content of reserved bits.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) Table 416. Watchdog mode register (MOD, 0x4000 0000) bit description Symbol Value Description Reset value WDINT Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by writing 1.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) Table 417. Watchdog operating modes selection WDEN WDRESET Mode of Operation X (0 or 1) Debug/Operate without the Watchdog running. Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) Table 419. Watchdog Feed register (FEED, 0x4000 0008) bit description Symbol Description Reset Value FEED Feed value should be 0xAA followed by 0x55. 31:8 Reserved, user software should not write ones to reserved bits.
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UM11029 NXP Semiconductors Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) Table 422. Watchdog Timer Window register (WINDOW, 0x4000 0018) bit description Symbol Description Reset Value 23:0 WINDOW Watchdog window value. 0xFF FFFF 31:24 - Reserved, user software should not write ones to reserved bits.
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Chapter 23: LPC84x Self-wake-up timer (WKT) Rev. 1.0 — 16 June 2017 User manual 23.1 How to read this chapter The self-wake-up timer is available on all LPC84x parts. 23.2 Features • 32-bit, loadable down counter. Counter starts automatically when a count value is loaded.
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The self-wake-up timer can be clocked from two alternative clock sources: UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 424 of 515...
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The oscillator must also be set to remain active in Deep power-down if needed. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 425 of 515...
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A read reflects the current value of the timer. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 426 of 515...
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Chapter 24: LPC84x Multi-Rate Timer (MRT) Rev. 1.0 — 16 June 2017 User manual 24.1 How to read this chapter The MRT is available on all LPC84x parts. 24.2 Features • 31-bit interrupt timer Four channels independently counting down from individually set values •...
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LOAD bit to 1. No interrupt is generated when the INTVALn register is written. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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The reset values shown in Table 426 are POR reset values. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 429 of 515...
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This register contains the MRT load value and controls how the timer is reloaded. The load value is IVALUE -1. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 430 of 515...
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The control register configures the mode for each MRT and enables the interrupt. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 432 of 515...
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Writing a 1 to this bit clears the interrupt request. 31:4 Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 433 of 515...
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Chapter 25: LPC84x System tick timer (SysTick) Rev. 1.0 — 16 June 2017 User manual 25.1 How to read this chapter The SysTick timer is available on all LPC84x parts. 25.2 Features • Simple 24-bit timer. Uses dedicated exception vector.
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UM11029 NXP Semiconductors Chapter 25: LPC84x System tick timer (SysTick) The SysTick timer is an integral part of the Cortex-M0+. The SysTick timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software.
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UM11029 NXP Semiconductors Chapter 25: LPC84x System tick timer (SysTick) Table 434. SysTick Timer Control and status register (SYST_CSR, 0xE000 E010) bit description Symbol Description Reset value ENABLE System Tick counter enable. When 1, the counter is enabled. When 0, the counter is disabled.
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UM11029 NXP Semiconductors Chapter 25: LPC84x System tick timer (SysTick) 25.6.4 System Timer Calibration value register The value of the SYST_CALIB register is driven by the value of the SYSTCKCAL register in the system configuration block SYSCON (see Table 164).
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UM11029 Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Rev. 1.0 — 16 June 2017 User manual 26.1 How to read this chapter The ADC is available on all parts. The number of available ADC channels depends on the package type.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Calibration is required after every power-up or wake-up from Deep power-down • mode. See Section 26.3.4 “Hardware self-calibration”. For a sampling rate higher than 1 Msamples/s, VDDA must be higher than 2.7 V. See •...
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) 26.3.2 Perform a sequence of conversions triggered by an external pin The ADC can perform conversions on a sequence of selected channels. Each individual conversion of the sequence (single-step) or the entire sequence can be triggered by hardware.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 439. ADC hardware trigger inputs Input # Source Description No hardware trigger. PININT0_IRQ GPIO_INT interrupt 0. PININT1_IRQ GPIO_INT interrupt 1. SCT0_OUT3 SCT output 3. SCT0_OUT4 SCT output 4. T0_MAT3 CTIMER match 3.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) The VREFP and VREFN pins provide a positive and negative reference voltage input. The result of the conversion is (4095 x input voltage VIN)/(VREFP - VREFN). The result of an input voltage below VREFN is 0, and the result of an input voltage above VREFP is 4095 (0xFFF).
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) 26.5 General description sequence B complete IRQ ADC_SEQB_IRQ PININT_IRQ0 data overrun IRQ ADC_OVR_IRQ PININT_IRQ1 SCT_OUT3 start conversion SCT_OUT4 CONVERSION TRIGGER T0_MAT3 result DATA COMP0_OUT REGISTERS GPIO_INT_BMAT ARM_TXEV THRESHOLD channel CHANNEL...
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) 26.6 Register description The reset value reflects the data stored in used bits only. It does not include reserved bits content. Table 442. Register overview : ADC (base address 0x4001 C000 )
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 442. Register overview : ADC (base address 0x4001 C000 ) Name Access Address Description Reset Reference offset value THR1_LOW 0x054 A/D Low Compare Threshold Register 1: Contains the lower...
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 443. A/D Control Register (CTRL, addresses 0x4001 C000) bit description Symbol Value Description Reset value CLKDIV The system clock is divided by this value plus one to produce the sampling clock.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 444. A/D Conversion Sequence A Control Register (SEQA_CTRL, address 0x4001 C008) bit description Symbol Value Description Reset value 11:0 CHANNELS Selects which one or more of the twelve channels will be sampled and 0x00 converted when this sequence is launched.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 444. A/D Conversion Sequence A Control Register (SEQA_CTRL, address 0x4001 C008) bit description Symbol Value Description Reset value BURST Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 444. A/D Conversion Sequence A Control Register (SEQA_CTRL, address 0x4001 C008) bit description Symbol Value Description Reset value SEQA_ENA Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQA_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit).
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 445. A/D Conversion Sequence A Control Register (SEQA_CTRL, address 0x4001 C008) bit description Symbol Value Description Reset value TRIGPOL Select the polarity of the selected input trigger for this conversion sequence.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 445. A/D Conversion Sequence A Control Register (SEQA_CTRL, address 0x4001 C008) bit description Symbol Value Description Reset value SINGLESTEP When this bit is set, a hardware trigger or a write to the START bit...
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) 26.6.4 A/D Global Data Register A and B The A/D Global Data Registers contain the result of the most recent A/D conversion completed under each conversion sequence. Results of A/D conversions can be read in one of two ways. One is to use these A/D Global Data Registers to read data from the ADC at the end of each A/D conversion.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 446. A/D Sequence A Global Data Register (SEQA_GDAT, address 0x4001 C010) bit description Symbol Description Reset value 29:26 These bits contain the channel from which the RESULT bits were converted (e.g.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 447. A/D Sequence B Global Data Register (SEQB_GDAT, address 0x4001 C014) bit description Symbol Description Reset value 19:18 THCMPCROSS Indicates whether the result of the last conversion performed represented a...
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) The information presented in the DAT registers always pertains to the most recent conversion completed on that channel regardless of what sequence requested the conversion or which trigger caused it.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 448. A/D Data Registers (DAT[0:11], address 0x4001 C020 (DAT0) to 0x4001 C04C (DAT11)) bit description Symbol Description Reset value 29:26 CHANNEL This field is hard-coded to contain the channel number that this particular register relates to (i.e.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 449. A/D Compare Low Threshold register 0 (THR0_LOW, address 0x4001 C050) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 452. Compare High Threshold register 1 (THR1_HIGH, address 0x4001 C05C) bit description Symbol Description Reset value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 453. A/D Channel Threshold Select register (CHAN_THRSEL, addresses 0x4001 C060) bit description Symbol Value Description Reset value CH6_THRSEL Threshold select by channel. Threshold 0. Channel 6 results will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers Threshold 1.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Disabled: Threshold comparisons on channel n will not generate an A/D • threshold-compare interrupt request. Outside threshold: A conversion result on channel n which is outside the range • specified by the designated HIGH and LOW threshold registers will set the channel n THCMP flag in the FLAGS register and generate an A/D threshold-compare interrupt request.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 454. A/D Interrupt Enable register (INTEN, address 0x4001 C064 ) bit description Symbol Value Description Reset value ADCMPINTEN2 Threshold comparison interrupt enable. Disabled. Outside threshold. Crossing threshold. Reserved 10:9 ADCMPINTEN3 Threshold comparison interrupt enable.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 454. A/D Interrupt Enable register (INTEN, address 0x4001 C064 ) bit description Symbol Value Description Reset value 24:23 ADCMPINTEN10 Threshold comparison interrupt enable. Disabled. Outside threshold. Crossing threshold. Reserved 26:25 ADCMPINTEN11 Threshold comparison interrupt enable.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 455. A/D Flags register (FLAGS, address 0x4001 C068) bit description Symbol Description Reset value THCMP5 Threshold comparison event on Channel 5. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) Table 455. A/D Flags register (FLAGS, address 0x4001 C068) bit description Symbol Description Reset value SEQB_INT Sequence A interrupt/DMA flag. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every A/D conversion performed as part of sequence B.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) hardware triggers. Each sequence can be triggered by a different hardware trigger. One of these conversion sequences is referred to as the A sequence and the other as the B sequence.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) state (as designated by the TRIGPOL bit). If this condition is not met, a trigger will be generated immediately upon enabling the sequence - even though no actual transition has occurred on the trigger input.
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) 26.7.4.2 Threshold-Compare Out-of-Range Interrupt Every conversion performed on any channel is automatically compared against a designated set of low and high threshold levels specified in the THRn_HIGH and THRn_LOW registers. The results of this comparison on any individual channel(s) can be...
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UM11029 NXP Semiconductors Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC) 26.7.7 Hardware Trigger Source Selection Each ADC has a selection of several on-chip and off-chip hardware trigger sources. The trigger to be used for each conversion sequence is specified in the TRIGGER fields in the two SEQn_CTRL registers.
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Selectable speed vs. power. Maximum update rate of 1 MHz. • UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 469 of 515...
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V if the ADC and DAC are not used. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 470 of 515...
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Clear on any write to the CR register. Set by hardware when the timer times out. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 471 of 515...
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16-bit reload value for the DAC interrupt/DMA timer. 31:16 - Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 472 of 515...
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If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the CR address will go directly to the CR register. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 473 of 515...
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Rev. 1.0 — 16 June 2017 User manual 28.1 How to read this chapter The analog comparator is available on all LPC84x parts. 28.2 Features • Selectable external inputs can be used as either the positive or negative input of the comparator.
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Section 10.3.1 “Connect an internal signal to a package pin” to assign the analog comparator output to any pin on the LPC84x package. Table 462. Analog comparator pin description Function Type Pin...
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COMPEDGE and the interrupt request are cleared when software writes a 1 to EDGECLR. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 476 of 515...
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Reserved. Write as 0. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 477 of 515...
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5 mV 10 mV 20 mV 31:27 - Reserved UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 478 of 515...
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Selects the reference voltage Vref for the voltage ladder: Supply pin VDD VDDCMP pin 31:7 Reserved. UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 479 of 515...
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Chapter 29: LPC84x CRC engine Rev. 1.0 — 16 June 2017 User manual 29.1 How to read this chapter The CRC engine is available on all LPC84x parts. 29.2 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x –...
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CR C CRC SUM Fig 64. CRC block diagram UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 481 of 515...
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0=No 1’s complement for CRC_SUM 31:6 Reserved Always 0 when read 0x0000000 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 482 of 515...
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1's complement for CRC sum: NO CRC_MODE = 0x0000 0000 CRC_SEED = 0x0000 FFFF UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 483 of 515...
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1's complement for CRC sum: YES CRC_MODE = 0x0000 0036 CRC_SEED = 0xFFFF FFFF UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 484 of 515...
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UM11029 Chapter 30: LPC84x ROM API integer divide routines Rev. 1.0 — 16 June 2017 User manual 30.1 How to read this chapter The ROM-based 32-bit integer division routines are available on all parts. 30.2 Features • Performance-optimized signed/unsigned integer division.
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UM11029 NXP Semiconductors Chapter 30: LPC84x ROM API integer divide routines 30.4 API description The integer division routines perform arithmetic integer division operations and can be called in the application code through simple API calls. Table 471. Divide API calls...
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UM11029 NXP Semiconductors Chapter 30: LPC84x ROM API integer divide routines Table 472. sidiv Routine sidiv Input parameter numerator: Numerator signed integer. denominator: Denominator signed integer. Return Signed division result without remainder. Description Signed integer division 30.4.2 DIV unsigned integer division Table 473.
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UM11029 NXP Semiconductors Chapter 30: LPC84x ROM API integer divide routines 30.5 Functional description 30.5.1 Signed division The example C-code listing below shows how to perform a signed integer division via the ROM API. /* Divide (-99) by (+6) */ int32_t result;...
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Chapter 31: LPC84x Serial Wire Debug (SWD) Rev. 1.0 — 16 June 2017 User manual 31.1 How to read this chapter The debug functionality is identical for all LPC84x parts. 31.2 Features • Supports ARM Serial Wire Debug mode. Direct debug access to all memories, registers, and peripherals.
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UM11029 NXP Semiconductors Chapter 31: LPC84x Serial Wire Debug (SWD) The boundary scan mode and the pins needed are selected by hardware (see Section 31.5.3). There is no access to the boundary scan pins through the switch matrix. Remark: If SWD is disabled in the FAIM configuration, these pins will be configured as GPIO pins on POR.
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UM11029 NXP Semiconductors Chapter 31: LPC84x Serial Wire Debug (SWD) 3.3 V LPC84x ~10 kΩ - 100 kΩ VTREF SWDIO SWDIO from SWD SWCLK SWCLK connector nRESET RESET ~10 kΩ - 100 kΩ DGND PIO0_12 ISP entry The VTREF pin on the SWD connector enables the debug connector to match the target voltage.
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UM11029 NXP Semiconductors Chapter 31: LPC84x Serial Wire Debug (SWD) 31.5.4 Micro Trace Buffer (MTB) The MTB registers are located at memory address 0x5000 C000 and are described in Ref. 4. The EXTTRACE register in the SYSCON block (see Section 8.6.34) starts and...
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AN11538 application note and code bundle (SCT cookbook) AN11538 — ARMv6-M Architecture Reference Manual UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 493 of 515...
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NXP Semiconductors. applications and products. In no event shall NXP Semiconductors be liable for any indirect, incidental, NXP Semiconductors does not accept any liability related to any default, punitive, special or consequential damages (including - without limitation - lost...
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Table 80. Response packet (error) ....54 Table 29. LPC84x device ID register values ..33 Table 81.
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Table 132. FRO direct clock source update enable register (FRG1DIV, address 0x4004 80E0) bit description UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 496 of 515...
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......130 Table 208. PIO0_16 register (PIO0_16, address 0x4004 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 497 of 515...
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......210 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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8060) bit description....275 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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(USART4)) bit description....299 0x4005 8028 (SPI0), 0x4005 C028 (SPI1)) bit UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 500 of 515...
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0x048) bit description....392 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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......452 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Table 473. uidiv ....... .487 UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017...
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Fig 53. Early watchdog feed with windowed mode enabled Fig 7. LPC84x clock generation ....83 Fig 8. UM11029 clock generation (continued) ..84 Fig 54.
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Erase Sector(s) ..... . . 41 continued >> UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 505 of 515...
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Content verification ....65 6.4.4 Flash signature generation result register . . . 62 Chapter 7: LPC84x Nested Vectored Interrupt Controller (NVIC) 7.4.7 Interrupt Priority Register 1 ....75 How to read this chapter .
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8.6.25 Peripheral clock source select registers ..104 Chapter 9: LPC84x FRO API ROM routine 9.4.1 set_fro_frequency ....125 How to read this chapter .
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PIO1_20 register ..... 201 continued >> UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 508 of 515...
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Pattern Match engine example ..236 13.7.3 Pattern match engine edge detect examples 237 Chapter 14: LPC84x Input multiplexing and DMA trigger multiplexing (INPUT MUX, DMA TRIGMUX) 14.5.2 DMA trigger input multiplexing ... 240 14.1...
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UM11029 NXP Semiconductors Chapter 32: Supplementary information Chapter 15: LPC84x Reduced power modes and power management 15.7.4.2 Programming sleep mode ....254 15.1 How to read this chapter ....245 15.7.4.3...
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I2C Status register ....339 continued >> UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 511 of 515...
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SCTimer/PWM DMA request 0 and 1 registers . . continued >> UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. User manual Rev. 1.0 — 16 June 2017 512 of 515...
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21.7 Functional description ....404 Chapter 22: LPC84x Windowed Watchdog Timer (WWDT) 22.5.3.2 Changing the WWDT reload value ..417 22.1...
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UM11029 NXP Semiconductors Chapter 32: Supplementary information Chapter 25: LPC84x System tick timer (SysTick) 25.6.1 System Timer Control and status register . . 435 25.1 How to read this chapter ....434 25.6.2...
Page 515 29.6.1 CRC mode register ....482 Chapter 30: LPC84x ROM API integer divide routines 30.4.3 DIV signed integer division with remainder . 487 30.1...