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FEATURES
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm25LV512: 64K x 8 (512 Kbit)
- Pm25LV010: 128K x 8 (1 Mbit)
Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 32 Kbyte blocks (8 sectors per block)
- Two blocks with 32 Kbytes each (512 Kbit)
Four blocks with 32 Kbytes each (1 Mbit)
- 128 pages per block
Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
High Performance Read
- 25 MHz clock rate (maximum)
Page Mode for Program Operations
- 256 bytes per page
GENERAL DESCRIPTION
The Pm25LV512/010 are 512 Kbit/1 Mbits 3.0 Volt-only serial Flash memories. These devices are designed to use
a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations.
The devices can be programmed in standard EPROM programmers as well.
The device is optimized for use in many commercial applications where low-power and low-voltage operation are
essential. The Pm25LV512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface
consisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are com-
pletely self-timed.
Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled
by programming the status register. Separate write enable and write disable instructions are provided for additional
data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts
to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial
sequence.
The Pm25LV512/010 are manufactured on PMC's advanced nonvolatile CMOS technology, P-FLASH™. The de-
vices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.
Pm25LV512 / Pm25LV010
512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory
With 25 MHz SPI Bus Interface
Block Write Protection
- The Block Protect (BP1, BP0) bits allow part or entire
of the memory to be configured as read-only.
Hardware Data Protection
- Write Protect (WP#) pin will inhibit write operations
to the status register
• Page Program (up to 256 Bytes)
- Typical 2 ms per page program time
• Sector, Block and Chip Erase
- Typical 40 ms sector/block/chip erase time
Single Cycle Reprogramming for Status Register
- Build-in erase before programming
High Product Endurance
- Guarantee 100,000 program/erase cycles per single
sector (preliminary)
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin JEDEC SOIC
- 8-contact WSON
- Optional lead-free (Pb-free) packages
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Table of Contents
Summary of Contents for PMC Pm25LV010
- Page 1 - Low voltage range: 2.7 V - 3.6 V • Memory Organization - Pm25LV512: 64K x 8 (512 Kbit) - Pm25LV010: 128K x 8 (1 Mbit) Cost Effective Sector/Block Architecture - Uniform 4 Kbyte sectors - Uniform 32 Kbyte blocks (8 sectors per block)
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Page 2: Connection Diagrams
CONNECTION DIAGRAMS C E # W P # G N D 8-Pin SOIC PIN DESCRIPTIONS H O L D # S C K l l i l l i C E # H O L D # Top View W P # S C K G N D 8-Contact WSON... -
Page 3: Product Ordering Information
Temperature Range C = Commercial (0°C to +85°C) Package Type S = 8-pin SOIC (8S) Q = 8-contact WSON (8Q) Operating Speed 25 MHz PMC Device Number Pm25LV512 (512 Kbit) Pm25LV010 (1 Mbit) Package Temperature Range Commercial C to + 85... -
Page 4: Block Diagram
BLOCK DIAGRAM SPI Chip Block Diagram High Voltage Generator Control Logic Instruction Decoder Serial /Parallel convert Logic 2KBit Page Buffer Status Address Latch Register & Counter Memory Array X - D E C O D E R... -
Page 5: Serial Interface Description
SERIAL INTERFACE DESCRIPTION Pm25LV512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication term definitions are in the following section. MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave. TRANSMITTER/RECEIVER: The Pm25LV512/010 has separate pins designated for data transmission (SO) and reception (Sl). -
Page 6: Spi Modes
SERIAL INTERFACE DESCRIPTION (CONTINUED) SPI MODES These devices can be driven by microcontroller with its SPI peripheral running in either of the two following modes: Mode 0 = (0, 0) Mode 3 = (1, 1) For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is Figure 2. -
Page 7: Device Operation
Serial Clock (SCK). Then the first manufacturer ID (9Dh) is shifted out on Serial Data Output (SO), followed by the device ID (7Bh = Pm25LV512; 7Ch = Pm25LV010) and the second manufacturer ID (7Fh), each bit been shifted out during the falling edge of Serial Clock (SCK). - Page 8 WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec- tion for the Pm25LV010. The Pm25LV010 is divided into four blocks where the top quarter (1/4), top half (1/2), or all of the memory blocks can be protected (locked out) from write. The Pm25LV512 is divided into 2 blocks where all of the memory blocks can be protected (locked out) from write.
- Page 9 Table 5. Block Write Protect Bits t s i s t i ) 4 / ) 2 / ) l l The WRSR instruction also allows the user to enable or disable the Write Protect (WP#) pin through the use of the Write Protect Enable (WPEN) bit.
- Page 10 READ: Reading the Pm25LV512/010 via the SO (Serial Output) pin requires the following sequence. After the CE# line is pulled low to select a device, the READ instruction is transmitted via the Sl line followed by the byte address to be read (Refer to Table 7). Upon completion, any data on the Sl line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line.
- Page 11 SECTOR_ERASE, BLOCK_ERASE: Before a byte can be reprogrammed, the sector/block which contains the byte must be erased. In order to erase the Pm25LV512/010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the SECTOR ERASE or BLOCK ERASE instruction can be executed.
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Page 12: Absolute Maximum Ratings
ABSOLUTE MAXIMUM RATINGS a t l a t l Notes: 1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. - Page 13 DC CHARACTERISTICS Applicable over recommended operating range from: = 0°C to +85°C, V = +2.7 V to +3.6 V (unless otherwise noted). Symbol Parameter Vcc Active Read Current Vcc Program/Erase Current Vcc Standby Current CMOS Vcc Standby Current TTL Input Leakage Current Output Leakage Current Input Low Voltage Input HIgh Voltage...
- Page 14 AC CHARACTERISTICS Applicable over recommended operating range from T = 1TTL Gate and 30 pF (unless otherwise noted). l l a d i l t s i = 0°C to +85°C, V = +2.7 V to +3.6 V...
- Page 15 AC CHARACTERISTICS (CONTINUED) AC WAVEFORMS C E # S C K VALID IN HI-Z Note: 1. For SPI Mode 0 (0,0) OUTPUT TEST LOAD 3.3 V 1.8 K OUTPUT PIN 1.3 K C K L C K H INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 3.0 V Input...
- Page 16 AC CHARACTERISTICS (CONTINUED) HOLD Timing C E # S C K H O L D # PIN CAPACITANCE ( f = 1 MHz, T = 25°C ) Note: These parameters are characterized but not 100% tested.
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Page 17: Timing Diagrams
TIMING DIAGRAMS RDID Timing C E # S C K I N S T R U C T I O N 3 Dummy Bytes 1010 1011b H I G H I M P E D A N C E WREN Timing S C K WRDI Timing C E #... - Page 18 RDSR Timing C E # S C K INSTRUCTION = 0000 0101b H I G H I M P E D A N C E WRSR Timing C E # S C K INSTRUCTION = 0000 0001b H I G H I M P E D A N C E READ Timing C E # S C K...
- Page 19 FAST READ Timing C E # S C K INSTRUCTION = 0000 1011b H I G H I M P E D A N C E C E # 34 35 36 S C K D U M M Y B Y T E H I G H I M P E D A N C E PAGE PROGRAM Timing S C K...
- Page 20 SECTOR ERASE Timing C E # S C K INSTRUCTION = 1101 0111b H I G H I M P E D A N C E BLOCK ERASE Timing C E # S C K INSTRUCTION = 1101 1000b H I G H I M P E D A N C E CHIP ERASE Timing C E # S C K...
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Page 21: Reliability Characteristics
PROGRAM/ERASE PERFORMANCE Note: These parameters are characterized and are not 100% tested. RELIABILITY CHARACTERISTICS Note: 1. These parameters are characterized and are not 100% tested. 2. Preliminary specification only and will be formalized after cycling qualification test. i t i r i t i r i t i r i t i r... - Page 22 PACKAGE TYPE INFORMATION 8-Pin JEDEC Small Outline Integrated Circuit (SOIC) Package (measure in millimeters) Top View 4.00 3.80 6.20 5.80 End View 45º 1.27 0.40 Side View 0.51 0.33 5.00 4.80 1.27 BSC 0.25 0.10 1.75 1.35 0.25 0.19...
- Page 23 PACKAGE TYPE INFORMATION (CONTINUED) 8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters) Top View 6.00 B S C Bottom View 4.00 5.00 B S C Pin 1 1.27 B S C 0.48 0.35 0.75 0.50 Side View 0.25 0.19 0.80 0.70...
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Page 24: Revision History
REVISION HISTORY...
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