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IMD SF104x User Manual

Fingerprint image sensor module
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SF3013M Fingerprint Image Sensor Module User Manual
PRELIMINARY
SF104x
Fingerprint Image Sensor Module
User Manual
Image Match Design Inc.
http://www.imagematch.com.tw/
B3-2, No. 1, Lising 1st Road, Hisnchu Science
Park, Hsinchu 300, Taiwan (R.O.C.)
Tel：+886-3-666-9388
Fax：+886-3-666-9387
Service：albertke@imagematch.com.tw
SF104-P01
February 7, 2014
Page - 1

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  • Page 1 PRELIMINARY SF104-P01 SF104x Fingerprint Image Sensor Module User Manual February 7, 2014 Image Match Design Inc. http://www.imagematch.com.tw/ B3-2, No. 1, Lising 1st Road, Hisnchu Science Park, Hsinchu 300, Taiwan (R.O.C.) Tel：+886-3-666-9388 Fax：+886-3-666-9387 Service：albertke@imagematch.com.tw SF3013M Fingerprint Image Sensor Module User Manual...

  • Page 2: Revision History

    PRELIMINARY SF104-P01 Revision History Version Date Content Approved Checked Drawn 2014/02/07 Initial draft Albert Ke 2014/3012 I/O spec Interface and drawing 2014/03/17 Eros update SF3013M Fingerprint Image Sensor Module User Manual Page - 2...

  • Page 3: Table Of Contents

    PRELIMINARY SF104-P01 Content 1  OVERVIEW ........................5  1.1  ......................5  ESCRIPTION 1.2  ......................... 5  EATURES 1.3  ..................6  ENSOR LOCK IAGRAM 1.4  ......................6  PPLICATIONS 2  PHYSICAL DIMENSION ....................7  3  DEVICE OPERATION ....................7  3.1  ..................7  ETTING UP CLOCK DIVIDER 3.2 ...
  • Page 4 PRELIMINARY SF104-P01 9.5  ................... 36  EFERENCE SCHEMATIC SF3013M Fingerprint Image Sensor Module User Manual Page - 4...

  • Page 5: Overview

    A/D converting, digital process, following is simple interface protocol. The captured image quality of SF104x can be adjusted by setting gain, offset and reference voltage parameters. In addition, the internal operation parameter and interface speed can also be configured to the need.

  • Page 6: Sensor Block Diagram

    PRELIMINARY SF104-P01 1.3 Sensor Block Diagram   1.4 Applications The compact, thin packaging of SF104x sensor module allows a wide range of applications  Security devices  Fingerprint identification systems  Fingerprint recognition systems SF3013M Fingerprint Image Sensor Module User Manual...

  • Page 7: Physical Dimension

    PRELIMINARY SF104-P01 Physical Dimension The sensor’s active pixel array is 160x160 pixels, and the SF104xM module is a 13.4mm*13.9mm highly integrated SPI fingerprint module. Device operation Sensor & ADC Timing ADCCLK D0~D7 Generator 128-BYTE Digital control FIFO D0~D7 Registers Analog control Register access interface 3.1 Setting up clock divider...

  • Page 8: Configuring Gain And Range Of Pre-Amp And Adc

    PRELIMINARY SF104-P01 OPCLK Clock from Divide by Divide PCLK external div_opclk by 6 oscillator detect Divide by Divide by start 4096 (DDIV+1) In the above diagram, OPCLK is used for internal timing, and PCLK is for image pixels. The “detect start” signal starts the short “finger detect” cycle in detect mode. The PCLK is 1/6 of OPCLK.

  • Page 9: Command And Registers

    PRELIMINARY SF104-P01 160x160 Sample PGA1 PGA2 Pixel &hold array Gain Gain Two cascaded programmable gain amplifier are used for conditioning the sensor signal before converted by ADC. Register REG1/REG_PGA bit [1:0] is for the control of PGA1 gain, and register REG1/REG_PGA bit [7:4] for the control of PGA2 gain. The ADC bias current and input voltage range is controlled by BIAS, (VRT-VRB) and VRB parameters in REG3/REG_ADC.
  • Page 10 PRELIMINARY SF104-P01 command code name function read/write 0x01 rdata read pixel data 0x02 start start scan 0x03 status read status 0xC0 srst software reset 0x20+N rread read register 0x40+N rwrite write register For the rread and rwrite command, the number N is the register address. The effective N is in the range of 0x00 to 0x11.

  • Page 11: Spi Command Protocol

    PRELIMINARY SF104-P01 3.4 SPI command protocol Command and data are exchanged throught the SPI MISO and MOSI wires. Each byte of data sent through the MOSI port brings back a received byte through the MISO port. Commands can be cascaded one by another. The term “SPI command sequence” in the following context is defined as a sequence of command code and data bytes exchange within one active SPISEL strobe.
  • Page 12 PRELIMINARY SF104-P01  read sequence (the last command byte is a dummy command)  write sequence  read image sequence In fact, except for the write register command (which writes a sequence of register content), commands can be mixed in a single sequence like following: ...

  • Page 13: Command Code Detail

    PRELIMINARY SF104-P01 3.5 Command code detail Code 01 / RDATA command (read only)  This command pumps image data from FIFO and sends it to host Code 02 / START command (write only)  This command starts fingerprint image scan Code 03 / status read command (read only) ...
  • Page 14 PRELIMINARY SF104-P01 Code 0xC0 / SRST command (write only) This command generates a software reset to the system. Its effect is the same as  hardware reset except that the register content is left unchanged. Code 0x2N / register read command ...

  • Page 15: Register Detail

    PRELIMINARY SF104-P01 3.6 Register detail REGISTER R/W Bit(s) DEFAULT DESCRIPTION NAME 0000_0000 Clock control Test mode 1 00 : AREGC[2] [7:6] 01 : TESTPIN = VREF 10 : TESTPIN = VINPTST 11 : AREGC[0] Test mode 0 REG_CLK 00 : AREGC[3] [5:4] 01 : TESTPIN = VAMP 10 : TESTPIN = CDS...
  • Page 16 PRELIMINARY SF104-P01 For the gain control of PGA2 PGA2 gain =PGA_gain*[(Vinp_pga-Vinn_pga)+Voff]/[2*(VRT-VRB)]*255 EN_TEST1 0 : Disable Test mode 1 1 : Enable Test mode 1 EN_TEST0 0 : Disable Test mode 0 1 : Enable Test mode 0 PGA1_GAIN 00 : 4.6 [1:0] 01 : 7.6 10 : 12.8...
  • Page 17 PRELIMINARY SF104-P01 ADC bias current settings 000 : 8uA 001 : 12uA 010 : 16uA (default) 011 : 20uA 1xx : 24uA ADC_VRT (VRT-VRB) settings: 00 : 0.90V [3:2] 01 : 1.05V (default) 10 : 1.20V 11 : 1.35V ADC_VRB VRB settings: 00 : 0.800V [1:0]...
  • Page 18 PRELIMINARY SF104-P01 Bit address for writing OTP_WD Write data 0000_0000 OTP control [7:3] Not used OTP_PRG OTP “PRG” control bit (Program enable) REG_OTP_ MODE OTP_RST OTP “RST” control bit (Reset) OTP_CEB OTP “CEB” control bit (Enable, active low) OTP read data REG_OTP_R OTP_RDAT [7:0]...
  • Page 19 PRELIMINARY SF104-P01 EN_WINDOW Enable windowing mode The windowing size is assigned by reg_llx, reg_lly, reg_urx and reg_ury (0x0C~0x0F) 0 : Disable 1 : Enabl EN_INSCAN_DET Enable the in scan line detection mode The finger detection scan line can be changed according to value of reg_inscanline (0x11) if enable 0 : Disable 1 : Enable...
  • Page 20 PRELIMINARY SF104-P01 EN_ANALOG Enable analog circuit 0 : Disable 1 : Enable 0000_0000 Mode control bits Not used EN_INTR Enable detect interrupt REG_MODE B 0 : Disable 1 : Enable Not used ENBITS [4:0] Must be set to value 21 (0x15H) to enable the chip 0000_0000 Windowing function position setting REG_LLX...
  • Page 21 PRELIMINARY SF104-P01 Windowing is a flexible function which user can read the image data within 160x160 pixel size according to your need. The windowing size is assigned by 4 registers, REG_LLX, REG_LLY, REG_URX and REG_URY. Refer to following picture to how to set the windowing position and size. 0000_0000 Windowing function position setting REG_LLY...

  • Page 22: Operation Workflow

    PRELIMINARY SF104-P01 Change mode for switching mode. See the “finger detection” section below. 0100_0000 Set in scan detection finger detection line number INSCANLINE_NUMBER In scan line number value which limitation is 0~0x9F or Y axis range when enable windowing function. REG_INSCA NLINE [7:0]...

  • Page 23: Reset

    PRELIMINARY SF104-P01 4.2 Reset There are 3 sources of Reset that can force the chip entering reset state (in which all internal logic are disabled)  the hardware reset pin 　  the SPI software reset command 　  　 the reset caused by the content of REG_MODE (REG11) register, as described earlier.

  • Page 24: Timing Considerations

    PRELIMINARY SF104-P01 The finger detection mode is enabled by setting the EN_DET bit (bit 5 of REG10) to 1. Finger detect interrupt is enabled by setting the EN_INTR bit (bit 6 of REG11) to 1. Enabling interrupt also changes the hardware Reset pin to INTR output pin. In finger detection mode, the hardware logic will periodically scan the row which assign by REG_INSCANLINE of the pixel array.

  • Page 25: Asample Session

    PRELIMINARY SF104-P01 Several timing parameter should be kept in mind for good estimation of timing: Upon power up, reset, or whenever detection mode is turned off, the delay time from  sending the start command to the first data byte available is about 180 pclk cycles. ...
  • Page 26 PRELIMINARY SF104-P01 GPIO.SRST=0; GPIO.SRST=1; // initialize registers detect threshold (REG8=128) detect divider (REG9=128) enable analog (REG10[0]=1) enable clock (REG10[2]=1) enable detect (REG10[5]=1) enable interrupt pin (REG11[6]=1) REG10 spiwrite({0x40,0x32,0xE5,0x50,0x25,0x00,0x00,0x00,0x00,0x00,0x20,0x85,0x15,0x00,0x00,0x9F,0x9F}, 17); spiwrite({0x50,0x00},2); // inform chang of geometry // software reset spiwrite({0xc0},1); // wait for interrupt while (~GPIO.INTR) nop;...
  • Page 27 PRELIMINARY SF104-P01 // delay 180 pclk cycle or wait for FIFO status is half-full GPIO.SSEL = 0; SPISEND(0x03); repeat { byte=SPIREAD({0x03}); } until (byte.bit0 == 1); GPIO.SSEL = 1; // read image GPIO.SSEL = 0; SPISEND(0x01); for (i=0; i<(160*160); i++) image[i] = SPIREAD(0x01);...

  • Page 28: Timing Characteristics

    PRELIMINARY SF104-P01 } until (byte.bit6 == 0); // wait until DETOK bit goes away GPIO.SSEL = 1; } // end of main Timing characteristics   5.1 SPI interface timing General SPI Timing Instruction without return data Instruction with return data SF3013M Fingerprint Image Sensor Module User Manual Page - 28...
  • Page 29 PRELIMINARY SF104-P01 Terminating read by applying new command SF3013M Fingerprint Image Sensor Module User Manual Page - 29...
  • Page 30 PRELIMINARY SF104-P01 SPI timing parameters SYMBOL PARAMETER NOTE MIN. TYP. MAX. UNITS Clock frequency Reset time Rise time for digital inputs Fall time for digital inputs Frequency for SPI clock. SPI_SCK Part of SPI_CK clock period, SCKL during which SPI_CK is low. Part of SPI_CK clock period, SCKH during which SPI_CK is high.

  • Page 31: Maximum Ratings And Operating Condition

    PRELIMINARY SF104-P01 Maximum ratings and operating condition 6.1 Maximum rating Symbol Parameter Conditions Value Unit Supply voltage -0.3 to 3.3 Supply voltage of I/O -0.3 to 3.3 VDDIO Input pin voltage 1 (SPICLK, (Note1) -0.3 to V +0.3 VDDIO SPIDI, SPICSn) Input pin voltage 2 (RSTn) (Note2) -0.3 to V...

  • Page 32: Electrical Characteristics

    PRELIMINARY SF104-P01 4Mhz) System Clock ESDKV ESD protection Electrical characteristics Symbol Parameter Conditions MAX Unit Digital inputs High level input voltage 0.8*VDD Low level input voltage 0.2*VDD High level input current Low level input current Input capacitance Digital outputs High level output voltage = 1mA 0.8*VDD Low level output voltage...

  • Page 33: Environmental Limits

    PRELIMINARY SF104-P01 Table 9-1 Requirements for ESD immunity The ESD immunity is achieved by the combination of a surface coating with ability to withstand > ±6 kV, a drive frame and a primary drive electrode that leads charge away from the sensor.

  • Page 34: Packaging Information

    PRELIMINARY SF104-P01 Table 9-3 Requirements for mechanical durability   Packaging information   9.1 The SF104 packaging Size:13.4mm*13.9mm*1.1mm (with FPC) 9.2 Signal definition Pin# Description INTn SPIDO (SPIMISO) RSTn SPICLK SPIDI (SPIMOSI) SPICSn VDDIO SF3013M Fingerprint Image Sensor Module User Manual Page - 34...

  • Page 35: Part Drawing

    Output Master In Slave Out (SPIMISO) System power. Voltage supply for core Input operation. A LOW on this pin resets the SF104x to take RSTn Input on its default states The SPI clock rate provided by the master SPICLK Input must not exceed 18MHz.
  • Page 36 PRELIMINARY SF104-P01 Pin Name Type Pin Description different application, SPICLK should be adjusted for best image quality. Power Ground SPIDI Input Master Out Slave In (SPIMOSI) SPICSn Input Chip select for SPI Connect ESD pin to Ground for System power. This voltage is supplied for IO interface operation.

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