Related Manuals for e2v ELIIXA+ 16K/8K CXP MONO
Summary of Contents for e2v ELIIXA+ 16K/8K CXP MONO
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Page 1: User Manual
ELIIXA+ Family CMOS Multi-Line Camera USER MANUAL ELIIXA+ 16K/8K CXP MONOCHROME e2v.com/cameras... -
Page 2: Table Of Contents
Table of Contents 1 CAMERA OVERVIEW ........................ 5 1.1 Features ..............................5 1.2 Key Specifications ............................ 5 1.3 Description............................... 6 1.4 Typical Applications ..........................6 1.5 Models ..............................6 2 CAMERA PERFORMANCES ....................... 7 2.1 Camera Characterization ......................... 7 2.2 Image Sensor ............................8 2.3 Multi-Lines modes ........................... - Page 3 7.2.3 Multi-Line Gain ..........................22 7.2.4 HDR mode (Only available on “BH0” Models) ................22 7.2.5 Test Image Pattern Selector ......................23 7.3 Acquisition Control ..........................24 7.3.1 External Triggers on GPIO Connector ..................... 25 7.3.2 CXP Trigger Line ..........................25 7.3.3 Scan Direction ..........................
- Page 4 B.3 Timing Values ............................54 Appendix C. HDR Mode ......................55 C.1 HDR Block .............................. 55 C.2 Example with Ratio 2 and 10bits output ....................55 C.3 HDR With LUT 10bits => 8bits ....................... 56 C.4 Example of difference between “AB” and “C” Line : ................56 Appendix D.
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Page 5: Camera Overview
1 CAMERA OVERVIEW 1.1 Features Cmos Sensor 4x 16384 Pixels, 5 x 5µm Multi-Line structure (1, 2 or 4 lines to adapt the sensitivity) Interface : CoaXPress® (4x Links) Line Rate : Up to 100000 l/s ... -
Page 6: Description
CE, FCC and RoHS compliant 1.3 Description e2v’s next generation of line scan cameras are setting new, high standards for line rate and image quality. Thanks to e2v’s recently developed multi line CMOS technology, the camera provides an unmatched 100 000 lines/s in a 16k pixel format and combines high response with an extremely low noise level; this delivers high signal to noise ratio even when short integration times are required or when illumination is limited. -
Page 7: Camera Performances
2 CAMERA PERFORMANCES 2.1 Camera Characterization Unit Mode 1S (0dB) Mode 2S (0dB) Mode 4S (0dB) Typ. Typ. Typ. Dark Noise RMS Dynamic Range 2394:1 3412:1 2730:1 Readout Noise Full Well Capacity 13650 27300 27300 Peak Response LSB/ (660nm) (nJ/cm2) Non Linearity Without Flat Field Correction : FPN rms... -
Page 8: Image Sensor
2.2 Image Sensor ADC Column The Eliixa+ 16k sensor is composed of two pairs Memory Node of sensitive lines. Each pair of lines use the same Analog to Digital Column converter (ADC Pixel Line A Column). An appropriate (embedded) Time delay in the exposure between each line this Pixel Line B allows to combine two successive exposures in... -
Page 9: Response & Qe Curves
2.4 Response & QE curves 2.4.1 Quantum Efficiency Quantum Efficiency 1060 2.4.2 Spectral Response Single Modes : 1S, 2S, 4S Response in 16k Pixels 5µm LSB12bits/(nJ/cm2)) 1000 1050 1100 ELIIXA+ 16 CXP M – R K – 06/2017 ANUAL A G E... - Page 10 Binning Modes : 1SB, 2SB Response in 8k Pixels 10µm LSB12bits/(nJ/cm2)) 1200 1100 1000 1000 1050 1100 ELIIXA+ 16 CXP M – R K – 06/2017 | 10 ANUAL A G E...
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Page 11: Camera Hardware Interface
3 CAMERA HARDWARE INTERFACE 3.1 Mechanical Drawings The Step file is available on the web : www.e2v.com/cameras ELIIXA+ 16 CXP M – R K – 06/2017 | 11 ANUAL A G E... -
Page 12: Input/Output Connectors And Led
Sensor alignment Z = -9.4 mm ±100µm X = 9 mm ±100 µm Y = 50mm ±100 µm Flatness ±50 µm Rotation (X,Y plan) ±0,1° Tilt (versus lens mounting plane) 50µm 3.2 Input/output Connectors and LED USB Connector For Firmware upgrade Trigger Connector Multi-Colored LED... -
Page 13: Power Over Coaxpress
3.2.1 Power Over CoaXPress The ELIIXA+ CXP is compliant with the Power Over CoaXPress : There is no Power connector as the power is delivered through the Coaxial Connectors 1 and 2. In the Standard, the Power Over CoaXPress allows to deliver 13W (under 24V) per Channel. The ELIIXA+ CXP requires 18W then two connectors are required for the power : The two first are used for this purpose. -
Page 14: Trigger Connector
3.2.3 Trigger Connector Camera connector type: Hirose HR10A-7R-5SB or compliant Cable connector type: Hirose HR10A-7P-5P (male) or compliant, Provided with the Camera Signal LVDS IN1+ / TTL IN1 LVDS IN1- LVDS IN2+ / TTL IN2 LVDS IN2- Receptacle viewed from camera back IN1/IN2 are connected respectively to Line0/Line1 and allow to get external line triggers or the forward/Reverse “Live”... -
Page 15: Standard Conformity
A 10m CoaXPress Cable for the data transfer, certified at 6Gb/s e2v recommends using the same configuration to ensure the compliance with the following standards. 4.1 CE Conformity The ELIIXA+ cameras comply with the requirements of the EMC (European) directive 2004/108/CE (EN50081-2, EN 61000-6-2) (see next page). -
Page 16: Getting Started
There is no CDROM delivered with the Camera : This User Manual , and any other corresponding documents can be dowlaoded on the Web site. Main Camera page : www.e2v.com/cameras Select the appropriate Camera Page (ELIIXA+) 5.2 Setting up in the system... -
Page 17: Camera Software Interface
6 CAMERA SOFTWARE INTERFACE The ELIIXA+ CoaxPress Camera is compliant with GenICam 2.1 and the SFNC 1.5 standards. This means that the Camera embeds its own definition and parameter description in an xml file. Most of these Parameters are compliant with the SNFC. The specific parameters (non SNFC) are still compliant with GenICam and can be detailed through the GenICam API process to the application. -
Page 18: Camera Commands
7 Camera Commands 7.1 Device Control These are Identification values of the Camera. They can be accessed in the “Device Control” section Size Feature CXP @ R/W Description bytes 0x02000 DeviceVendorName RO Get camera vendor name as a string (including ‘\0’) Boostrap 0x02020 DeviceModelName... - Page 19 or Tap balance (available only for integrator/user mode) Bit 9: true if a an underflow occurs during FFC calibration StatusWarningUnderflow or Tap balance (available only for integrator/user mode) Status2V5 Bit 10: true if 2V5 failure CC3 Scrolling direction Bit 11: 0 : forward, 1: reverse StatusErrorHardware Bit 16 : true if hardware error detected A standby mode, what for ?
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Page 20: Image Format
7.2 Image Format Size Feature CXP @ R/W Description bytes Mapped on SensorWidth : 16384 or 8192 in binning Width 0x07000 mode Height 0x07004 AcquisitionMode 0x07008 RW 1: Continuous AcquisitionStart 0x0700C WO 0: Start the acquisition AcquisitionStop 0x07010 WO 0: Stop the acquisition 0x0101: Mono8 PixelFormat 0x07014... -
Page 21: Structure Of The Sensor
Size Feature CXP @ R/W Description bytes 0: HDR Ratio 1 (or x2) 1: HDR Ratio 2 (or x4) HDR Ratio 4 (or x8) HDR Ratio 8 (or x16) 7.2.1 Structure of the Sensor FPGA Web Direction In 2S Mode, the summation of the two lines is done in the FPGA : B+C Memory node Pixel Line A... -
Page 22: Multi-Line Gain
7.2.3 Multi-Line Gain The Multi-Line Gain is a feature that can be used only when the Top and the Bottom of the Sensor are used and summed in the FPGA to increase the sensitivity (2S, 4S and 2SB Modes) The Multi-Line Gain of x1/2 is applied in the FPAG just before the summation of the Top and Bottom Information of the Sensor. -
Page 23: Test Image Pattern Selector
Ratio 1 : Equivalent to x2 ratio between Top and Bottom or 1 bit in the Dynamic Ratio 2 : Equivalent to x4 ratio between Top and Bottom or 2 bit in the Dynamic Ratio 4 : Equivalent to x8 ratio between Top and Bottom or 3 bit in the Dynamic ... -
Page 24: Acquisition Control
7.3 Acquisition Control The Acquisition Control section describes all features related to image acquisition, including the trigger and exposure control. It describes the basic model for acquisition and the typical behavior of the device. Feature CXP @ Size Description bytes Set line period, from from 1 (0,1µs) to 65535 (6553,5µs), LinePeriod 0x08400... -
Page 25: External Triggers On Gpio Connector
If the single CoaxPress Trigger is used, the Synchronization mode using 2xTriggers can’t be used. Camera Line0 Trigger GPIO module modul Line1 Line2 modul Logical Unit HW Trigger IO control source Line0 - Debounce - Inverter Line0 & Line0 Line1 - rescaler Line1 ≥1... -
Page 26: Scan Direction
7.3.3 Scan Direction Forward/reverse information has to be set correctly as soon as one of the following modes : “2S”, “4S” or 2SB of the sensor is set. In these modes, the sensor/Camera need to know what is the real order of the lines for the exposure delays. -
Page 27: Full Exposure Control Mode
7.3.4 Full Exposure Control Mode The Full Exposure Control In 4S Sensor Mode, the Sensor is working as a double TDI (Time Integration Delay) : The two Top Pixels and the two bottom Pixels are working together in TDI with a delay between their exposure and outputting by the same Memory node and ADC. - Page 28 Not relevant. Prog_Tint has to be smaller than Tper. The sensor is in full exposure and the gain applied on the output is fixed by the User = G (max. x4) If Tper < 4 x Max (TPer , Prog_Tint) + 10µs mini The Sensor works in Full Exposure during the whole Line Period (LP) and the gain applied on the...
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Page 29: Genicam Triggers
7.3.5 GenICam Triggers Feature Name CXP @ Size Bit field Description bytes ExposureMode 0x08414 [31-30] Operation mode for the exposure control: 0: Off 1: Timed 2: TriggerWidth 3: TriggerControlled TriggerSelector Select the trigger to control : , - ExposureStart, - ExposureStop, - ExposureActive TriggerSelector = ExposureActive TriggerMode... -
Page 30: Trigger Presets
7.3.6 Trigger Presets Several triggers are pre-defined to help the user to define its trigger configuration. For external trigger, 5 modes are available (Same than in the Camera Link version) : Exposure Acquisition TriggerSelector Mode Mode ExposureActive ExposureStart ExposureStop TriggerMode TriggerMode TriggerMode Mode 0... -
Page 31: Rescaler
7.3.7 Rescaler Feature Name CXP @ Size R/W Bit field Description bytes TriggerRescalerSource 0x08540 [31-30] RescalerSize (see 7.3.7) Bit0: 0: line0 selected for rescaler 1: line1 selected for rescaler Bit1: Bypass Rescaler TriggerRescalerMultplier [29-18] mult factor for rescaler function Rescaler will create "mult" pulse between input trig TriggerRescalerDivider [17-6] div factor for rescaler function... -
Page 32: Digital I/O Control
The MaxSampledPeriod must be as close as possible to the trigger period while still being longer rescalerSize MaxSampledPeriod = 20ns x granularity x 2 The array below gives the MaxSampledPeriod in millisecond : granularity Precision (ns) Max Sample Period (ms) 1.31 5.24 20.97... -
Page 33: Counters & Timers Control
7.5 Counters & Timers Control 7.5.1 Counters Here is a following description of the counters : Clock Counter Event CounterEventSource CounterEnd CounterDuration Start / CounterTriggerSource + polarity Reset Feature Name CXP @ Size Description bytes field CounterSelector Not a Select which counter to configure {Counter1, register Counter2} CounterSelector = Counter1... - Page 34 Feature Name CXP @ Size Description bytes field 3: LevelHigh 4: LevelLow CounterStatus [15-13] Get counter status : 0: CounterIdle 1: CounterTriggerWait 2: CounterActive, 3: CounterCompleted 4: CounterOverflow CounterDuration 0x084B4 [31-0] Set the counter duration (or number of events) before CounterEnd event is generated CounterReset 0x084B8 Reset the selected counter...
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Page 35: Timers
7.5.2 Timers Here is a following description of the Timers : Event Timer Start / TimerTriggerSource + Polarity TimerEnd TimerDuration Reset + TimerDelay before start TimerActive counting Trigger source TimerEnd Timer TimerActive Timer Duration Duration Timer Timer Delay Delay Feature Name CXP @ Size Bit field Description... -
Page 36: Gain And Offset
7.6 Gain and Offset Sensor FPGA Quarter (Tap) LUT or Preamp Gains Contrast Exp. Adjust Gain Offset Gain Gain Gain Offset Gain Pixel Action on whole line Action per pixel Action per Sensor’s Quarter Analog Gain in the ADC The only analog Gain available in the ELIIXA+ is located at the sensor level, in the ADC converter. - Page 37 Feature CXP @ Size R/W Description bytes GainAbs 0x08600 Set pre amplifier gain to: GainSelector= AnalogAll 0: (-12dB) 1: (-6dB) 2: (0dB) (analog gain) Change balances and compensation GainAbs 0x08604 Set gain from 0dB(0) to +8 dB (6193) GainSelector= gainAll Gain Abs 0x08608 Set contrast expansion digital gain from 0 (0 dB) to...
- Page 38 ROI Gain : How does it works ? The ROI Gain feature comes in addition with the FFC (it’s applied and calculated after). The maximum complementary Gain ix x2. It can be applied in 2 commands : > First set the ROI Gain value : command address is : 0x8624 >...
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Page 39: Flat Field Correction
7.7 Flat Field Correction Size Feature CXP @ R/W Description bytes FFCEnable 0x08800 0: Disable Flat Field Correction (“False”) - In user/integrator mode : the factory FFC bank is written into the FPGA and the FFC stays enabled 1: Enable Flat Field Correction (“True”) FPNReset 0x08804 0: Reset FPN coefficients... - Page 40 How is performed the Flat Field Correction ? What is the Flat Field correction (FFC) ? The Flat Field Correction is a digital correction on each pixel which allows : To correct the Pixel PRNU (Pixel Response Non Uniformity) and DSNU (Dark Signal Non Uniformity) ...
- Page 41 Adjustment gain User Target value 3020 Standard FFC computed on the max of the line How to perform the Flat Field Correction ? Pixels FPN/DSNU Calibration > Cover the lens > Launch the FPN Calibration : Grab and calculation is performed in few seconds PRNU Calibration The User must propose a white/gray uniform target to the Camera (not a fixed paper).
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Page 42: Automatic Calibration
FFC Adjust : A good usage. When there are several Cameras to set up in a system on a single line, the most difficult is to have a uniform lightning whole along the line. If each Camera performs its own Flat field correction, relative to the max of each pixel line, the result will be a succession of Camera lines at different levels. -
Page 43: Save & Restore Ffc In User Memory Banks
7.7.3 Save & Restore FFC in User Memory Banks Feature CXP @ Size R/W Description bytes RestoreFFCFromBank 0x08C10 Restore current FFC (including FPN and FFCGain) from FFC bank number <val>, from 1 to 8; <val> comes from FFC SetSelector 1,2,3,4,5,6,7,8: User Banks SaveFFCToBank 0x08C14 Save current FFC (including FPN and FFCGain) to FFC bank... -
Page 44: Look Up Table
7.8 Look Up Table The User can define an upload a LUT in the Camera that can be used at the end of the processing. The LUT is defined as a correspondence between each of the 4096 gray levels (in 12 bits) with another outputted value. - Page 45 LUT User Bank Usage Upload/load from/to a Txt file User Save User1 Ram Memory User2 Load User3 User4 At the power up : - Last User Bank used is loaded in RAM ELIIXA+ 16 CXP M – R K – 06/2017 | 45 ANUAL A G E...
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Page 46: Statistics And Line Profile
7.9 Statistics and Line Profile This function allows the User to get some statistics on a pre-defined ROI. On request, the Camera acquires and then calculates some key values as the min, the max, the average or the standard deviation in this Region of Interest. -
Page 47: Privilege Level
The Cameras are delivered in Integrator mode. They can be locked in User mode and a specific password is required to switch back the Camera in Integrator mode. This password can be generated with a specific tool available from the hotline (hotline-cam@e2v.com) Feature... -
Page 48: Save & Restore Settings In User Memory Banks
7.11 Save & Restore Settings in User Memory Banks The settings (or Main configuration) of the Camera can be saved in 4x different User banks and one Integrator bank. This setting includes also the FFC and LUT enable parameters This function is available in the User Set Control section : Feature CXP @ Size... -
Page 49: Appendix
APPENDIX ELIIXA+ 16 CXP M – R K – 06/2017 | 49 ANUAL A G E... -
Page 50: Appendix A. Test Patterns
Appendix A. Test Patterns A.1 Test Pattern 1: Vertical wave The Test pattern 1 is a vertical moving wave : each new line will increment of 1 gray level in regards with the previous one. In 12 bits the level reaches 4095 before switching down to 0 ... -
Page 51: In 12 Bits (Medium) Format - No Binning (16384 Pixels)
A.2.2 In 12 bits (Medium) format – No Binning (16384 pixels) 4096 3072 2048 1024 2048 4096 6144 8192 10240 12288 14336 An increment of 1 LSB is made for each pixel. When it reaches 4095, turns back to 0 and starts again ELIIXA+ 16 CXP M... -
Page 52: In 8/12 Bits Full/Medium Format With Binning (8192 Pixels)
A.3.2 In 8/12 bits Full/Medium format with Binning (8192 Pixels) 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 7000 7500 8000 Pixel 0 : 32 Pixel 1 : 32 … Pixel 15 : 32 Pixel 16 : 33 Pixel 17 : 33 …... -
Page 53: Appendix B. Timing Diagrams
Appendix B. Timing Diagrams B.1 Synchronization Modes with Variable Exposure Time Synchro Mode Line Trigger CC1 or Internal Sync = 0 Sync = 1 (Exposure Time) Exposure Time Exposure Time Programmed Programmed ITC Trigger intProg Sync = 3 Line Triggers Sync = 4 Tint real... -
Page 54: Synchronisation Modes With Maximum Exposure Time
If T is the Line Period (internal or external coming from the Trigger line), in order to respect this line Period, the Exposure Time as to be set by respecting : T <= T Then, the real exposure time is : Tint real In the same way, The high level period of the Trig signal in sync=3 mode, T >= T... -
Page 55: Appendix C. Hdr Mode
Appendix C. HDR Mode C.1 HDR Block With the HDR Single Line Mode, the “HDR” is calculated in the camera as following : Line C (8bit) (12bit) Processing : Camera output FFC, HDR bloc interface HDR Output Gain (8, 10, 12bit) (12bit) Lines AB (8bit) (12bit) -
Page 56: Hdr With Lut 10Bits => 8Bits
C.3 HDR With LUT 10bits => 8bits Camera output The LUT could be used to compress the HDR output in 8bit. 1023 Camera 10b output without LUT Camera 8b output with 10b8b LUT illumination Saturation Lines AB Saturation Line C Lines AB used Line C used C.4 Example of difference between “AB”... -
Page 57: Appendix D. Data Cables
Appendix D. Data Cables CXP cables and the separate lanes of a CXP-multi-cable shall be coaxial with a characteristic impedance of 75Ω ± 4 Ω. When a series connection of CXP-cables is considered, all of the BNC connectors used have to be of the 75Ω... -
Page 58: Appendix E. Lenses Compatibility
Appendix E. Lenses Compatibility QIOPTICS (LINOS) Nominal Magnification M95 Focus tube Lens Reference Magnification Range Reference Part number Inspec.x. L 5.6/105 0,33 X 0,25 – 0,45 X 2408-012-000-41 0703-085-000-20 Inspec.x. L 5.6/105 0,5 X 0,4 – 0,65 X 2408-012-000-41 0703-084-000-20 Inspec.x. -
Page 59: Appendix F. Revision History
Rev J Full Exposure Control Gain tunable Version BA0 : 1.5.0 New Version BH0 with New Sensor and HDR Function : 2.0.1 Rev K New Teledyne-e2v Chart New Sensor version for BA0 EV71YC4MCP1605-BA0 : 2.0.2 EV71YC4MCP1605-BH0 : 2.0.2 ELIIXA+ 16 CXP M –...