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Abov AC30M1x64 User Manual

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32-bit Cortex-M0 based
Programmable Motor Controller
FlashROM 64/32KB / SRAM 4KB
AC30M1x64
AC30M1x32
USER MANUAL
Version 1.1.0
2016.8.17.

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Summary of Contents for Abov AC30M1x64

  • Page 1 32-bit Cortex-M0 based Programmable Motor Controller FlashROM 64/32KB / SRAM 4KB AC30M1x64 AC30M1x32 USER MANUAL Version 1.1.0 2016.8.17.
  • Page 2 ABOV Semiconductor for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of ABOV Semiconductor or others.

  • Page 3: Section 1.Introduction

    INTRODUCTION SECTION 1.INTRODUCTION ABOV Semiconductor 3 / 246...
  • Page 4 AC30M1x64/1x32 CHAPTER 1. OVERVIEW ABOV Semiconductor 4 / 246 4 / 246...

  • Page 5: Block Diagram

    32-bit computing to low cost system solution. AC30M1x64/1x32 provides 3-phase PWM generator units which are suitable to inverter motor drive system. Built-in 3- phase PWM generator controls one inverter motor. One 12-bit high speed ADC units with 12-channel analog multiplexed inputs support to get feedback information from motor.
  • Page 6 AC30M1x64/1x32 AN8/T2IO/T0IO/PA8 PC8/SDA AN9/T1IO/T3IO/PA9 PC7/SCL/T3IO AN10/PA10 PC1/SWDIO/TXD1 AN11/PA11 PC0/SWCLK/RXD1 nRESET/PC10 AC30M1464LBN AVDD/VDD AGND/GND LQFP-48 XOUT/T2IO/PC13 XIN/T3IO/PC12 PC9/CLKO SXIN/SDA/MISO/PD3 PC11/T0IO/BOOT SXOUT/SCL/MOSI/PD2 PC15/TXD0 SCK/PD1 PC14/RXD0 Figure 1.2 PIN LAYOUT (LQFP-48) ABOV Semiconductor 6 / 246 6 / 246...

  • Page 7: An8/T2Io/T0Io/Pa8

    OVERVIEW AN7/T1IO/PA7 PC7/SCL/T3IO AN8/T2IO/T0IO/PA8 PC1/SWDIO/TXD1 AN9/T1IO/T3IO/PA9 PC0/SWCLK/RXD1 AC30M1364LBN nRESET/PC10 PC11/T0IO/BOOT AC30M1332LBN AVDD/VDD PC15/TXD0 LQFP-32 AGND/GND PC14/RXD0 XOUT/T2IO/PC13 PB0/MPWMUH/SS XIN/T3IO/PC12 PB1/MPWMUL/SCK Figure 1.3 PIN LAYOUT (LQFP-32) ABOV Semiconductor 7 / 246...

  • Page 8: An9/T1Io/T3Io/Pa9

    AC30M1x64/1x32 AN7/T1IO/PA7 PC7/SCL/T3IO AN8/T2IO/T0IO/PA8 PC1/SWDIO/TXD1 AN9/T1IO/T3IO/PA9 PC0/SWCLK/RXD1 AC30M1364UB nRESET/PC10 PC11/T0IO/BOOT AC30M1332UB AVDD/VDD PC15/TXD0 QFN-32 AGND/GND PC14/RXD0 XOUT/T2IO/PC13 PB0/MPWMUH/SS XIN/T3IO/PC12 PB1/MPWMUL/SCK Figure 1.4 PIN LAYOUT (QFN-32) ABOV Semiconductor 8 / 246 8 / 246...

  • Page 9: Product Features

    OVERVIEW Product Features Product features of AC30M1x64/1x32 is below  High Performance Low-power Cortex-M0 Core  64/32KB Code Flash Memory − Endurance : 10,000 times at room temperature − Retention : 10 years  4KB SRAM  General Purpose I/O (GPIO) −...
  • Page 10 AC30M1x64/1x32 − LQFP-32 − QFN-32 Table 1.1 Device type Part Number Flash SRAM UART MPWM I/O Ports Package 1-unit AC30M1464LBN 64KB LQFP-48 12 ch 1-unit AC30M1364LBN 64KB LQFP-32 10 ch 1-unit AC30M1364UB 64KB QFN-32 10 ch 1-unit AC30M1332LBN 32KB LQFP-32...
  • Page 11 OVERVIEW ARCHITECTURE 1.3.1 Block Diagram AC30M1x64/1x32 Block diagram is shown as following. Debug Interface ( BOD ) Power Control 2K-Bytes nRESET Boot ROM Cortex-M0 64/32K-Bytes 4k-Bytes SysTick Timer Flash Memory SRAM NVIC AHB-Lite BUS APB BUS Watch-Dog Timer 12-Bit A/D Converter...

  • Page 12: Functional Description

    On chip 4KB 0-wait SRAM can be used for working memory space and program code can be loaded on this SRAM. Boot Logic The smart boot logic supports the flash programming. The AC30M1x64/1x32 can be entered by external boot pin and UART and SPI programming are available in boot mode. UART0 or SPI is used in boot mode communication.
  • Page 13 C communication. The master and the slave mode are supported. Universal Asynchronous Receiver/Transmitter (UART) The AC30M1x64/1x32 has 2 channels UART block. For accurate baud rate control, the fractional baud rate generator is provided. General PORT I/Os 16-bit PA, 8-bit PB, 16-bit PC and 4-bit PD ports are available and provide multiple functionality.
  • Page 14 AC30M1x64/1x32 Pin Description Below pin configuration contains two pair of power/ground pair and other dedicated pins. The multi-function pins have four selections of functions including GPIO. The configuration including pin ordering can be changed without notice. Table 1.2 Pin Description...
  • Page 15 PORT A Bit 9 Input/Output T3IO Timer 3 Input/Output T1IO Timer 1 Input/Output AIN9 Analog Input 9 PA10 IOUS PORT A Bit 10 Input/Output AIN10 Analog Input 10 PA11 IOUS PORT A Bit 11 Input/Output AIN11 Analog Input 11 ABOV Semiconductor 15 / 246...
  • Page 16 AC30M1x64/1x32 PC10 IOUS PORT C Bit 10 Input/Output nRESET External Reset Input Pull-up PC13 IOUS PORT C Bit 13 Input/Output T2IO Timer 2 Input/Output XOUT External Crystal Oscillator Output PC12 IOUS PORT C Bit 12 Input/Output T3IO Timer 3 Input/Output...

  • Page 17: Memory Map

    0x2000 0000 0x4000 0600 0x0F00 0600 64/32 DIVIDER 0x4000 0500 SRAM CODE 0x0F00 0000 0x0000 0000 0x4000 0300 CODE 0x4000 0200 0x0001 0000 0x4000 0100 FLASH ROM(64/32KB) Reserved 0x0000 0000 0x4000 0000 Figure 1.6 Memory Map ABOV Semiconductor 17 / 246...
  • Page 18 AC30M1x64/1x32 CHAPTER 2. ABOV Semiconductor 18 / 246 18 / 246...
  • Page 19 Cortex-M0 Core CPU core is supported from the ARM Cortex-M0 processor which provides a high-performance, low-cost platform. Document DDI0432C from ARM provides detail information of Cortex-M0. ABOV Semiconductor 19 / 246...

  • Page 20: Interrupt Controller

    AC30M1x64/1x32 Interrupt Controller Table 2.1 Interrupt Vector Map Priority Vector Address Interrupt Source 0x0000_0000 Stack Pointer 0x0000_0004 Reset Address 0x0000_0008 NMI Handler 0x0000_000C Hard Fault Handler 0x0000_0010 MPU Fault Handler 0x0000_0014 BUS Fault Handler 0x0000_0018 Usage Fault Handler 0x0000_001C 0x0000_0020...
  • Page 21 Interrupt Priority Level Registers. Each Interrupt Priority Level Register occupies 1 byte (8 bits). NVIC registers in the Cortex-M0 processor can only be accessed using word-size transfers, so for each access, four Interrupt Priority Level Registers are accessed at the same time. ** __NVIC_PRIO_BITS = 2 ABOV Semiconductor 21 / 246...

  • Page 22: Boot Mode

    AC30M1x64/1x32 CHAPTER 3. Boot Mode ABOV Semiconductor 22 / 246 22 / 246...

  • Page 23: Boot Mode Pins

    BOOT MODE Boot Mode Pins AC30M1x64/1x32 has boot mode option to program internal flash memory. Boot mode can be entered by setting BOOT pin to ‘L’ at reset timing. (Normal state is ‘H’) The boot mode supports UART boot and SPI boot.
  • Page 24 AC30M1x64/1x32 Boot Mode Connections User can design target board using any of boot mode ports – UART or SPI. Followings are sample connection diagrams of boot mode. 2.2~5.5V HOST 10kΩ nRESET RESET BOOT BOOT AC30M1x64 AC30M1x32 RXD0 TXD0 Figure 3.1 Connection diagram of UART Boot 2.2~5.5V...
  • Page 25 BOOT MODE ISP Mode Connections User can design target board using any of ISP mode port. 2.2~5.5V E-PGM+ 10kΩ nRESET nRESET AC30M1x64 AC30M1x32 SWCLK SWCLK SWDIO SWDIO Figure 3.3 Connection diagram of ISP and E-PGM+ ABOV Semiconductor 25 / 246...

  • Page 26: Section 2.Peripherals

    AC30M1x64/1x32 SECTION 2.PERIPHERALS ABOV Semiconductor 26 / 246 26 / 246...

  • Page 27: System Control Unit (Scu)

    System Control Unit - SCU CHAPTER 1. SYSTEM CONTROL UNIT (SCU) ABOV Semiconductor 27 / 246...
  • Page 28 AC30M1x64/1x32 OVERVIEW The AC30M1x64/1x32 has built-in intelligent power control block which manages system analog blocks and operating modes Internal reset and clock signals are controlled by SCU block to maintain optimize system performance and power dissipation. SCU MODE APB BUS...

  • Page 29: Clock System

    System Control Unit - SCU CLOCK SYSTEM AC30M1x64/1x32 has two main operating clocks. One is HCLK which supplies the clock to CPU and AHB bus system. The other one is PCLK which supplies the clock to Peripheral systems. User can control the clock system variation by software. Figure 1.2 shows the clock system of the chip. And Table 1.1 shows clock source descriptions.
  • Page 30 AC30M1x64/1x32 40 MHz High Speed Internal OSC 40 kHz Low Speed Internal OSC 1.2.1 HCLK clock domain HCLK clock feeds the clock to the CPU and AHB bus. Cortex-M0 CPU requires 2 clocks related with HCLK clock. FCLK and HCLK. FCLK is free running clock and it is always running except power down mode. HCLK can be stopped in the sleep mode and power down mode.
  • Page 31 Flash read access time is one of limitation factor for the performance. The wait control recommendation is provided in Table 1.2. Table 1.2 Flash wait control recommendation FM.CFG.WAIT FLASH Access Wait Available Max System clock frequency 0 clock wait ~20MHz 1 clock wait ~40MHz 2 clock wait ~40MHz ABOV Semiconductor 31 / 246...
  • Page 32 RESET AC30M1x64/1x32 has two system reset. One is the cold reset by POR which is effective during power up or down sequence. The other reset is the warm reset which is generated by several reset sources. The reset events make the chip to turn initial state.
  • Page 33 SCU.PRER register. The reset can be masked independently. PIN_RSTB WARM_RSTB_CNT 0.4 msec WARM_RSTB Typical SYS_RSTB BOOTROM EXCUTION 0.4 msec 42.1 msec Typical Typical MAIN CODE START 42.5msec Typical Figure 1.5 Warm reset diagram ABOV Semiconductor 33 / 246...
  • Page 34 AC30M1x64/1x32 1.3.3 Reset Tree Cold Reset VDDEXT 4.25 msec CM0 PORESETn Counter SYSRESETn SCU.RSER[0] MOSC FAIL DETECTOR SCU.RSER[1] MCLK FAIL DETECTOR SCU.RSER[2] CM0 SYSRESETn WDT RESET REQUEST DETECTOR SCU.RSER[3] SW RESET REQUEST DETECTOR SCU.RSER[4] 0.4 msec Counter nRESET PIN RESET DETECTOR SCU.RSER[6]...
  • Page 35 EVENT EVENT RESET INITIALIZATION EVENT WAKE-UP PCU WAKE-UP EVENT EVENT POWER SLEEP DOWN SCB.SCR[2]* = 0 SCB.SCR[2]* = 1 *note) SCB.SCR is System Control Register in System Control Block Figure 1.7 Operation Mode Block Diagram ABOV Semiconductor 35 / 246...

  • Page 36: Run Mode

    AC30M1x64/1x32 1.3.5 RUN Mode This mode is to operate the CPU and the peripheral hardware by using the high-speed clock. After reset followed by INIT state, it is entered into RUN mode. ABOV Semiconductor 36 / 246 36 / 246...
  • Page 37 PER and PCER register. SLEEP MODE ENTER SCB.SCR[2]* = 0 (ENTER SLEEP MODE) Wait for Interrupt signal WAKE UP *note) SCB.SCR is System Control Register in System Control Block Figure 1.8 Sleep mode sequence ABOV Semiconductor 37 / 246...
  • Page 38 AC30M1x64/1x32 1.3.7 POWER-DOWN Mode All the internal circuits are entered the stop state. Power down operation has special power off sequence as below picture. POWER DOWN MODE ENTER STOP1 STOP2 STOP1 or STOP2 FM.MR[7:0] = TRIM MODE FM.MR[7:0] = TRIM MODE SCU.VDCCON[25]=STOP1...

  • Page 39: Pin Description

    System Control Unit - SCU PIN DESCRIPTION Table 1.3 SCU pins PIN NAME TYPE DESCRIPTION nRESET External Reset Input XIN/XOUT External Crystal Oscillator SXIN/SXOUT External sub-Crystal Oscillator STBO Stand-by Output Signal CLKO Clock Output Monitoring Signal ABOV Semiconductor 39 / 246...

  • Page 40: Base Address

    AC30M1x64/1x32 REGISTERS The base Address of SCU is 0x4000_0000 and register map is described in Table.1.4 Table1.4. Base address of SCU NAME BASE ADDRESS 0x4000_0000 Table 1.5 SCU Register Map NAME OFFSET TYPE DESCRIPTION RESET VALUE 0x0004 System Mode Register...
  • Page 41 Output High when chip is in normal Output High when chip is in Power Down Output Low when chip is in normal SWRST Internal soft reset activation bit (check RSER[4] for reset) Normal operation Internal soft reset generated and auto cleared ABOV Semiconductor 41 / 246...
  • Page 42 AC30M1x64/1x32 1.5.3 WUER Wakeup Source Enable Register Enable wakeup source when the chip is in the Power Down mode. Wakeup sources which will be used the source of chip wakeup should be enabled in each bit field. If the source is used as a wakeup source, the corresponding bit should be written with ‘1’.
  • Page 43 No wakeup event Wakeup event was generated WDTWU Status of wakeup source of WDT event No wakeup event Wakeup event was generated LVDWU Status of wakeup source of LVD event No wakeup event Wakeup event was generated ABOV Semiconductor 43 / 246...
  • Page 44 AC30M1x64/1x32 1.5.5 RSER Reset Source Enable Register The reset source to the CPU can be selected by RSER register. When writing ‘1’ in the bit field of each reset source, the reset source event will be transferred to reset generator. When writing ‘0’ in the bit field of each reset source, the reset source event will be masked and not generate the reset event.
  • Page 45 Write : Clear the status LVDRST LVD reset status bit Read : Reset from this event was not exist Write : no effect Read :Reset from this event was occurred Write : Clear the status ABOV Semiconductor 45 / 246...
  • Page 46 AC30M1x64/1x32 1.5.7 PRER1 Peripheral Reset Enable Register 1 The reset of each peripheral by event reset, can be masked by user setting. PRER1/PRER2 register will control the enable of the event reset. If the corresponding bit is ‘1’, the peripheral corresponded with this bit, accepts the reset event.
  • Page 47 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADC reset enable MPWM0 MPWM reset enable UART1 UART1 reset enable UART0 UART0 reset enable C reset enable SPI reset enable ABOV Semiconductor 47 / 246...
  • Page 48 AC30M1x64/1x32 1.5.9 PER1 Peripheral Enable Register 1 To use peripheral unit, it should be activated by writing ‘1’ to the correspond bit in the PER1/PER2 register. Before the activation, the peripheral will stay in reset state. All the peripherals enabled by default. To disable the peripheral unit, write ‘0’ to the correspond bit in the PER1/PER2 register, and then the peripheral enter the reset state.
  • Page 49 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADC function enable MPWM MPWM function enable UART1 UART1 function enable UART0 UART0 function enable C function enable SPI function enable ABOV Semiconductor 49 / 246...
  • Page 50 AC30M1x64/1x32 1.5.11 PCER1 Peripheral Clock Enable Register 1 To use peripheral unit, its clock should be activated by writing ‘1’to the corresponding bit in the PCER1/PCER2 register. Before enabling its clock, the peripheral won’t operate properly. To stop the clock of the peripheral unit, write ‘0’to the correspond bit in the PCER1/PCER2 register, and then the clock of the peripheral is stopped.
  • Page 51 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADC clock enable MPWM MPWM clock enable UART1 UART1 clock enable UART0 UART0 clock enable C clock enable SPI clock enable ABOV Semiconductor 51 / 246...

  • Page 52: System Clock Control Register

    AC30M1x64/1x32 1.5.13 CSCR Clock Source Control Register The AC30M1x64/1x32 has multiple clock sources to generate internal operating clocks. Each clock sources can be controlled by CSCR register. This register is 8-bit register. CSCR=0x4000_0040 SOSCCON LSICON HSICON MOSCCON SOSCCON External crystal sub oscillator control...
  • Page 53 External main oscillator fail interrupt External main oscillator fail interrupt not occurred Read : External main oscillator fail interrupt is pending Write : Clear pending interrupt MOSCSTS External main oscillator status Not oscillate External main oscillator is working normally ABOV Semiconductor 53 / 246...
  • Page 54 AC30M1x64/1x32 1.5.16 NMIR NMI Control Register NMIR is the non-maskable interrupt configuration register which can be set by software. There are five kinds of interrupt sources from MPWM, WDT and SCU. It will jump to NMI handler if Selected NMI event occurred and it must check event status.
  • Page 55 Clock Output Register The AC30M1x64/1x32 can drive the clock from internal MCLK clock with dedicated post divider. To use CLKO output function, it should be set as CLKO that has output mode in Pin Mux. Clock Output Register is 8-bit register.
  • Page 56 AC30M1x64/1x32 1.5.18 VDCCON VDC Control Register On chip VDC control register. VDCTRIM is used for the trim value of VDC output. To modify VDCTRIM bit, VDCTE should be write ‘1’ simultaneously. VDCWDLY value can be written with writing ‘1’ to VDCDE bit simultaneously. To change VDCCON register value, it has to enter TRIM mode.
  • Page 57 VDDEXT level is under than LVD level LVDEN LVD Function enable LVD is not enabled LVD is enabled CAUTION) This LVD Voltage level is not recommanded. Because it sometimes can change LVD detect level at high temperature. ABOV Semiconductor 57 / 246...
  • Page 58 AC30M1x64/1x32 1.5.20 HSIOSCTRIM High Speed Internal OSC Trim Register Internal oscillator frequency trim register This register is 32-bit register. HSIOSCTRIM=0x4000_006C 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BISCON Build in self calibration function enable.
  • Page 59 XTAL_COMP[15:0] XTAL Compare value Calibration supports below configurations on the table Table 1.6 BISC count value XTAL FREQ TARGET FREQ UPDATE PERIOOD XTAL_COMP INTOSC_COMP Nano Sec Count Value Count Value 10,000 1,000,000 7999 39999 10,000 ABOV Semiconductor 59 / 246...
  • Page 60 AC30M1x64/1x32 1.5.22 MOSCR External Main Oscillator Control Register External main crystal oscillator has two characteristics. For the noise immunity, NMOS amp type is recommended and for the low power characteristic, INV amp type is recommended. This register is 16-bit register.
  • Page 61 External Mode Status Register External Mode Status Register shows external mode pin status while booting. This register is 8-bit register. EMODR=0x4000_0084 Reserved Reserved BOOT BOOT BOOT pin level BOOT(PC11) pin is low BOOT(PC11) pin is high ABOV Semiconductor 61 / 246...
  • Page 62 MCCR1 Miscellaneous Clock Control Register 1 The AC30M1x64/1x32 can drive the clock from internal MCLK clock with dedicated post divider. STCSEL bits and STCDIV bits of MCCR1 are used as SYSTICK external clock source. This register is 32-bit register. MCCR1=0x4000_0090...
  • Page 63 Miscellaneous Clock Control Register 2 The AC30M1x64/1x32 can drive the clock from internal MCLK clock with dedicated post divider. PWMCSEL bits and PWMDIV bits of MCCR2 are used as MPWM clock source. If it is used MPWM, it must set this register. This register is 32- bit register.
  • Page 64 Miscellaneous Clock Control Register 3 The AC30M1x64/1x32 can drive the clock from internal MCLK clock with dedicated post divider. TIMERCSEL bits and TIMERDIV bits of MCCR3 are used as TIMER external clock source. WDTCSEL bits and WDTDIV bits of MCCR3 are used as WDT external clock source.
  • Page 65 MCCR4 Miscellaneous Clock Control Register 4 The AC30M1x64/1x32 can drive the clock from internal MCLK clock with dedicated post divider. PxDCSEL bits and PxDDIV bits of MCCR4 are used as PORT debounce clock source. This register is 32-bit register. MCCR4=0x4000_009C...
  • Page 66 MCCR5 Miscellaneous Clock Control Register 5 The AC30M1x64/1x32 can drive the clock from internal MCLK clock with dedicated post divider. PxDCSEL bits and PxDDIV bits of MCCR5 are used as PORT debounce clock source. This register is 32-bit register. MCCR5=0x4000_00A0...
  • Page 67 Miscellaneous Clock Control Register 7 The AC30M1x64/1x32 can drive the clock from internal MCLK clock with dedicated post divider. ADCCSEL bits and ADCDIV bits of MCCR7 are used as ADC external clock source. UARTCSEL bits and UARTDIV bits of MCCR7 are used as UART clock source.
  • Page 68 AC30M1x64/1x32 Functional Description 1.6.1 Built in self calibration Self-calibration block has 4-fine trim value which can be configurable. The calibration value will be changed until the frequency of INTOSC cross the target frequency level. 8 steps up trim and 8 steps down trim are available with 0.7% difference in each step.
  • Page 69 Port Control Unit - PCU CHAPTER 2. PORT CONTROL UNIT (PCU) ABOV Semiconductor 69 / 246...
  • Page 70 AC30M1x64/1x32 OVERVIEW PCU (Port Control Unit) controls the external I/Os as below  Set pin function mux  Set external signal directions of each pins  Set interrupt trigger mode for each pins  Set internal pull-up register control and open drain control...
  • Page 71 Open-drain Enable Input mode Port MUX GPIO output Function 1 output Function 2 output Function 3 output Analog disable Function input Debounce Logic Debounce enable Debounce count Figure 2.3 I/O Port Block Diagram (General I/O pins) ABOV Semiconductor 71 / 246...

  • Page 72: Pin Multiplexing

    AC30M1x64/1x32 Pin Multiplexing GPIO pins have alternative function pins. Below table shows pin multiplexing information. Table 2.1 GPIO Alternative function FUNCTION PORT PA0* T2IO AIN0 PA1* T3IO AIN1 WDTO PA2* AIN2 STBO PA3* AIN3 PA4* AIN4 PA5* AIN5 PA6* T0IO...
  • Page 73 VMRG PC9* CLKO PC10 nRESET* PC11 BOOT* T0IO PC12* T3IO PC13* T2IO XOUT PC14* RXD0 PC15* TXD0 PD0* PD1* PD2* MOSI SXOUT PD3* MISO SXIN (*) mark indicates default pin setting. mark indicates secondary port ABOV Semiconductor 73 / 246...
  • Page 74 AC30M1x64/1x32 REGISTERS Base address of PCU block is 0x4000_1000. All the register access is globally masked by PORTEN register. In other to change register value except PORTEN register, the port access should be enabled in advance. Table 2.3 Base address of each port control...
  • Page 75 AIN4 PA5* AIN5 PA6* T0IO AIN6 PA7* T1IO AIN7 PA8* T2IO T0IO AIN8 PA9* T3IO T1IO AIN9 PA10 PA10* AIN10 PA11 PA11* AIN11 PA12 PA12* T0IO PA13 PA13* T1IO PA14 PA14* T2IO PA15 PA15* T3IO ABOV Semiconductor 75 / 246...
  • Page 76 AC30M1x64/1x32 2.3.2 PCB.MR PORT B Pin MUX Register PB port mode select register. This register must be set properly before use the port. Otherwise the port can’t guarantee its functionality. PCB.MR=0x4000_1100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 77 PC3* PC4* T0IO PC5* RXD1 T1IO PC6* TXD1 T2IO PC7* T3IO PC8* VMRG PC9* CLKO PC10 PC10 nRESET* PC11 PC11 BOOT* T0IO PC12 PC12* T3IO PC13 PC13* T2IO XOUT PC14 PC14* RXD0 PC15 PC15* TXD0 ABOV Semiconductor 77 / 246...
  • Page 78 AC30M1x64/1x32 2.3.4 PCD.MR PORT D Pin MUX Register PD port mode select register. This register must be set properly before use the port. Otherwise the port can’t guarantee its functionality. PCD.MR=0x4000_1300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 79 PORT n Pull-up Resistor Control Register (Except for PCC.PCR) Every pin in the port has on-chip pull-up resistors which can be configured by PCn.PCR registers. PCA.PCR=0x4000_1008, PCB.PCR=0x4000_1108 PCD.PCR=0x4000_1308 0000 PUEn Port pull-up control Disable pull-up resistor Enable pull-up resister ABOV Semiconductor 79 / 246...
  • Page 80 AC30M1x64/1x32 2.3.8 PCC.PCR PORT C Pull-up Resistor Control Register Every pin in the port has on-chip pull-up resistors which can be configured by PCC.PCR registers. PCC.PCR=0x4000_1208 0C03 PUEn Port pull-up control Disable pull-up resistor Enable pull-up resister 2.3.9 PCn.DER PORT n Debounce Enable Register Every pin in the port has a digital debounce filter which can be configured by PCn.DER registers.
  • Page 81 Pin interrupt mode Prohibit external interrupt Low level interrupt or Falling edge interrupt mode High level interrupt or Rising edge interrupt mode Both of rising and falling edge interrupt mode. Not support for level trigger mode ABOV Semiconductor 81 / 246...
  • Page 82 AC30M1x64/1x32 2.3.13 PORTEN Port Access Enable PORTEN enables register writing permission of all PCU registers. PORTEN=0x4000_1FF0 PORTEN PORTEN Writing the sequence of 0x15 and 0x51 in this register enables writing to PCU registers, and writing other values protects all PCU registers from writing.

  • Page 83: Functional Description

    When the input functions of I/O port is used by Pin Control Register, the output function of I/O port is disabled. The Port Function different according to the Pin Mux Register. The Input Data Register capture the data present on the I/O pin or Debounced input data at every GPIO Clock cycle. ABOV Semiconductor 83 / 246...
  • Page 84 AC30M1x64/1x32 When the De-Bounce functions of Input Data is used by Debounce Enable Register. External input data captured by Debounce CLK. If CNT Value is “01”, Debounced Input Data is “1”. If CNT Value is “10”, Debounced Input Data is “0”...

  • Page 85: General Purpose I/O (Gpio)

    General Purpose I/O - GPIO CHAPTER 3. GENERAL PURPOSE I/O (GPIO) ABOV Semiconductor 85 / 246...
  • Page 86 AC30M1x64/1x32 OVERVIEW Most of pins except dedicated function pins can be used general I/O ports. General input/output ports are controlled by GPIO block.  Output signal level (H/L) select  Read Input signal level Pn.BSR PSEL Pn.BCR Pn.ODR DOUT[31:0] PINs DIN[31:0] Pn.IDR...

  • Page 87: Pin Description

    General Purpose I/O - GPIO Pin description Table 3.1 External signal PIN NAME TYPE DESCRIPTION PA0 – PA15 PB0 – PB7 PC0 – PC15 PD0 – PD3 ABOV Semiconductor 87 / 246...
  • Page 88 AC30M1x64/1x32 REGISTERS The base Address of GPIO is 0x4000_2000 and register map is described in Table3.2 and 3.3. Table 3.2 Base address of each port NAME BASE ADDRESS PA PORT 0x4000_2000 PB PORT 0x4000_2100 PC PORT 0x4000_2200 PD PORT 0x4000_2300 Table 3.3 GPIO Register map...
  • Page 89 Each pin level status can be read in the Pn.IDR register. Even if the pin is alternative mode except analog mode, the pin level can be detected in the Pn.IDR register. PA.IDR=0x4000_2004, PB.IDR=0x4000_2104 PC.IDR=0x4000_2204, PD.IDR=0x4000_2304 0000 Pin current level The pin is low level The pin is high level ABOV Semiconductor 89 / 246...
  • Page 90 AC30M1x64/1x32 3.3.3 Pn.BSR PORT n Bit Set Register Pn.BSR is a register for control each bit of Pn.ODR register. Writing a ‘1’ into the specific bit will set a corresponding bit of Pn.ODR to ‘1’. Writing ‘0’ in this register has no effect.
  • Page 91 When set the Bit Set Register, GPIO Output Data Register set the high. When set the Bit Clr Register, GPIO Output Data Register set the Low. The Input Data Register capture the data present on the I/O pin or Debounced input data at every GPIO Clock cycle. ABOV Semiconductor 91 / 246...

  • Page 92: Flash Memory Controller

    AC30M1x64/1x32 CHAPTER 4. FLASH MEMORY CONTROLLER ABOV Semiconductor 92 / 246 92 / 246...
  • Page 93 0x0000_2000 WP[2] 0x0000_3000 WP[3] 0x0000_4000 WP[4] 0x0000_5000 WP[5] 0x0000_6000 WP[6] 0x0000_7000 WP[7] FLASH MEMORY 64KB 0x0000_8000 WP[8] 0x0000_9000 WP[9] 0x0000_A000 WP[10] 0x0000_B000 WP[11] 0x0000_C000 WP[12] 0x0000_D000 WP[13] 0x0000_E000 WP[14] 0x0000_F000 WP[15] Figure 4.1 Bloack diagram ABOV Semiconductor 93 / 246...

  • Page 94: Base Address

    0x00000000 FM.CRC 0x0020 Flash CRC16 check value 0x00000000 FM.CFG 0x0030 Flash Memory Configuration value 0x00008200 FM.HWID 0x0040 Second HW ID for AC30M1x64/1x32 0x30146400 BOOTCR 0x0074 Boot ROM clear, SRAM Remap register 0x00000000 FM.WPROT 0x0078 Write Protection register 0x00FFFF00 FM.RPROT 0x007C...
  • Page 95 ACODE Flash mode entry sequence A5 à 5A Trim mode entry sequence 81 à 28 AMBA mode entry sequence 66 à 99 PROT mode entry sequence 39 à 7D TESTEN mode entry sequence (test only) ABOV Semiconductor 95 / 246...
  • Page 96 AC30M1x64/1x32 4.2.2 FM.CR Flash Memory Control Register Internal flash memory control register. FM.CR[17:0] bits can be accessed while flash mode entry is activated. FM.CR[31], FM.CR[27:24] bit can be accessed in AMBA mode and FMCR[30:28] bits can be accessed in trim mode.
  • Page 97 Flash Memory Controller Write enable PBLD Page buffer load(WE should be set) Program mode enable Erase mode enable Page buffer reset ABOV Semiconductor 97 / 246...
  • Page 98 AC30M1x64/1x32 4.2.3 FM.AR Flash Memory Address Register Internal flash memory program, erase address register FM.AR=0x4000_010C FADDR 0x0000 FADDR 14-bit address covers 16K words address (one word = 4 bytes) 4.2.4 FM.DR Flash Memory Data Register Internal flash memory program data register FM.DR=0x4000_0110...
  • Page 99 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CRC16 0x00000 CRC16 CRC16 check value read register polynomial: (1 + x5 + x12 + x16) data width: 32 (the first serial bit is D[31]) ABOV Semiconductor 99 / 246...
  • Page 100 AC30M1x64/1x32 4.2.8 FM.CFG Flash Memory Config Register Internal flash memory Config register. This register has the same address with FMTRIM0 register FM.CFG=0x4000_0130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
  • Page 101 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FHWID 0x3014_6400 FHWID Flash HWID register It returns size option values 0x30146400 : 64KB flash product option 0x30143200 : 32KB flash product option 0x30FF0000 : wrong size option code, 64KB flash enable ABOV Semiconductor 101 / 246...
  • Page 102 AC30M1x64/1x32 4.2.10 BOOTCR Boot ROM Remap Clear Register Boot ROM remap clear register. This register is 8-bit register. BOOTCR=0x4000_0174 SREMAP BOOTROM SREMAP SRAM remap enable register When this bit is set, SRAM will be located at 0x0000_0000 address. This bit location can be accessed in AMBA mode...
  • Page 103 Flash mode enable to write FM.CR register (write 0x5A and then write 0xA5 into FMMR) Set FM.TMR register to be 0.5ms operation (based on 40MHz Int OSC clock) Set target Page address in FM.AR Set PMODE bit first set PPGM, WE, PGM bits of FMCR ABOV Semiconductor 103 / 246...
  • Page 104 AC30M1x64/1x32 Wait until IDLE bit of FM.MR register become “1” after pre-program Clear WE, PGM bits of FMCR Wait 5us Clear PPGM bit of FM.CR Wait 30us before returning to normal operation Clear PMODE bit of FM.CR Clear Flash mode (write 0x00 into FM.MR)

  • Page 105: Internal Sram

    Internal SRAM CHAPTER 5. INTERNAL SRAM ABOV Semiconductor 105 / 246...
  • Page 106 AC30M1x64/1x32 OVERVIEW The AC30M1x64/1x32 has a block of 0-wait on-chip SRAM. The size of SRAM is 4KB. The SRAM base address is 0x2000_0000 The SRAM memory area is usually used for data memory and stack memory. Sometimes the code is dumped into the SRAM memory for fast operation or flash erase/pgm operation.

  • Page 107: Watchdog Timer (Wdt)

    Watch-Dog Timer CHAPTER 6. WATCH-DOG TIMER (WDT) ABOV Semiconductor 107 / 246...
  • Page 108 AC30M1x64/1x32 OVERVIEW The Watchdog timer can monitor the system and generate an interrupt or a reset. It has 32-bit down-counter.  32-bit down counter (WDT.CNT)  Select reset or periodic interrupt  Count clock selection  Dedicated pre-scaler  Watchdog underflow output signal WPRS WDT.CON[2:0]...

  • Page 109: Watchdog Timer

    31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WDTCNT 0x0000_0A3D WDTCNT Watchdog timer current counter register 32-bit down counter will run from the written value. ABOV Semiconductor 109 / 246...

  • Page 110: Watchdog Timer Control Register

    AC30M1x64/1x32 6.2.3 WDT.CON Watchdog Timer Control Register WDT module should be configured properly before running. When target purpose is defined, the WDT can be configured in the WDTCON register WDT.CON=0x4000_0208 WDBG Watchdog operation control in debug mode Watchdog counter running when debug mode...

  • Page 111: Functional Description

    Selectable clock source (40 kHz ~ 16 MHz) and the time out interval when 1 count Time out period = {(Load Value) * (1/pre-scaled WDT counter clock frequency) + max 5Text} + max 4Tclk *Time out period (time out period from load Value to interrupt set ‘1’) ABOV Semiconductor 111 / 246...
  • Page 112 AC30M1x64/1x32 Table 6.3. Pre-scaled WDT counter clock frequency WDTCLKIN WDTCLKIN WDTCLKIN WDTCLKIN WDTCLKIN WDTCLKIN WDTCLKIN WDTCLKIN External / 16 / 32 / 64 / 128 / 256 Clock source (WDTCLKIN) 10kHz 5kHz 2.5kHz 1.25kHz 0.625kHz 0.3125kHz 0.15625kHz 40kHz MCLK Bus clock...
  • Page 113 16-bit Timer CHAPTER 7. 16-BIT TIMER ABOV Semiconductor 113 / 246...
  • Page 114 AC30M1x64/1x32 OVERVIEW The timer block is consisted with 4 channels of 16 bit General purpose timers. They have independent 16 bit counter and dedicated prescaler feeds counting clock. They can support periodic timer, PWM pulse, one-shot timer and capture mode. They can be synchronized together.

  • Page 115: Pin Description

    16-bit Timer Pin description Table 7.1. External pin PIN NAME TYPE DESCRIPTION TnIO External clock / capture input and PWM/one-shot output ABOV Semiconductor 115 / 246...

  • Page 116: Base Address

    AC30M1x64/1x32 REGISTERS The base Address of TIMER is 0x4000_3000 and register map is described in Table 7.2 and 7.3. Table 7.2 Base Address of each channel NAME BASE ADDRESS 0x4000_3000 0x4000_3020 0x4000_3040 0x4000_3060 Table 7.3 Timer Register Map NAME OFFSET...
  • Page 117 Clear select when capture mode Rising edge clear mode Falling edge clear mode Both edge clear mode None clear mode MODE[1:0] Timer operation mode control Normal periodic operation mode PWM mode One shot mode Capture mode ABOV Semiconductor 117 / 246...
  • Page 118 AC30M1x64/1x32 7.3.2 Tn.CR2 Timer n Control Register 2 Timer Control Register 2 is 8-bit register. T0.CR2=0x4000_3004, T1.CR2=0x4000_3024 T2.CR2=0x4000_3044, T3.CR2=0x4000_3064 PWMO TCLR PWMO PWM output for read TCLR Timer register clear Normal operation Clear count register. (This bit will be cleared after next timer clock)
  • Page 119 PWM and one-shot modes. Capture mode - Rising edge of TnIO port will capture the count value when rising edge clear mode - Falling edge of TnIO port will capture the count value when falling edge clear mode ABOV Semiconductor 119 / 246...
  • Page 120 AC30M1x64/1x32 7.3.6 Tn.CNT Timer n Count Register. Timer Count Register is 16-bit register. T0.CNT=0x4000_3014, T1.CNT=0x4000_3034 T2.CNT=0x4000_3054, T3.CNT=0x4000_3074 PRECLR 0x0000 0x0000 PRECLR Prescaler initialize when timer count value write operation 0x00 Prescaler will be initialized when write timer count value on Tn.CNT[15:0].
  • Page 121 MAIE GRA Match interrupt enable Not effect Enable match register A interrupt MBIE GRB Match interrupt enable Not effect Enable match register B interrupt OVIE Counter overflow interrupt enable Not effect Enable counter overflow interrupt ABOV Semiconductor 121 / 246...
  • Page 122 AC30M1x64/1x32 Functional Description 7.4.1 Timer basic operation TMCLK in Figure 7.2 is reference clock for operation of the timer. This clock will be divided by prescaler setting and the counting clock will work. Below figures show the starting point of the counter and the ending of the period point of the counter in normal periodic mode.
  • Page 123 TnIO output signal will be toggled at every Match A condition time. If Tn.GRA is 0 value, the TnIO output is not change its previous level. If Tn.GRA is same as Tn.GRB, the TnIO output will toggle at same time as counter start time. The initial level of TnIO signal is decided by Tn.CR1.STARTLVL value. ABOV Semiconductor 123 / 246...

  • Page 124: One Shot Mode

    AC30M1x64/1x32 7.4.3 One shot Mode Figure 7.4 shows the timing diagram in one shot mode. Tn.GRB value decides the one shot period. One more compare point is provided with Tn.GRA register value. Figure 7.4 One shot mode operation The period of one shot count can be calculated as below equation.
  • Page 125 ADC Trigger generation is available at Match A interrupt time. 7.4.5 PWM Synchronization function 2 PWM outputs usually are used as synchronous pwm signal control. This function is provided with synchronous start function. Figure 7.6 shows synchronous pwm generation function. ABOV Semiconductor 125 / 246...
  • Page 126 AC30M1x64/1x32 T0.GRB T0.CNT T0.GRA Timer0 was cleared by start event of Timer1 Timer0 starts Timer0 restarts T1.GRB T1.CNT T1.GRA Timer1 starts T0IO T1IO T0.CNT=T0.GRA T1.CNT=T1.GRA T0.CR2 T1.CR2 T0.CNT=T0.GRB TEN=1 TEN=1 T1.CNT=T1.GRB (SSYNC=1) For timing synchronization, every GRB register should have same values.

  • Page 127: Capture Mode

    The conversion rate must be shorter than timer period. If it is not a case, overrun situation can be happened. ADC acknowledge is not required, because trigger signal will be cleared automatically after 3 pclk clock pulses. ABOV Semiconductor 127 / 246...
  • Page 128 AC30M1x64/1x32 Figure 7.9 ADC trigger function timing diagram ABOV Semiconductor 128 / 246 128 / 246...
  • Page 129 CHAPTER 8. FREE RUN TIMER (FRT) ABOV Semiconductor 129 / 246...
  • Page 130 AC30M1x64/1x32 OVERVIEW The FRT block is a 32-bit Free Run Timer. It can be used in Power-down Mode  32-bit up-counter with SOSC, MOSC, LSI  Matched Interrupt FRT.PER FRT IRQ Match Compare Overflow Compare LSI CLK MOSC CLK 32 Bit DIVIDER FRT.CNT...

  • Page 131: Base Address

    TYPE DESCRIPTION RESET VALUE FRT.MR 0x0000 FRT mode register 0x00000000 FRT.CR 0x0004 FRT control register 0x00000000 FRT.PER 0x0008 FRT period match register 0x00000000 FRT.CNT 0x000C FRT counter register 0x00000000 FRT.SR 0x0010 FRT status register 0x00000000 ABOV Semiconductor 131 / 246...
  • Page 132 AC30M1x64/1x32 8.2.1 FRT.MR FRT Mode Register FRT is a 32-bit up counter. It can be used in power down mode when using SUB OSC. The SUB OSC clock is directly connected to FRT. Timer Control Register is 8-bit register. FRT.MR=0x4000_0600...
  • Page 133 OverFlow Interrupt flag bit Overflow interrupt did not occur Overflow interrupt occurred Interrupt flag bit Match interrupt did not occur. Match Interrupt occurred In Counter Match Clear mode, this bit should be cleared for restarting the counter. ABOV Semiconductor 133 / 246...
  • Page 134 AC30M1x64/1x32 FUNCTION DESCRIPTION ABOV Semiconductor 134 / 246 134 / 246...

  • Page 135: Universal Asynchronous Receiver/Transmitter (Uart)

    UART CHAPTER 9. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ABOV Semiconductor 135 / 246...
  • Page 136 AC30M1x64/1x32 OVERVIEW 2-channel UART (Universal Asynchronous Receiver/Transmitter) modules are provided. UART operation status including error status can be read from status register. The prescaler which generates proper baud rate, is exist for each UART channel. The prescaler can divide the UART clock source which is PCLK, from 1 to 65535. And baud rate generation is by clock which internally divided by 16 of the prescaled clock and 8-bit precision clock tuning function.
  • Page 137 & CONTROL (Fraction) PWRITE LOGIC TRNASMITTER TIMING PENABLE & LINE CONTROL STATUS REGISTER PCLK TRANSMITTER nRESET BUFFER TRANSMITTER TRANSMITTER HOLDING SHIFTER REGISTER REGISTER INTERRUPT INTERRUPT ENABLE CONTROL INTERRUPT REGISTER LOGIC INTERRUPT REGISTER Figure9.1. Block diagram ABOV Semiconductor 137 / 246...

  • Page 138: Pin Description

    AC30M1x64/1x32 Pin description Table 9.1. External signal PIN NAME TYPE DESCRIPTION TXD0 UART Channel 0 transmit output RXD0 UART Channel 0 receive input TXD1 UART Channel 1 transmit output RXD1 UART Channel 1 receive input ABOV Semiconductor 138 / 246...

  • Page 139: Receive Buffer Register

    UART Receive Buffer Register is 8-bit Read-Only register. Received data will be read out from this register. Maximum length of data is 8 bits. Last data received will be maintained in this register until a new byte is received. U0.RBR=0x4000_8000, U1.RBR=0x4000_8100 RBR[7:0] Receive Buffer Register ABOV Semiconductor 139 / 246...
  • Page 140 AC30M1x64/1x32 9.3.2 Un.THR Transmit Data Hold Register UART Transmit Data Hold Register is 8-bit Write-Only register. The data for transmit can be stored in this register. But the write data cannot be read from this register. The data which is written in Un.THR register, will be transferred into the transmit shifter register whenever the transmit shifter register is empty.
  • Page 141 The UART supports 3-priority interrupt generation and interrupt source ID register shows one interrupt source which has highest priority among pending interrupts. The priority is defined as below.  Receive line status interrupt  Receive data ready interrupt/ Character timeout interrupt  Transmit hold register empty interrupt ABOV Semiconductor 141 / 246...
  • Page 142 AC30M1x64/1x32 Table9.4. Interrupt ID and control Priority IPEN Interrupt sources Bit 4 Interrupt Interrupt condition Interrupt clear Bit 2 Bit 1 Bit 0 None Receiver Overrun, Parity, Framing Read LSR register or Break Error Line Status Read receive Receiver Receive data is available.

  • Page 143: Uart Line Control Register

    Parity bit will be generated according to bit 3,4,5 of Un.LCR register. The table shows the variation of parity bit generation. Table9.5. Interrupt ID and control STICKP PARITY Parity No Parity Odd Parity Even Parity Force parity as “1” Force parity as “0” ABOV Semiconductor 143 / 246...
  • Page 144 AC30M1x64/1x32 9.3.6 Un.DCR UART Data Control Register UART Data Control Register is 8-bit register. The inversion function of Tx or Rx data line, is controlled by this Un.DCR register. When the corresponding bit set 1, the data line of Tx or RX signal will be inverted.

  • Page 145: Uart Line Status Register

    Bit 1,2,3,4 will arise the line status interrupt when RLSIE bit in Un.IEN register is set. Other bits can generate its interrupt when its interrupt enable bit in Un.IEN register is set. ABOV Semiconductor 145 / 246...
  • Page 146 AC30M1x64/1x32 9.3.8 Un.BDR Baud rate Divisor Latch Register UART Baud rate Divisor Latch Register is 16-bit register. U0.BDR=0x4000_8020, U1.BDR=0x4000_8120 0x0000 Baud rate Divider latch value To establish the communication with UART channel, the baud rate should be set properly. The programmable baud rate generate is provided to give from 1 to 65535 divider number.
  • Page 147 8-bit fractional counter will count up by FCNT value every (baud rate)/16 periods and whenever fractional counter overflow is happen, the divisor value will increment by 1. So this period will be compensated. Then next period, the divisor value will return to original set value. ABOV Semiconductor 147 / 246...
  • Page 148 AC30M1x64/1x32 9.3.10 Un.IDTR Inter-frame Delay Time Register UART Inter-frame Time Register is 8-bit register. Dummy delay can be inserted between 2 continuous transmits. U0.IDTR=0x4000_8030, U1.IDTR=0x4000_8130 WAITVAL Start Bit Multi sampling enable Multi sampling is disable for start bit, Single sample will be done at 8/16 baud rate for the start bit Multi sampling is enabled for start bit.

  • Page 149: Functional Description

    10 11 12 13 14 15 Bit Sampling Position (7/16) Figure 9.3 The Sampling Timing of UART Receiver  It is recommended to enable debounce settings in the PCU block to reinforce the immunity of external glitch noise. ABOV Semiconductor 149 / 246...

  • Page 150: Transmit Interrupt

    AC30M1x64/1x32 9.4.2 Transmitter The transmitter has data transmit function. The start bit, data bits, optional parity bit and stop bit are serially shifted, least significant bit first. The number of data bit is selected in the DLAN[1:0] filed in Un.LCR register.
  • Page 151 UART Figure 9.6 Transmit interrupt timing diagram ABOV Semiconductor 151 / 246...

  • Page 152: Serial Peripheral Interface (Spi)

    AC30M1x64/1x32 CHAPTER 10. SERIAL PERIPHERAL INTERFACE (SPI) ABOV Semiconductor 152 / 246 152 / 246...
  • Page 153 Tx Shifter SPI DIV CLK Clock Register Divider MOSI SPI Register Block Transmit & Receive Logic MISO RxData[16:0] RxSData[16:0] Rx Shifter Rx Data Register SSDET TRDY RRDY SPI IRQ Interrupt Generator Figure 10.1 Bloack diagram ABOV Semiconductor 153 / 246...

  • Page 154: Pin Description

    AC30M1x64/1x32 10.2 PIN DESCRIPTION Table 10.1. External Pins PIN NAME TYPE DESCRIPTION SPI Slave select input / output SPI Serial clock input / output MOSI SPI Serial data ( Master output, Slave input ) MISO SPI Serial data ( Master input, Slave output )
  • Page 155 SPI Receive Data Register 0x000000 SP.CR 0x04 SPI Control Register 0x001020 SP.SR 0x08 SPI Status Register 0x000006 SP.BR 0x0C SPI Baud rate Register 0x0000FF SP.EN 0x10 SPI Enable register 0x000000 SP.LR 0x14 SPI delay Length Register 0x010101 ABOV Semiconductor 155 / 246...
  • Page 156 AC30M1x64/1x32 10.3.1 SP.TDR SPI Transmit Data Register SP.TDR is a 17-bits read/write register. It contains serial transmit data. SP.TDR=0x4000_9000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 157 CPOL=0, CPHA=1 : data sampling at falling edge, data changing at rising edge CPOL=1, CPHA=0 : data sampling at falling edge, data changing at rising edge CPOL=1, CPHA=1 : data sampling at rising edge, data changing at falling edge ABOV Semiconductor 157 / 246...

  • Page 158: Spi Status Register

    AC30M1x64/1x32 10.3.4 SP.SR SPI Status Register SP.SR is a 10-bits read/write register. It contains the status of SPI interface. SP.SR=0x4000_9008 SSDET The rising or falling edge of SS signal Detect flag. SS edge is not detected. SS edge is detected.
  • Page 159 SP.BR is an16-bits read/write register. Baud rate can be set by writing the register. SP.BR=0x4000_900C 0x00FF Baud rate setting bits Baud Rate = PCLK / (BR + 1) (BR must be bigger than “0”, BR >= 2 ) ABOV Semiconductor 159 / 246...
  • Page 160 AC30M1x64/1x32 10.3.6 SP.EN SPI Enable register SP.EN is a bit read/write register. It contains SPI enable bit. SP.EN=0x4000_9010 ENABLE ENABLE SPI Enable bit SPI is disabled. SP.SR is initialized by writing “0” to this bit but other registers aren’t initialized.
  • Page 161 0x01 ~ 0xFF : 1 ~ 255 SCLKs. (BTL ≥ 1) STart Length value 0x01 ~ 0xFF : 1 ~ 255 SCLKs. (STL ≥ 1) SCLK MISO MISO MISO MOSI MOSI MOSI Figure 10.2 SPI Wave form (STL, BTL and SPL) ABOV Semiconductor 161 / 246...

  • Page 162: Functional Description

    AC30M1x64/1x32 10.4 FUNCTIONAL DESCRIPTION SPI Transmit block and Receive block share Clock Gen Block but they are independent each other. Transmit block and Receive block have double buffers and SPI is available for back to back transfer operation. 10.4.1 SPI timing The SPI has four modes of operation.
  • Page 163 (falling edge if CPOL equals zero and rising edge if CPOL equals one). After eight clock pulses the transmission is completed. MOSI MISO Figure 10.5 SPI Transfer Timing 3/4 (CPHA=1, CPOL=0, MSBF=0) MOSI MISO Figure 10.6 SPI transfer timing 4/4 (CPHA=1, CPOL=1, MSBF=1) ABOV Semiconductor 163 / 246...
  • Page 164 AC30M1x64/1x32 CHAPTER 11. C Interface ABOV Semiconductor 164 / 246 164 / 246...
  • Page 165 Slave Addr. Register1 enable (I2CSAR1) Noise SDAIN Canceller 8-bit Shift Register (debounce) (SHFTR) SDAOUT Data Out Register Out Controller (I2CDR) Debounce enable (I2CSCLHR) SCLIN Noise Canceller Out Controller (I2CSCLLR) (debounce) (I2CDAHR) SCLOUT Figure 11.1.I C Block diagram ABOV Semiconductor 165 / 246...
  • Page 166 AC30M1x64/1x32 11.2 PIN DESCRIPTION Table 11.1. I C interface external pins PIN NAME TYPE DESCRIPTION C channel Serial clock bus line (open-drain) C channel Serial data bus line (open-drain) ABOV Semiconductor 166 / 246 166 / 246...

  • Page 167: Base Address

    0x0C C Slave Address Register 0x00 IC.CR 0x14 C Control Register 0x00 IC.SCLL 0x18 C SCL LOW duration Register 0xFFFF IC.SCLH 0x1C C SCL HIGH duration Register 0xFFFF IC.SDH 0x20 C SDA Hold Register 0x7F ABOV Semiconductor 167 / 246...

  • Page 168: I C Data Register

    AC30M1x64/1x32 11.3.1 IC.DR C Data Register IC.DR is an 8-bits read/write register. It contains a byte of serial data to be transmitted or a byte which has just been received. IC.DR=0x4000_A000 ICDR 0xFF ICDR The most recently received data or data to be transmitted.

  • Page 169: I 2 C Status Register

    Mastership is lost. BUSY BUSY flag C bus is in IDLE state. C bus is busy. TMODE Transmitter/Receiver mode flag Receiver mode. Transmitter mode. RXACK Rx ACK flag Rx ACK is not received. Rx ACK is received. ABOV Semiconductor 169 / 246...
  • Page 170 AC30M1x64/1x32 11.3.3 IC.SAR C Slave Address Register IC.SAR is an 8-bits read/write register. It shows the address in slave mode. IC.SAR=0x4000_A00C SVAD GCEN 0x00 SVAD 7-bit Slave Address GCEN General call enable bit General call is disabled. General call is enabled.

  • Page 171: I 2 C Control Register

    Stop is disabled. Stop is enabled. When this bit is set, transmission will be stopped. START Transmission start bit in master mode. Waits in slave mode. Starts transmission in master mode. Figure 11.2 INTDEL in Master mode ABOV Semiconductor 171 / 246...
  • Page 172 AC30M1x64/1x32 11.3.5 IC.SCLL C SCL LOW duration Register IC.SCLL is a 16-bit read/write register. SCL LOW time can be set by writing this register in master mode. IC.SCLL=0x4000_A018 SCLL 0xFFFF SCLL SCL LOW duration value. SCLL = ( PCLK * SCLL[15:0] ) + 2*PCLKs Default value is 0xFFFF.
  • Page 173 IC.SCLH is a 16-bit read/write register. SCL HIGH time will be set by writing this register in master mode. IC.SCLH=0x4000_A01C SCLH 0xFFFF SCLH SCL HIGH duration value. SCLH = ( PCLK * SCLH[15:0] ) + 3 PCLKs Default value is 0xFFFF. Figure 11.4 SCL HIGH Timing ABOV Semiconductor 173 / 246...
  • Page 174 AC30M1x64/1x32 11.3.7 IC.SDH SDA Hold Register IC.SDH is a 15-bit read/write register. SDA HOLD time will be set by writing this register in master mode. IC.SDH=0x4000_A020 0x7FFF SDA HOLD time setting value. SDH = ( PCLK * SDH[14:0] ) + 4 PCLKs Default value is 0x7FFF.

  • Page 175: I 2 C Bit Transfer

    The data on the SDA line must be stable during the “H” period of the clock. The “H” or “L” state of the data line can only change when the clock signal on the SCL line is “L” (see Fig 11.6). Data line Stable: Change of Data Data valid allowed except S, Sr, P Figure 11.6 I C Bus bit transfer ABOV Semiconductor 175 / 246...
  • Page 176 AC30M1x64/1x32 11.4.2 START/Repeated START/STOP Within the procedure of the I C-bus, unique situations arise which are defined as START(S) and STOP(P) conditions (see Figure 11.7). i) An “H” to “L” transition on the SDA line while SCL is “H” is one such unique case. This situation indicates a START condition.

  • Page 177: Data Transfer

    Signal from Slave Signal from Slave Byte Complete, Clock line held low Interrupt within Device while interrupts are served. STOP or Repeated START or Repeated START Condition START Condition Figure 11.8 I C Bus data transfer ABOV Semiconductor 177 / 246...
  • Page 178 AC30M1x64/1x32 11.4.4 Acknowledge Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable “L” during the “H”...
  • Page 179 The first device to complete its “H” period will again pull the SCL line “L”. Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT Figure 11.10 Clock synchronization during the arbitration procedure ABOV Semiconductor 179 / 246...
  • Page 180 AC30M1x64/1x32 11.4.6 Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition which results in a defined START condition to the bus.

  • Page 181: Master Transmitter

    Master command or Data Write From slave to master STOP Interrupt, SCL line is held low Interrupt after stop command Arbitration lost as master and LOST& addressed as slave Figure 11.12 Transmitter Flowchart in Master mode ABOV Semiconductor 181 / 246...

  • Page 182: Master Receiver

    AC30M1x64/1x32 11.5.2 Master Receiver It shows the flow of receiver in master mode (see Figure 11.13). IDLE Master SLA+W S or Sr Transmitter SLA+R STOP LOST DATA LOST LOST& STOP Other master continues LOST From master to slave / Master command or Data Write...

  • Page 183: Slave Transmitter

    Interrupt, SCL line is held low Master command or Data Write From slave to master Interrupt after stop command Arbitration lost as master and LOST& addressed as slave GCALL General Call Address Figure 11.14 Transmitter Flowchart in Slave mode ABOV Semiconductor 183 / 246...

  • Page 184: Slave Receiver

    AC30M1x64/1x32 11.5.4 Slave Receiver It shows the flow of receiver in slave mode (see Figure 11.15). IDLE S or Sr SLA+W GCALL LOST& DATA STOP IDLE From master to slave / Interrupt, SCL line is held low Master command or Data Write...
  • Page 185 Motor PWM CHAPTER 12. MOTOR PULSE-WIDTH-MODULATOR (MPWM) ABOV Semiconductor 185 / 246...
  • Page 186 AC30M1x64/1x32 12.1 OVERVIEW The MPWM is Programmable Motor controller which is optimized for 3-phase AC and DC motor control application. It can be used in many other application that need timing, counting and comparison. The MPWM includes 3 channels, each of which controls a pair of outputs that is turn can control a motor.

  • Page 187: Motor Pwm

    MPWM Phase-U H-side output MPWMUL MPWM Phase-U L-side output MPWMVH MPWM Phase-V H-side output MPWMVL MPWM Phase-V L-side output MPWMWH MPWM Phase-W H-side output MPWMWL MPWM Phase-W L-side output PRTIN MPWM Protection Input OVIN MPWM Over-voltage Input ABOV Semiconductor 187 / 246...

  • Page 188: Base Address

    AC30M1x64/1x32 12.3 REGISTERS Base address of MPWM is below.. Table 12.2. MPWM base address NAME BASE ADDRESS MPWM 0x4000_4000 Table 12.3 shows Register memory map. Table 12.3. MPWM Register map NAME OFFSET TYPE DESCRIPTION RESET VALUE MP.MR 0x0000 MPWM Mode register 0x0000_0000 MP.OLR...
  • Page 189 The UPDOWN in MP.MR field is only effective when MOTORB in MP.MR is set “1”. Otherwise the UPDOWN field value will be ignored internally and will keep “1” value. In the motor mode, the counter is always updown count operation. ABOV Semiconductor 189 / 246...
  • Page 190 AC30M1x64/1x32 12.3.2 MP.OLR MPWM Output Level Register PWM output level register is 8-bit register. This register will control the active level of each PWM output port. The default active level is negated when the corresponding bit is set. The normal level is defined in each operating mode.
  • Page 191 Motor PWM POLWH WH CONTROL WH OUTPUT OLR.WHL Figure 12.2 Polarity Control Block ABOV Semiconductor 191 / 246...
  • Page 192 AC30M1x64/1x32 12.3.3 MP.FOLR MPWM Force Output Level Register PWM force output register is 8-bit register. The PWM output level can be forced by an abnormal event from externally or user intended condition. When the forced condition is occurred, each PWM output level which is programmed in FOLR register will be forced.
  • Page 193 PWM HALT (PWM counter stop but not reset) PWM outputs keep previous state PSTART PWM counter stop and clear PWM counter start (will be resynced @PWM clock twice) PWMEN should be “1” to start PWM counter ABOV Semiconductor 193 / 246...
  • Page 194 AC30M1x64/1x32 12.3.6 MP.PRD MPWM Period Register PWM Period Register is 16-bit register. MP.PRD=0x4000400C PERIOD 0x0002 PERIOD 16-bit PWM period. It should be larger than 0x0010 (if Duty is 0x0000, PWM will not work) 12.3.7 MP.DUH MPWM Duty UH Register PWM UH channel duty register is 16-bit register.
  • Page 195 MPWM Duty VL Register PWM VL channel duty register is 16-bit register. MP.DVL=0x4000_4020 DUTY VL 0x0001 DUTY VL 16-bit PWM Duty for VL output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) ABOV Semiconductor 195 / 246...
  • Page 196 AC30M1x64/1x32 12.3.12 MP.DWL MPWM Duty WL Register PWM WL channel duty register is 16-bit register. MP.DWL=0x4000_4024 DUTY WL 0x0001 DUTY WL 16-bit PWM Duty for WL output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) 12.3.13...
  • Page 197 In other case, the interrupt is generated by ADC trigger counter match condition. The ADC trigger mode is selected by ATMOD bit field in ATRm register. ABOV Semiconductor 197 / 246...
  • Page 198 AC30M1x64/1x32 12.3.15 MP.CNT MPWM Counter Register PWM Counter Register is 16-bit Read-Only register. MP.CNT=0x4000_4038 0x0000 PWM Counter Value 12.3.16 MP.DTR MPWM Dead Time Register PWM Dead Time Register is 16-bit register. MP.DTR=0x4000_403C 0x00 DTEN Dead-time function enable 2 channel symmetric mode does not support dead time function. It should be disabled in 2 channel symmetric mode.
  • Page 199 Disable Protection Output Enable Protection Output with FOR value ULPROTM Activate U-phase L-side protection output Disable Protection Output Enable Protection Output with FOR value Note) MP.PCR0 is related to PRTIN pin and MP.PCR1 is related to OVIN. ABOV Semiconductor 199 / 246...
  • Page 200 AC30M1x64/1x32 12.3.18 MP.PSRn MPWM Protection 0,1 Status Register PWM Protection Status Register is 16-bit register. This register indicates which outputs are disabled. And User can set the output masks manually. Without writing PROTKEY when writing any value, the written values are ignored.
  • Page 201 ADC trigger Mode register ADC trigger Disable Trigger out when up count match Trigger out when down count match Trigger out when up-down count match ATCNT ADC Trigger counter (it should be less than PWM period) ABOV Semiconductor 201 / 246...

  • Page 202: Functional Description

    AC30M1x64/1x32 12.4 Functional Description The MPWM includes 3 channels, each of which controls a pair of outputs that in turn can control something off-chip component. In normal pwm mode, each channel is running independently. 6 PWM output can be generated.
  • Page 203 The symmetrical feature is appeared in each channel which is controlled by corresponding DUTY register value. ABOV Semiconductor 203 / 246...
  • Page 204 AC30M1x64/1x32 12.4.4 Motor PWM 1-Chennel Asymmetric mode timing The 1 channel asymmetric mode makes asymmetric duration pulses which are defined by H-side and L-side DUTY register. So L-side signal is always negate signal of H-side. During up count period, the H-side DUTY register matching condition makes the active level pulse and during down count period, the L-side DUTY register matching condition makes the default level pulse.
  • Page 205 H-side duty level is matched in up count period and is returned to default level when the H-side duty level is matched again in down count period. When the PSTART is set, the L-side pwm output is changed to the active level then the L-side pwm output is inverse output of H-side output. ABOV Semiconductor 205 / 246...
  • Page 206 AC30M1x64/1x32 12.4.6 PWM Dead-time operation To prevent external short condition, the MPWM provide dead time function. This function is only available for motor pwm mode. When one of H-side or L-side output changes to active level, amount of dead time will be inserted if DTEN.MP.DTR bit is enabled.
  • Page 207 When the dead time counter is reached to dead time value, the mask is disabled. Figure 12.9 Normal Dead-time Operation (T >T DUTY A couple of figures in below show special case of dead time configurations. ABOV Semiconductor 207 / 246...
  • Page 208 AC30M1x64/1x32 MP.CNT 2 x T DUTY MP.PRD MP.DUH/V/W DT-Rising MASKED Mask DT-Falling MASKED Mask DT-Rising MP0UH MP0VH MP0WH DT-Falling MP0UH MP0VH MP0WH Figure 12.10 Minimum H-side pulse timing (T <T <2xT DUTY DUTY MP.CNT 2 x T DUTY MP.PRD MP.DUH/V/W...
  • Page 209 Figure 12.12 Minimum L-side pulse timing (T <Period-T DUTY MP.CNT 2 x T DUTY MP.PRD MP.DUH/V/W DT-Rising MASKED Mask MASKED MASKED DT-Falling Mask DT-Rising MP0UH MP0VH MP0WH DT-Falling DT-Falling MP0UH MP0VH MP0WH Figure 12.13 Zero L-side pulse timing (T >Period-T DUTY ABOV Semiconductor 209 / 246...
  • Page 210 AC30M1x64/1x32 MP.CNT MP.PRD MP.DxH=0 DT-Rising No Rising mask Mask No Falling mask DT-Falling Mask MP0UH Always MP0VH MP0WH ‘ ’ MP0UH MP0VH Always ‘L’ MP0WH Figure 12.14 H-side always on (T =Period: dead-time disabled) DUTY MP.CNT MP.DxH=MP.PRD MP.PRD DT-Rising No Rising mask...
  • Page 211 H-side is performed in both up count period. The duty compare of L-side is performed in both down count period. MP.CNT MP.DUL MP.DVL MP.DWH/DWL MP.DUH MP.DVH MP0UH MP0UL MP0VH MP0VL MP0WH MP0WL Sensing margin Figure 12.17 Asymmetrical PWM Timing and Sensing margin ABOV Semiconductor 211 / 246...
  • Page 212 AC30M1x64/1x32 12.4.9 Description of ADC Triggering function Total 6 ADC trigger timing registers are provided. This dedicated register will make a trigger signal to start ADC conversion. The conversion channel of ADC will be defined in ADC control register. MP.CNT •...
  • Page 213 An example of ADC Data acquisition MP.CNT MP.DWH MP.ATR1 MP.DUH MP.DVH MP0U MP0UL MP0V MP0VL MP0W MP0WL Ia, Ib ADC Start (MPxATR1==MPxCNT) Start Figure 12.19 An example of ADC acquisition timing by event from MPWM ABOV Semiconductor 213 / 246...
  • Page 214 AC30M1x64/1x32 12.4.10 Interrupt Generation Timing Each timing event can make interrupt request to the CPU. Figure 12.20 Interrupt Generation Timing ABOV Semiconductor 214 / 246 214 / 246...
  • Page 215 Divider CHAPTER 13. DIVIDER (DIV64) ABOV Semiconductor 215 / 246...
  • Page 216 AC30M1x64/1x32 13.1 OVERVIEW The divider module provides hardware divider ability to accelerate complicated calculation. This divider is sequential 64bit/32bit divider requires 32 clock cycles for one operation. The equation of the operation is below (AREGH,AREGL) / BREG = (QREGH,QREGL) ...
  • Page 217 0x00000000 BREG 0x000C 32bit data register for divisor 0x00000000 QREGL 0x0010 Most 32bit data register for quotient 0x00000000 QREGH 0x0014 Least 32bit data register for quotient 0x00000000 RREG 0x0018 32bit data register for remainder 0x00000000 ABOV Semiconductor 217 / 246...
  • Page 218 AC30M1x64/1x32 13.2.1 Divider Control Register DIVCON register control the hardware divider module. CR=0x4000_0500 I_ERROR Divide by zero flag Not divide by zero Divide by zero BUSY Divider is now under operating Divider is not busy Divider is busy DONE Divider operation done flag...
  • Page 219 When MODE bit set 1, the divide operation will be started automatically as soon as writing this register. BREG=0x4000_050C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BREG[31:0] 0x0000_0000 BREG 32 bit value for divisor B. ABOV Semiconductor 219 / 246...
  • Page 220 AC30M1x64/1x32 13.2.1 QREGL QREG (Quotient) Lower 32bit Register The divider will store lower 32bit value of quotient in this register QREGL=0x4000_0510 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 221 12-BIT A/D Converter CHAPTER 14. 12BIT A/D CONVERTER ABOV Semiconductor 221 / 246...
  • Page 222 AC30M1x64/1x32 14.1 12-bit ADC Introduction ADC block consists of 1 ADC units.  12 channels of analog inputs  Single and Continuous conversion mode  Up to 8 times sequential conversion supports  Software trigger supports  3 internal trigger sources supports (Soft-trig, MPWM, Timers) ...

  • Page 223: Bit A/D Converter

    ADC Input 1 ADC Input 2 ADC Input 3 ADC Input 4 ADC Input 5 ADC Input 6 ADC Input 7 ADC Input 8 ADC Input 9 AN10 ADC Input 10 AN11 ADC Input 11 ABOV Semiconductor 223 / 246...
  • Page 224 AC30M1x64/1x32 14.3 REGISTERS Base addresses of ADC units are as below. Table 14.2 ADC base address NAME BASE ADDRESS 0x4000_B000 Table 14.3 ADC Register map NAME OFFSET TYPE DESCRIPTION RESET VALUE AD.MR 0x0000 ADC Mode register 0x00 AD.CSCR 0x0004 ADC Current Sequence/Channel register 0x00 AD.CCR...

  • Page 225: Adc Mode Register

    If ADCMOD was set for Burst Mode, ADC channels are controlled by SEQ0CH ~ SEQ7CH. Sequential mode always start from SEQ0CH. (In 3 sequential mode, Analog inputs of channels which assigned at SEQ0CH, SEQ1CH and SEQ2CH are converted sequentially). ABOV Semiconductor 225 / 246...
  • Page 226 AC30M1x64/1x32 14.3.2 AD.CSCR ADC Current Sequence/Channel Register ADC Current Seqneuce/Channel Registers are 7-bit registers. This registers consist of Current Sequence Numbers and Current Active Channel values. CSEQN (Current Sequence Number) can be written to change next sequence number. Writing CSEQN as 0x7 when CSEQN is 0x3 and AD.MR.SEQCNT is 0x7, the next sequence number is 0x7 and AD converts the channel of AD.SCSR.SEQ7CH and the 4,5,6 sequence are skipped.
  • Page 227 0 – internal clock(CKDIV enabled) 1 – external clock(SCU clock-MCCR7) CLKINVT Divided clock inversion(optional bit) 0 – duty ratio of divided clock is larger than 50% 1 – duty ratio of divided clock is less than 50% ABOV Semiconductor 227 / 246...
  • Page 228 AC30M1x64/1x32 14.3.4 AD.TRG ADC Trigger Selection Register ADC Trigger registers are 32-bit registers. ADC Trigger channel register. In Single/Burst mode, all the bit fields are used. In Burst conversion mode, Only BSTTRG bit field (bit3~bit0) is used. AD.TRG=0x4000_B00C 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

  • Page 229: Adc Control Register

    @AD clock. If ASTART is set as 0 when ARST is 0 in Timer/MPWM trigger event mode, AD converts to AD.MR.SEQCNT once and AD stops. ASTART should be written to start the conversion sequence again ABOV Semiconductor 229 / 246...

  • Page 230: Adc Status Register

    AC30M1x64/1x32 14.3.7 AD.SR ADC Status Register ADC Status Register is 8-bit register. AD.SR=0x4000_B024 ABUSY TRGIRQ EOSIRQ EOCIRQ ADC End-of-Conversion flag (Start-of-Conversion made by ADC_CLK clears this bit, not ASTART) ABUSY ADC conversion busy flag Reserved. Reserved. TRGIRQ ADC Trigger interrupt flag (Write “1” to clear flag)
  • Page 231 14.3.9 AD.DRm ADC Sequence Data Register 0~7 ADC Data Registers are 16-bit registers. ADC conversion result register. AD.DR0=0x4000_B030, AD.DR1=0x4000_B034, AD.DR2=0x4000_B038, AD.DR3=0x4000_B03C AD.DR4=0x4000_B040, AD.DR5=0x4000_B044, AD.DR6=0x4000_B048, AD.DR7=0x4000_B04C ADC DATA 0x000 ADC DATA ADC channel 0~7 data (12-bit) ABOV Semiconductor 231 / 246...
  • Page 232 AC30M1x64/1x32 14.4 Functional Description 14.4.1 AD conversion timing diagram When AD.MR.ADMOD is 0x0 and AD.MR.SEQCNT is 0x0, ADC conversion will be started by AD.CR.ASTART written as ‘1’. Once AD.CR.ASTART is set, SOC (start of Conversion) will be activated in 3 ADC clocks and AD.SR.EOCIRQ will be set in 2 ADC clocks and 2 PCLKs after the End of Conversion.
  • Page 233 ADC will covert ADC Channels as much as AD.MR.SEQCNT set. See Figure 14.4. Figure 14.2 ADC Burst mode timing (when AD.MR.AMOD = ‘1’) Figure 14.3 ADC trigger timing in Burst mode (SEQCNT = 3’b111, 8 sequence coversion) ABOV Semiconductor 233 / 246...
  • Page 234 AC30M1x64/1x32 14.4.3 ADC Sequential conversion mode timing diagram Single sequential conversion mode (Single sequential mode) is when AD.MR.ADMOD is 0x0 and AD.MR.SEQCNT is not 0x0. To set sequential conversion mode, AD.MR.AMOD is 2’b00 and AD.MR.SEQCNT is not 2’b00. The operation of sequential mode is the almost same as the burst mode. The difference is ths source of SOC. Each SOC is made by the trigger of the SEQTRGx as each SEQCNT.

  • Page 235: Section 3.Characteristic

    CHARACTERISTIC SECTION 3.CHARACTERISTIC ABOV Semiconductor 235 / 246...

  • Page 236: Electrical Characteristic

    AC30M1x64/1x32 CHAPTER 1. Electrical Characteristic ABOV Semiconductor 236 / 246 236 / 246...

  • Page 237: Electrical Characteristics

    Output Low Current per pin Output Low Current Total ∑ I Output High Current per pin Output Low Current Total ∑ I Power consumption Input Main Clock Range Operating Frequency ℃ Storage Temperature +125 ℃ Operating Temperature +105 ABOV Semiconductor 237 / 246...
  • Page 238 AC30M1x64/1x32 1.1.2 DC Characteristics Table 1.2 Recommended Operating Condition Parameter Symbol Condition Typ. unit Supply Voltage Supply Voltage AVDD MOSC SOSC 32.768 Operating Frequency FREQ 38.8 41.2 ℃ Operating Temperature +105 Table 1.3 DC Electrical Characteristics (VDD = +5V, Ta = 25 ℃)

  • Page 239: Current Consumption

    Table 1.5 POR Electrical Characteristics (Temperature: -40 ~ +105℃) Parameter Symbol Condition Typ. unit Operating Voltage VDD18 Typ. <6uA Operating Current If always on VDD rising POR Set Level 1.55 (slow) VDD falling POR Reset Level (slow) ABOV Semiconductor 239 / 246...

  • Page 240: Vdc Electrical Characteristics

    AC30M1x64/1x32 1.1.5 LVD Electrical Characteristics Table 1.6 LVD Electrical Characteristics (Temperature: -40 ~ +105℃) Parameter Symbol Condition Typ. unit Operating Voltage Typ. <6uA Operating Current when always on VDD falling LVD Set Level 0 VLVD0 1.58 1.73 (slow) VDD falling...
  • Page 241 Electrical Characteristics 1.1.7 External OSC Characteristics Table 1.8 External OSC Characteristics (Temperature: -40 ~ +105℃) Parameter Symbol Condition unit Operating Voltage @4MHz/5V Frequency OSCF Output Voltage VOUT Load Capacitance LOAD ABOV Semiconductor 241 / 246...

  • Page 242: Adc Electrical Characteristics

    AC30M1x64/1x32 1.1.8 ADC Electrical Characteristics Table 1.9 ADC Electrical Characteristics (Temperature: -40 ~ +105℃) Parameter Symbol Condition Typ. unit Operating Voltage AVDD Resolution Operating Current IDDA Analog Input Range AVDD Conversion Rate MSPS Operating Frequency ACLK ±3.5 DC Accuracy ±2.5 Offset Error ±1.5...
  • Page 243 Package CHAPTER 2. Package ABOV Semiconductor 243 / 246...

  • Page 244: Lqfp-48

    AC30M1x64/1x32 LQFP-48 Package dimension Figure 2.1 Package dimension (LQFP-48) ABOV Semiconductor 244 / 246 244 / 246...

  • Page 245: Lqfp

    Package LQFP-32 Package dimension Figure 2.2 Package dimension (LQFP-32) ABOV Semiconductor 245 / 246...
  • Page 246 AC30M1x64/1x32 QFN-32 Package dimension Figure 2.3 Package dimension (QFN-32) ABOV Semiconductor 246 / 246 246 / 246...

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