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ABOV SEMICONDUCTOR MC81F4204 User Manual

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MC81F4204
ABOV SEMICONDUCTOR
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC81F4204
MC81F4204 R/M/V/D/B/W/U
User's Manual
(Ver. 1.41)
April 24, 2012 Ver.1.41
1

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Summary of Contents for ABOV SEMICONDUCTOR MC81F4204

  • Page 1 MC81F4204 ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS MC81F4204 MC81F4204 R/M/V/D/B/W/U User’s Manual (Ver. 1.41) April 24, 2012 Ver.1.41...
  • Page 2 Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors. ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 3: Revision History

    MC81F4204 REVISION HISTORY VERSION 1.41 (April 24, 2012) This book Add the chapter ’ 7.10 POR Electrical CHARACTERISTICS’. VERSION 1.40 (May 21, 2011) This book Update 20QFN pin assignment and package diagram. VERSION 1.39 (December 28, 2010) This book Change ‘5.5v’ to “VDD level” in DC Electrical Characteristics description(page 27/28).
  • Page 4 MC81F4204 Add “16TSSOP” at 16pin pin assignment page. Remove fxt(sub-clock source) at block diagrams and register descriptions of T0/1/2 and Buzzer. VERSION 1.21 (July 7, 2009) “25.3 Hardware Conditions to Enter the ISP Mode” is updated. Notes of R35 port control registers are updated.
  • Page 5 MC81F4204 Update the chapter ‘6. PORT STRUCTURE’. Update the chapter ‘7. ELECTRICAL CHARACTERISTICS’. Update the chapter ’25. IN SYSTEM PROGRAMMING’. VERSION 0.3 Preliminary (December 19, 2008) Block diagrams of Timer 2/3 and PWM are corrected. VERSION 0.2 Preliminary (November 17, 2008) Some errata are corrected.

  • Page 6: Table Of Contents

    MC81F4204 TABLE OF CONTENTS REVISION HISTORY ..........................3 TABLE OF CONTENTS .......................... 6 1. OVERVIEW............................9 1.1 Description ............................ 9 1.2 Features............................9 1.3 Development Tools........................10 1.4 Ordering Information........................11 2. BLOCK DIAGRAM ..........................12 3. PIN ASSIGNMENT ........................... 13 3.1 20 pin- PDIP/SOP/TSSOP......................
  • Page 7 MC81F4204 9.2 Program Memory ........................48 9.3 Data Memory ..........................51 9.4 User Memory ..........................51 9.5 Stack Area ..........................52 9.6 Control Registers ( SFR ) ......................52 9.7 Addressing modes ........................57 10. I/O PORTS ............................64 10.1 R0 Port Registers ........................65 10.2 R1 Port Registers ........................
  • Page 8 MC81F4204 22. RESET ............................122 22.1 Reset Process ........................122 22.2 Reset Sources ........................123 22.3 Reset Circuit ...........................123 22.4 Watch Dog Timer Reset ......................124 22.5 Power On Reset ........................125 22.6 Low Voltage Reset........................125 23. POWER DOWN OPERATION......................126 23.1 Sleep Mode..........................126 23.2 Stop Mode..........................128 23.3 Sleep vs Stop..........................131...

  • Page 9: Overview

    1. OVERVIEW 1.1 Description MC81F4204 is a CMOS 8 bit MCU which provides a 4K bytes FLASH-ROM and 192 bytes RAM. It has following major features, 12 bit ADC : It has 10 ch A/D Converter which can be used to measure minute electronic voltage and currents.

  • Page 10: Development Tools

    MC81F4204 1.3 Development Tools The MC81F4204 is supported by a full-featured macro assembler, C-Compiler, an in-circuit emulator CHOICE-Dr. , FALSH programmers and ISP tools. There are two different type of programmers such as single type and gang type. For more detail, Macro assembler operates under the MS- Windows 95 and up versioned Windows OS.

  • Page 11: Ordering Information

    MC81F4204 1.4 Ordering Information Device Name FLASH ROM Package MC81F4204R 4K Bytes 192 Bytes 16_TSSOP MC81F4204M 16_SOP MC81F4204V 16_PDIP MC81F4204D 20_SOP MC81F4204B 20_PDIP MC81F4204W 20_TSSOP April 24, 2012 Ver.1.41...

  • Page 12: Block Diagram

    MC81F4204 2. BLOCK DIAGRAM Figure 2-1 System Block Diagram April 24, 2012 Ver.1.41...

  • Page 13: Pin Assignment

    MC81F4204 3. PIN ASSIGNMENT 3.1 20 pin- PDIP/SOP/TSSOP April 24, 2012 Ver.1.41...

  • Page 14: Pin- Qfn

    MC81F4204 3.2 20 pin- QFN 3.3 16 pin- PDIP/SOP/TSSOP April 24, 2012 Ver.1.41...

  • Page 15: Summary

    MC81F4204 3.4 Summary Pin number Pin status alternative functions at RESET 20pin 16pin input EXT10/SXin input EXT11/SXout input AN0/EXT0/EC0 input AN1/EXT1/T0O/PWM0O input AN2/EXT2/EC1/SCK input AN3/EXT3/T1O/PWM1O/SI input AN4/EXT4/EC2/SO input AN5/EXT5/T2O input Vref/EXT6 input AN6/EXT7/PWM2O input AN7/EXT8/PWM3O/BUZO Open-drain output AN8/EXT9/PWM4O Open-drain output...

  • Page 16: Package Diagram

    MC81F4204 4. PACKAGE DIAGRAM 4.1 20 PDIP- MC81F4204B 4.2 20 SOP - MC81F4204D April 24, 2012 Ver.1.41...

  • Page 17: Tssop - Mc81F4204W

    MC81F4204 4.3 20 TSSOP - MC81F4204W April 24, 2012 Ver.1.41...

  • Page 18: Qfn - Mc81F4204U

    MC81F4204 4.4 20 QFN - MC81F4204U 4.5 16 PDIP - MC81F4204V April 24, 2012 Ver.1.41...

  • Page 19: Sop - Mc81F4204M

    MC81F4204 4.6 16 SOP - MC81F4204M 4.7 16 TSSOP - MC81F4204R April 24, 2012 Ver.1.41...

  • Page 20: Pin Description

    MC81F4204 5. PIN DESCRIPTION Alternative Pin Names Pin Description Functions This port is a 1-bit programmable I/O pin. EXT10 Schmitt trigger input, Push-pull, or Open-drain output port. EXT11 When used as an input port, a Pull-up resistor can be AN0/EC0/EXT0 specified in 1-bit.
  • Page 21 MC81F4204 Alternative Pin Names Pin Description Functions EXT5 External interrupt input/Timer 2 capture input R07/AN5/T2O EXT6 External interrupt input R10/Vref EXT7 R11/AN6/ PWM2O EXT8 R12/AN7/ PWM3O/BUZO EXT9 R13/AN8 EXT10 EXT11 Timer 0 clock output R03/AN1/EXT1/ PWM0O PWM0O PWM 0 clock output...
  • Page 22 MC81F4204 Alternative Pin Names Pin Description Functions ADC input pins R11/EXT7/ PWM2O R12/EXT8/ PWM3O/BUZO R13/EXT9 AN14 Serial clock input R04/AN2/EC1/ EXT2 R05/AN3/EXT3/ Serial data input T1O/PWM1O Serial data output R06/AN4/EC2/ EXT4 System reset pin RESETB – Main oscillator pins –...

  • Page 23: Port Structure

    MC81F4204 6. PORT STRUCTURE [Schmitt trigger In] + [Out/Open-drain-out] + [Xin/Xout] Pull-up Enable OPEN- DRAIN *Output data* Output Disable *Input data* OSCS ROM Option *Xin/Xout* Input/Output data Clock Xout [Schmitt trigger In] + [Out/Open-drain-out] + [SXin/SXout] Input/Output data Input data...
  • Page 24 MC81F4204 [Schmitt trigger In] + [Out / Open-drain-out] + [ADC] Input/Output data Input data Output data EXT0 / EC0 EXT1 T0O/PWM0O EXT2/SCK/EC1 EXT3/SI T1O/PWM1O EXT4/EC2 EXT5 EXT6 Vref EXT7 PWM2O EXT8 PWM3O/BUZO EXT9 PWM4O [Schmitt trigger In] + [Out / Open-drain-out]...
  • Page 25 MC81F4204 [Input] + [Out / Open-drain-out] + [ADC] Pull-up Enable OPEN- DRAIN *Output data* Output Disable ADC enable ADC select *Input data* *ADC* Input/Output data Input data Output data AN14 [Input] + [Out/Open-drain out] Pull-up Enable OPEN- DRAIN *Output data*...

  • Page 26: Electrical Characteristics

    MC81F4204 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Unit Parameter Symbol Ratings Note Supply Voltage -0.3 – +6.0 – -0.3 – VDD+0.3 Voltage on any pin with respect to Vss -0.3 – VDD+0.3 Maximum current output sourced by (IOH per I/O pin) Normal Voltage Pin ΣIOH...

  • Page 27: A/D Converter Characteristics

    MC81F4204 7.3 A/D Converter Characteristics ° ° = - 40 C to + 85 C, Vref = 2.7 V to 5.5 V) Parameter Symbol Conditions Units A/D converting – – – – bits Resolution ± 3 Integral Linearity Error –...

  • Page 28: Dc Electrical Characteristics

    MC81F4204 7.4 DC Electrical Characteristics ° ° = - 40 C to + 85 C, V = 2.2 – 5.5V, Vss=0V, f =12MHz) Parameter Symbol Conditions Units R0x, R1x, R33 – R35 VIH1 0.8VDD – VDD+0.3 V DD = 4.5V – 5.5V...

  • Page 29: Dc Electrical Characteristics (Continued)

    MC81F4204 7.5 DC Electrical Characteristics (Continued) ° ° = - 40 C to + 85 C, V = 2.2 – 5.5V, Vss=0V, f =12MHz) Parameter Symbol Conditions Units Xin=VDD, Xout=VSS OSC feedback 1500 MΩ resistor ° TA=25 C, VDD=5V Active mode, fx=12MHz, VDD=5V±10%...

  • Page 30: Serial I/O Characteristics

    MC81F4204 7.7 Serial I/O Characteristics ° ° = - 40 C to + 85 C, V = 2.2 V to 5.5 V) Parameter Symbol Conditions Typ Max Units External SCK source 1,000 t KCY SCK cycle time Internal SCK source...
  • Page 31 MC81F4204 INTH INTH 0.8 V 0.2 V 0.8 V 0.2 V Output Data Figure 7-3 Serial Interface Data Transfer Timing April 24, 2012 Ver.1.41...

  • Page 32: Data Retention Voltage In Stop Mode

    MC81F4204 7.8 Data Retention Voltage in Stop Mode ° ° = - 40 C to + 85 C, V = 2.2 V to 5.5 V) Parameter Symbol Conditions Units Data retention supply V DDDR – – voltage V DDDR = 2.2V...

  • Page 33: Lvr (Low Voltage Reset) Electrical Characteristics

    MC81F4204 7.9 LVR (Low Voltage Reset) Electrical Characteristics ° ° = - 40 C to + 85 C, V = 2.2 V to 5.5 V) Parameter Symbol Conditions Units LVR voltage VLVR – Hysteresis voltage of – – △V Current consumption...

  • Page 34: Main Clock Oscillator Characteristics

    MC81F4x16 7.11 Main clock Oscillator Characteristics ° ° = - 40 C to + 85 C, V = 2.2 V to 5.5 V) Oscillator Parameter Conditions Typ. Units 2.2 V – 5.5 V – Main oscillation Crystal 2.7 V – 5.5 V –...

  • Page 35: External Rc Oscillation Characteristics

    MC81F4x16 7.12 External RC Oscillation Characteristics ° ° = - 40 C to + 85 C, V = 2.2 V to 5.0 V) Parameter Symbol Conditions Typ. Units RC oscillator freque- ° fERC – = 25 ncy Range (1) ° V DD =5.0V, T A = 25 –...

  • Page 36: Internal Rc Oscillation Characteristics

    MC81F4x16 7.13 Internal RC Oscillation Characteristics ° ° = - 40 C to + 85 C, V = 2.2 V to 5.0 V) Parameter Symbol Conditions Typ. Units ° V DD =5.0V, T A = 25 RC oscillator fIRC V DD =5.0V, frequency (1) -20% °...

  • Page 37: Operating Voltage Range

    MC81F4x16 7.15 Operating Voltage Range (Main OSC frequency) 12.0MHz 8.0MHz 4.2MHz 1.0MHz Supply voltage (V) Figure 7-10 Operating Voltage Range April 24, 2012 Ver.1.41...

  • Page 38: Typical Characteristics

    MC81F4x16 7.16 Typical Characteristics These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
  • Page 39 MC81F4204 Figure 7-16 I at V Figure 7-17 I at V Figure 7-18 V Figure 7-19 V April 24, 2012 Ver.1.41...
  • Page 40 MC81F4204 Figure 7-20 V Figure 7-21 V Figure 7-22 V Figure 7-23 V April 24, 2012 Ver.1.41...
  • Page 41 MC81F4204 Figure 7-25 Ext. R/C OSC Freq. - V at 25℃ Figure 7-24 8MHz Internal OSC Freq. - V Figure 7-26 Ext. R/C OSC Freq. - V at 85℃ Figure 7-27 Ext.l R/C OSC Freq. - V at -40℃ April 24, 2012 Ver.1.41...

  • Page 42: Rom Option

    01: 2.7V LVR Level Selection bits LVRS 10: 3.0V 11: 4.0V – bit4 – bit3 Not used MC81F4204 000: External RC 001: Internal RC; 4MHz 010: Internal RC; 2MHz 011: Internal RC; 1MHz OSCS Oscillator Selection bits 100: Internal RC; 8MHz...

  • Page 43: Read Timing

    MC81F4204 8.2 Read Timing Volt OSC. VDD rising curve Stabilization Time 32 ms 32 ms @4MHz level Time Rom option Reset process Read Start & Main program Start Figure 8-1 ROM option read timing diagram Rom option is affected 32 mili-second (typically) after VDD cross the POR level. More precisely saying, the 32 mili-second is the time for 1/2 counting of 1024 divided BIT with 4 MHz internal OSC.

  • Page 44: Memory Organization

    MC81F4204 9. MEMORY ORGANIZATION This MCU has separated address spaces for the *program memory* and the *data Memory*. The program memory is a ROM which stores a program code. It is not possible to write a data at the program memory while the MCU is running.
  • Page 45 MC81F4204 These registers also have increment, decrement, comparison and data transfer functions, and they can be used as a simple accumulator. Figure 9-3 Stack Pointer Stack Pointer: Stack Pointer is an 8-bit register which indicates the current ‘push’ point in the stack area.
  • Page 46 MC81F4204 Figure 9-5 PSW ( Program Status Word ) Registers Program Status Word: Program Status Word (PSW)contains several bits that reflect the current state of the CPU. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag.
  • Page 47 MC81F4204 This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. April 24, 2012 Ver.1.41...

  • Page 48: Program Memory

    MC81F4204 9.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 4K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 9-6 shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH.
  • Page 49 MC81F4204 Figure 9-7 PCALL and TCALL Memory Area April 24, 2012 Ver.1.41...
  • Page 50 MC81F4204 Example : Usage of TCALL   LDA #5  TCALL 0FH               ;1BYTE INSTRUCTION  :                      ;INSTEAD OF 3 BYTES  :                      ;NORMAL CALL    ;TABLE CALL ROUTINE    FUNC_A :  LDA LRG0  RET    FUNC_B : LDA LRG1  RET    ;TABLE CALL ADD. AREA    ORG 0FFC0H               ;TCALL ADDRESS AREA  DW FUNC_A  DW FUNC_B    April 24, 2012 Ver.1.41...

  • Page 51: Data Memory

    Figure 9-8 shows the internal Data Memory space available. Data Memory is divided into three groups, a user RAM, Stack memory and Control registers. 9.4 User Memory The MC81F4204 has a 192 bytes user memory (RAM). RAM pages are selected by the RPR register. RAM PAGE SELECT REGISTER 00E1H...

  • Page 52: Stack Area

    MC81F4204 9.5 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack;...
  • Page 53 MC81F4204 Address Register Name Mnemonic Initial value 00B0H Timer 0 Status And Control Register T0SCR – 0 0 0 0 0 0 0 00B1H Timer 0 Data Register T0DR 1 1 1 1 1 1 1 1 00B2H Timer 0 Counter Register...
  • Page 54 MC81F4204 Address Register Name Mnemonic Initial value 00DCH R3 Port Control Register High Byte R3CONH – – 0 0 0 0 0 0 00DDH R3 Port Control Register Low Byte R3CONL 1 0 0 1 1 – – – 00E1H RAM Page Selection Register –...
  • Page 55 MC81F4204 Address Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0SCR 00B0H – T0MS T0CC T0CS T0DR 00B1H Timer 0 Data Register T0CR 00B2H Timer 0 Counter Register T1SCR 00B3H –...
  • Page 56 MC81F4204 Address Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R3CONH 00DCH – – R3CONL 00DDH – – – 00E1H – – – – – – – RPR0 BUZR 00E5H BUCK...

  • Page 57: Addressing Modes

    MC81F4204 9.7 Addressing modes The MC81Fxxxx series MCU uses six addressing modes; Register Addressing Immediate Addressing Direct Page Addressing Absolute Addressing Indexed Addressing Indirect Addressing Register Addressing Register addressing means to access to the data of the A, X, Y, C and PSW registers. For Example ‘ASL ( Arithmetic Shift Left )’...
  • Page 58 MC81F4204 Direct Page Addressing -> dp In this mode, an address is specified within direct page. Current accessed page is selected by RPR(RAM Page select Register). And dp( Direct Page ) is an one byte data which indicates the target address in the current accessed page.
  • Page 59 MC81F4204 Example : Addressing accesses the address 0135 regardless of G-flag.        :          ;When G = 0      INC !0135h  ;increase ROM[135h]       :          ;op code is 98h       :    Indexed Addressing X indexed direct page (no offset) → {X} In this mode, an address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example :  ...
  • Page 60 MC81F4204 Example:        :          ;When G = 0, X = 35h  LDA {X}+    ;A = ROM[(RPR<<8) + X]   :          ; and X = X + 1       :          ;op code is 0DBh       :    X indexed direct page (8 bit offset) → dp+X This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in direct page.
  • Page 61 MC81F4204 Example :            :             ;when Y = 55h  LDA !0FA00H+Y      ;op code is D5h       :    Indirect Addressing Direct page indirect → [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y.
  • Page 62 MC81F4204 X indexed indirect → [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which i s determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example :  ...
  • Page 63 MC81F4204 Absolute indirect → [!abs] The program jumps to address specified by 16-bit absolute address. Example :        :             ;when G = 0  JMP [0E025h]   ;op code is 1Fh       :    April 24, 2012 Ver.1.41...

  • Page 64: I/O Ports

    MC81F4204 10. I/O PORTS The MC81F4204 microcontroller has three I/O ports, P0,P1 and P3. The CPU accesses ports by writing or reading port register directly. The R0 port has following features, - 1-bit programmable I/O port. - Schmitt trigger input, push-pull or open-drain output mode can be selected by software.

  • Page 65: R0 Port Registers

    010: Alternative function (AN4) 011: Alternative function (SO) 1xx: Output mode, push-pull – bit1 Not used for MC81F4204 1: Output mode, push-pull R05/AN3/EXT3/SI/T1O/PWM1O 0: depend on R0CONM.7 – .6 1. When R0CONH.0 is selected to ‘1’, R05 is push-pull output mode.
  • Page 66 MC81F4204 R0CONM – R03~05 R0 PORT CONTROL MIDDLE REGISTER 00C7H A reset clears the R0CONM register to ‘00H’, makes R04-R03 pins input mode. You can use R0CONM register setting to select input or output mode (open-drain or push-pull) and enable alternative functions.
  • Page 67 – – Reset value: 00H – – – bit7 – bit6 Not used for MC81F4204 00: Schmitt trigger input mode (EC0/EXT0) 01: Output mode, open-drain R02/AN0/EXT0/EC0 10: Alternative function (AN0) 11: Output mode, push-pull 00: Schmitt trigger input mode (EXT11)
  • Page 68 MC81F4204 PUR0 R0 PORT PULL-UP ENABLE REGISTER 00C9H Using the PUR0 register, you can configure pull-up resistors to individual R07-R00 pins. PUR0 PUR07 PUR06 PUR05 PUR04 PUR03 PUR02 PUR01 PUR00 Reset value: 00H 0: Disable pull-up resistor PUR07 R07 Pull-up Resistor Enable Bit...

  • Page 69: R1 Port Registers

    R1CONH register must also be enabled in the associated peripheral module. R1CONH Reset value: ----_--01b – bit7 – bit2 Not used for MC81F4204 00: Schmitt trigger input mode 01: Output mode, open-drain 10: Not available 11: Output mode, push-pull April 24, 2012 Ver.1.41...
  • Page 70 000: Schmitt trigger input mode (EXT8) 001: Output mode, open-drain 010: Alternative function (AN7) R12/AN7/EXT8/PWM3O/BUZO 011: Alternative function (PWM3O) 101: Alternative function (BUZO) 111: Output mode, push-pull Others: Not available – bit1 – bit0 Not used for MC81F4204 April 24, 2012 Ver.1.41...
  • Page 71 – Reset value: 00H – – – – bit7 – bit5 Not used for MC81F4204 000: Schmitt trigger input mode (EXT7) 001: Output mode, open-drain R11/AN6/EXT7/PWM2O 010: Alternative function (AN6) 011: Alternative function (PWM2O) 1xx: Output mode, push-pull 00: Schmitt trigger input mode (EXT6)
  • Page 72 Using the PUR1 register, you can configure pull-up resistors to individual R17-R10 pins. PUR1 PUR14 PUR13 PUR12 PUR11 PUR10 Reset value: 00H bit7 – bit5 Not used for MC81F4204 0: Disable pull-up resistor PUR14 R14 Pull-up Resistor Enable Bit 1: Enable pull-up resistor...

  • Page 73: R3 Port Registers

    – – Reset value: 00H – – – bit7 – bit6 Not used for MC81F4204 00: Schmitt trigger input mode 01: Not available R35/RESETB ( *note* ) 10: Output mode, open-drain 11: Not available 00: Schmitt trigger input mode 01: Schmitt trigger input pull-up mode...
  • Page 74 001: Input pull-up mode R31/AN14 010: Alternative function (AN14) 011: Output mode, open-drain 1xx: Output mode, push-pull bit2 – bit0 Not used for MC81F4204 R3 PORT DATA REGISTER 00C3H Reset value: --00_011-b In input mode, it represents the R3 port status.

  • Page 75: Interrutp Controller

    BTIR Figure 11-1 Block Diagram of Interrupt The MC81F4204 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). And 21 interrupt sources are provided.

  • Page 76: Registers

    Timer 2 Match Interrupt Enable Bit 1: Enable interrupt 0: Disable interrupt T2OVIE Timer 2 Overflow Interrupt Enable Bit 1: Enable interrupt bit 1 – bit 0 Not used for MC81F4204 IENL INTERRUPT ENABLE LOW REGISTER 00EBH IENL SIOIE WDTIE –...
  • Page 77 0: Interrupt request flag is not pending, request flag bit clear T2OVIR Timer 2 Overflow Interrupt Request Flag 1: Interrupt request flag is pending bit 1 – bit 0 Not used for MC81F4204 IRQL INTERRUPT REQUSEST LOW REGISTER 00EDH IRQL SIOIR WDTIR –...

  • Page 78: Interrupt Sequence

    Timer 2 Overflow Interrupt Flag Bit 1: Generation bit 1 – bit 0 Not used for MC81F4204 Note: When you use ‘Shard Interrupt Vector’, those INTFH is used to recognize which interrupt is generated. See ‘11.4 Shared Interrupt Vector’ on page 81 for more information.
  • Page 79 MC81F4204 Figure 11-2 Timing chart of Interrupt Acceptance and Interrupt Return Instruction A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to “1”...
  • Page 80 MC81F4204 Example: Register save using push and pop instructions. INTxx :    PUSH A  PUSH X  PUSH Y  ;SAVE ACC.  ;SAVE X REG.  ;SAVE Y REG.    ;; interrupt processing ;;    POP Y  POP X  POP A  RETI  ;RESTORE Y REG.  ;RESTORE X REG.  ;RESTORE ACC.  ;RETURN  April 24, 2012 Ver.1.41...

  • Page 81: Brk Interrupt

    MC81F4204 11.3 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.

  • Page 82: Multi Interrupt

    MC81F4204 11.5 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible.

  • Page 83: Interrupt Vector & Priority Table

    MC81F4204 11.6 Interrupt Vector & Priority Table Address Interrupt INT number Priority 0FFE0H Basic Interval Timer INT0 15 ( lowest priority) 0FFE2H Watchdog Timer INT1 0FFE4H 0FFE6H Timer 2 match/overflow INT3 0FFE8H Timer 1 match/overflow INT4 0FFEAH Timer 0 match/overflow...

  • Page 84: External Interrupts

    MC81F4204 12. EXTERNAL INTERRUPTS The external interrupt pins are edge triggered depending on the ‘external interrupt registers’. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. 12.1 Registers EINT0H – EXT 2~5 / R04~R07...
  • Page 85 MC81F4204 EINT0L – EXT 10,11,0,1 / R00~R03 R0 PORT EXTERNAL INTERRUPT ENABLE LOW REGISTER 00CBH A reset clears the EINT0L register to ‘00H’, disables EXT1-EXT0, EXT11-EXT10 interrupt. You can use EINT0L register setting to select Disable interrupt or Enable interrupt (by falling, rising, or both falling and rising edge).
  • Page 86 Reset value: 00H – – – – – bit7 – bit4 Not used for MC81F4204 EXT9IR R03/EXT9 External Interrupt Request Flag 0: Interrupt request flag is not pending, request flag bit clear EXT8IR R02/EXT8 External Interrupt Request Flag R01/EXT7 External Interrupt Request Flag...

  • Page 87: Procedure

    MC81F4204 EINTF EXTERNAL INTERRUPT FLAG REGISTER 00CDH EINTFH EXT0IF EXT2IF EXT4IF EXT7IF EXT8IF EXT9IF EXT10IF EXT11IF Reset value: 00H EXT0IF EXT0 External Interrupt Flag EXT2IF EXT2 External Interrupt Flag EXT4IF EXT4 External Interrupt Flag 0: Not generated EXT7 External Interrupt Flag...

  • Page 88: Oscillation Circuits

    MC81F4204 13. OSCILLATION CIRCUITS There are few example circuits for main oscillators. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

  • Page 89: Pcb Layout

    MC81F4204 Xout and Xin pins can be used as normal pins Figure 13-4 Internal RC Oscillator 13.2 PCB Layout For reference, here is a example layout for oscillator circuit. Figure 13-5 Layout of Oscillator PCB circuit Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors.

  • Page 90: Basic Interval Timer

    MC81F4204 14. BASIC INTERVAL TIMER The MC81F4204 has one 8-bit Basic Interval Timer that is free-run and can not be stopped except when peripheral clock is stopped. The Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BTIF).

  • Page 91: Registers

    WDTON BTCL Reset value: 17H – – – – bit7 – bit5 Not used for MC81F4204 0: Operate as 7-bit timer WDTON Watchdog Timer Enable Bit 1: Enable Watchdog timer 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to “0”,...
  • Page 92 MC81F4204 A 8 bit count register for the basic interval timer. April 24, 2012 Ver.1.41...

  • Page 93: Watch Dog Timer

    MC81F4204 15. WATCH DOG TIMER Figure 15-1 Block diagram of Basic Interval Timer/Watchdog Timer The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request.

  • Page 94: Registers

    MC81F4204 15.1 Registers WDTR WATCHDOG TIMER REGISTER 00F4H WDTR WDTCL WDTCMP Reset value: 7FH 0: Free-run count 1: When the WDTCL is set to “1”, binary WDTCL Watchdog Timer Clear Bit counter is cleared to “0”. And the WDTCL becomes “0” automatically after one machine cycle.

  • Page 95: Timer 0/1

    MC81F4204 16. Timer 0/1 The 8-bit timer 0/1 are an 8-bit general-purpose timer. Timer 0/1 have three operating modes, you can select one of them using the appropriate T0SCR/T1SCR setting: - Interval timer mode (Toggle output at T0O/T1O pin) - Capture input mode with a rising or falling edge trigger at EXT1/EXT3 pin - PWM mode (PWM0O/PWM1O) 16.1 Registers...
  • Page 96 T0OVIF(IRQH.6), is automatically cleared. T0SCR T0MOD T0MS T0CC T0CS Reset value: 00H Not used for MC81F4204 00: Interval mode (T0O) 01: PWM mode (OVF and match T0MS Timer 0 Mode Selection Bit interrupt can occur) 1X: Capture mode (OVF can occur)
  • Page 97 MC81F4204 T1DR TIMER 1 DATA REGISTER 00B4H T1DR One byte register Reset value: FFH A 8-bit compare value register for the timer 1 match interrupt. T1CR TIMER 0 COUNTER REGISTER 00B5H T1CR One byte register Reset value: 00H A 8-bit count register for the timer 1...
  • Page 98 – T1MS T1CC T1CS Reset value: 00H – bit7 Not used for MC81F4204 00: Interval mode (T1O) 01: PWM mode (OVF and match T1MS Timer 1 Mode Selection Bit interrupt can occur) 1X: Capture mode (OVF can occur) 0: No effect...

  • Page 99: Timer 0 8-Bit Mode

    MC81F4204 16.2 Timer 0 8-Bit Mode Figure 16-1 8-bit Timer 0 Block Diagram Timer 0 has the following functional components: Clock frequency divider (fxx divided by 2048, 512, 128, 32, 16, 8, 4, 2) with multiplexer External clock input pin, EC0 (R02)
  • Page 100 MC81F4204 Function Description Interval Timer Mode A match signal is generated and T0O pins are toggled when the T0CR register value equals the T0DR register value. The match signal generates a timer match interrupt and clears the T0CR register. Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the PWM0O pin.

  • Page 101: Timer 1 8-Bit Mode

    MC81F4204 16.3 Timer 1 8-Bit Mode Figure 16-2 8-bit Timer 1 Block Diagram Timer 1 has the following functional components: Clock frequency divider (fxx divided by 1024, 256, 64, 16, 8, 4, 2, 1) with multiplexer External clock input pin, EC1 (R04)
  • Page 102 MC81F4204 Function Description Interval Timer Mode A match signal is generated and T1O pins are toggled when the T1CR register value equals the T1DR register value. The match signal generates a timer match interrupt and clears the T1CR register. Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the PWM1O pin.

  • Page 103: Timer 2

    MC81F4204 17. Timer 2 The 8-bit timer 2 is an 8-bit general-purpose timer. Timer 2 have two operating modes, you can select one of them using the appropriate T2SCR setting: - Interval timer mode (Toggle output at T2O pin) - Capture input mode with a rising or falling edge trigger at EXT5 pin 17.1 Registers...
  • Page 104 T2CC T2CS Reset value: 00H – – bit7 - bit6 Not used for MC81F4204 0: Interval mode (T2O) T2MS Timer 2 Mode Selection Bit 1: Capture mode (OVF can occur) 0: No effect 1: Clear the Timer 2 counter (When...

  • Page 105: Timer 2 8-Bit Mode

    MC81F4204 17.2 Timer 2 8-Bit Mode Figure 17-1 8-bit Timer 2 Block Diagram Timer 2 has the following functional components: Clock frequency divider (fxx divided by 1024, 256, 64, 16, 8, 4, 2, 1) with multiplexer External clock input pin, EC2 (R06)
  • Page 106 MC81F4204 Function Description Interval Timer Mode A match signal is generated and T2O pins are toggled when the T2CR register value equals the T2DR register value. The match signal generates a timer match interrupt and clears the T2CR register. Capture Mode In capture mode, you have to set EXT5 interrupt.

  • Page 107: High Speed Pwm

    18. High Speed PWM Figure 18-1 High Speed PWM Block Diagram The MC81F4204 has two high speed PWM (Pulse Width Modulation) function which shared with Timer2. In PWM mode, the R11/PWM2O, R12/PWM3O, pins operate as a 10-bit resolution PWM output port.
  • Page 108 MC81F4204 over. And it can be maintained the duty value at present output when changed only period value shown as Example of PWM2. As it were, the absolute duty time is not changed in varying frequency. When user need to change mode from the Timer2 mode to the PWM mode, the Timer2 Note : should be stopped firstly, and then set period and duty register value.

  • Page 109: Registers

    Reset value: 0-H – – – – bit 7 Not used for MC81F4204 0: PWM 3 duty active low POL3 PWM 3 Polarity Selection Bit 1: PWM 3 duty active high 0: PWM 2 duty active low PWM 2 Polarity Selection Bit...
  • Page 110 MC81F4204 PWM2DR PWM 2 DATA REGISTER 00D0H PWM2DR One byte register Reset value: FFH A 8-bit data register for lower bits of 10-bit PWM 2 duty value. PWM3DR PWM 3 DATA REGISTER 00D1H PWM3DR One byte register Reset value: FFH A 8-bit data register for lower bits of 10-bit PWM 3 duty value.

  • Page 111: Buzzer

    MC81F4204 19. BUZZER Figure 19-1 Buzzer Driver Block Diagram The buzzer driver consists of 8-bit binary counter, the buzzer period data register BUPDR, and the buzzer driver register BUZR, the clock selector. It generates square-wave which is very wide range frequency (244 Hz ~ 250 KHz at f = 8MHz) by user programmable counter.

  • Page 112: Registers

    1: Enable Buzzer 0: No effect BURL Buzzer Data Reload Bit 1: Reload buzzer data to buffer – bit3 – bit1 Not used for MC81F4204 BUPDR BUZZER PERIOD DATA REGISTER 00E6H BUPDR One byte register Reset value: FFH A 8-bit data register for the buzzer period value.

  • Page 113: Frequency Table

    MC81F4204 19.2 Frequency table System Clock = 4MHz BUCK :01 = div16 frequency unit = Low nibble of BUPDR High nibble 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.788 3.676 3.571 3.472...
  • Page 114 MC81F4204 April 24, 2012 Ver.1.41...

  • Page 115: Bit Adc

    MC81F4204 20. 12-BIT ADC ADCH (Select one input pin of the assigned pins) Clock ADCLK Selector EOC Flag Input Pins Comparator Control Logic AN14 Reference Voltage ADDRH (R), ADDRL (R) Vref AVss Figure 20-1 A/D Converter Block Diagram The 12-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the 1` input channels to equivalent 12-bit digital values.

  • Page 116: Registers

    MC81F4204 20.1 Registers ADMR A/D MODE REGISTER 00BDH ADMR SSBIT ADCLK ADCH Reset value: 00H After reset, the start/stop bit is turned off. You can select only one analog input channel at a time. Other analog input (AD0-AD8,AD14,BGR) can be selected dynamically by manipulating the ADCH.

  • Page 117: Procedure

    MC81F4204 A 8-bit data register for lower 4-bits of the 12-bit ADC result. 20.2 Procedure To do the A/D converting, follow these basic steps: Set the ADC pins as the alternative mode. Set the ADMR register for - setting ADC channel - setting Clock - clearing the ‘End of Conversion’...

  • Page 118: Internal Reference Voltage Levels

    MC81F4204 20.4 Internal Reference Voltage Levels In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must be remained within the range V to V Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step.

  • Page 119: Serial I/O Interface

    MC81F4204 21. SERIAL I/O INTERFACE Figure 21-1 SIO Block Diagram Serial I/O interface modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: 8-bit control register (SIOCR) Clock selector logic...

  • Page 120: Registers

    MC81F4204 21.1 Registers SIOCR SERIAL I/O INTERFACE CONTROL REGISTER 00E7H A reset clears the SIOCR register value to "00H". Whit this value, internal clock source and receive- only mode are selected and the 3-bit counter is cleared. The data shift operation is disabled. The selected data direction is MSB-first.

  • Page 121: Procedure

    MC81F4204 Baud rate = (fxx/4) / (SIOPS+1) 21.2 Procedure To program the SIO module, follow these basic steps: 1. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the R0CONM, R0CONH register if necessary. - If one side uses a internal clock, the other side must use a external clock.

  • Page 122: Reset

    MC81F4204 22. RESET 22.1 Reset Process Figure 22-1 Timing Diagram After Reset When the reset event is occurred, there is a ‘stabilization time’ at the beginning. This time is counted from 00h to FFh by BIT. So it takes 1/(fxin/1024) * 256 second.

  • Page 123: Reset Sources

    MC81F4204 22.2 Reset Sources Figure 22-2 Reset Sources Diagram There are four reset sources in MC81F4204. Those are external reset, watch dog timer reset, power on reset and low voltage reset. 22.3 Reset Circuit When the external reset is enabled and the input signal of RESET pin is going to low for a while and going to high, the external reset is occurred.( See ‘7.7 Serial I/O Characteristics’...

  • Page 124: Watch Dog Timer Reset

    MC81F4204 Figure 22-3 Reset circuit Example 22.4 Watch Dog Timer Reset See ‘15. WATCH DOG TIMER’ on page 93. April 24, 2012 Ver.1.41...

  • Page 125: Power On Reset

    MC81F4204 22.5 Power On Reset There is a internal power on reset circuit internally. We simply call it POR. POR occurs the reset event when VDD is rising over the POR level. Note that, POR can be enabled and disabled by the PORC register. And default setting is ‘POR enable’.

  • Page 126: Power Down Operation

    MC81F4204 23. POWER DOWN OPERATION In the power-down modes, power consumption is reduced considerably. For applications where power consumption is a critical factor, device provides two kinds of power saving functions, STOP mode and SLEEP mode. Table 23-1 on page 131 shows the status of each Power Saving Mode. SLEEP mode is entered by the SSCR register to “0Fh”.
  • Page 127 MC81F4204 Note : After SLEEP mode, at least one or more NOP instruction for data bus pre-charge time should be written. LDM SSCR,#0FH ;for data bus pre-charge time ;for data bus pre-charge time Figure 23-1 SLEEP Mode Release Timing by External Interrupt Figure 23-2 Timing of SLEEP Mode Release by Reset April 24, 2012 Ver.1.41...

  • Page 128: Stop Mode

    MC81F4204 23.2 Stop Mode In the Stop mode, the main oscillator, system clock and peripheral clock is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up.
  • Page 129 MC81F4204 Release the STOP mode The source for exit from STOP mode is hardware reset, external interrupt, Timer(EC0,1,2), SIO. Reset re-defines all the Control registers but does not change the on-chip RAM. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction.
  • Page 130 MC81F4204 Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms. Figure 23-4 STOP Mode Release Timing by External Interrupt Figure 23-5 Timing of STOP Mode Release by Reset...

  • Page 131: Sleep Vs Stop

    MC81F4204 23.3 Sleep vs Stop Peripheral STOP Mode SLEEP Mode Stop Stop Retain Retain Basic Interval Timer Stop Operates Continuously Watchdog Timer Stop Operates Continuously Timer/Counter Stop (The event counter can Operates Continuously operate normally ) Buzzer, ADC Stop Operates Continuously...

  • Page 132: Changing The Stabilizing Time

    MC81F4204 23.4 Changing the stabilizing time After reset or wake up from the stop/sleep mode, there is a stabilizing time to make sure the system oscillation is stabilized. Actually the stabilizing time is the basic interval timer’s one cycle time.
  • Page 133 MC81F4204 In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port. In the left case, much current flows from port to GND. Figure 23-7 Application Example of Unused Output Port...

  • Page 134: Emulator

    MC81F4204 24. EMULATOR ⑤ ① ② ④ ③ ⑥ ⑧ ⑦ April 24, 2012 Ver.1.41...
  • Page 135 MC81F4204 Mark Name Description SW5.1 – SELL4416 Those two switch are used to select the device mode SW5.1 :On & SW5.2:On : 4432 mode SW5.2 – SELL4204 SW5.1 :Off & SW5.2:On : 4416 mode SW5.1 :On & SW5.2:Off : 4204 mode ①...
  • Page 136 MC81F4204 Mark Name Description A Oscillator socket ④ A Crystal/Resonator socket A capacitor socket for crystal ⑤ A capacitor socket for crystal Register socket for External RC Oscillator SW2 – EVA PWR SEL Eva.Board power source selection switch ⑥ User’s power source is supplied from the connector V_USER(⑦) which is described below.

  • Page 137: In System Programming

    MC81F4204 25. IN SYSTEM PROGRAMMING 25.1 Getting Started The In-System Programming (ISP) is an ability to program the code into the MCU while it is installed in a complete system. USB_SIO_ISP uses both USB to communicate with PC and SIO to communicate with MCU. That is why we call it as ‘USB_SIO_ISP’.

  • Page 138: Basic Isp S/W Information

    MC81F4204 25.2 Basic ISP S/W Information Figure 25-1 ISP Software The Figure 25-1 is the USB_SIO_ISP software based on MS-Windows. This software supports only SIO_ISP type devices. Function Description Load File Load the data from the selected file storage into the memory buffer.
  • Page 139 MC81F4204 Erase Erase the data in your target MCU before programming it. Set the configuration data of target MCU. The security locking is set with this Option Selection button. Progam the configuration data of target MCU. The security locking is Option Write performed with this button.

  • Page 140: Hardware Conditions To Enter The Isp Mode

    MC81F4204 25.3 Hardware Conditions to Enter the ISP Mode Anytime RESET/ Vpp pin goes +9V, the MCU entering an ISP mode except RESET/Vpp pin is output mode(See note1). User Target Board User reset circuitry USB-SIO-ISP B/D VDD(+5v) 10-pin connector 0.1uF 75KΩ...

  • Page 141: Entering Isp Mode At Power On Time

    MC81F4204 25.4 Entering ISP mode at power on time Basically anytime +9v signal is forced to RESET/Vpp pin, the MCU is entering into ISP mode. But it makes trouble when the RESET/Vpp pin is output mode. Because the +9v signal is clashing with the port’s output voltage.

  • Page 142: Usb-Sio-Isp Board

    MC81F4204 25.5 USB-SIO-ISP Board Connect USB -mini type cable Figure 25-3 USB-SIO-ISP Board April 24, 2012 Ver.1.41...

  • Page 143: Instruction Set

    MC81F4204 26. INSTRUCTION SET 26.1 Terminology List Accumulator X - register Y - register Program Status Word #imm 8-bit Immediate data Direct Page Offset Address !abs Absolute Address Indirect expression Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit...

  • Page 144: Instruction Map

    MC81F4204 ↔ Exchange Equal ≠ Not Equal 26.2 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC ″...

  • Page 145: Instruction Set

    MC81F4204 26.3 Instruction Set Arithmetic / Logic FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC ADC #imm ADC dp ADC dp + X ADC !abs Add with carry. NV--H-ZC A ← ( A ) + ( M ) + C ADC !abs + Y...
  • Page 146 MC81F4204 FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC CMP [ dp ] + Y CMP { X } CMPX #imm Compare X contents with memory contents N-----ZC CMPX dp ( X ) - ( M ) CMPX !abs CMPY #imm...
  • Page 147 MC81F4204 FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC INC dp + X INC !abs INC X INC Y LSR A Arithmetic shift left LSR dp 7 6 5 4 3 2 1 0 “0” N-----ZC LSR dp + X LSR !abs Multiply : YA ←...
  • Page 148 MC81F4204 FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } Test memory contents for negative or zero TST dlp N-----Z- ( dp ) –...
  • Page 149 MC81F4204 Register / Memory Operation FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC LDA #imm LDA dp LDA dp + X LDA !abs Load accumulator A ← ( M ) LDA !abs + Y N-----Z- LDA [ dp + X ]...
  • Page 150 MC81F4204 FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC X-register auto-increment : STA { X }+ ( M ) ← A, X ← X + 1 STX dp Store X-register contents in memory -------- STX dp + Y ( M ) ← X...
  • Page 151 MC81F4204 16 BIT manipulation FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC 16-bits add without carry ADDW dp NV--H-ZC YA ← ( YA ) + ( dp + 1 ) ( dp ) Compare YA contents with memory pair contents :...
  • Page 152 MC81F4204 BIT manipulation FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC Bit AND C-flag : C ← ( C ) ∧ ( M.bit ) AND1 M.bit -------C Bit AND C-flag and NOT : AND1B M.bit -------C C ← ( C ) ∧ ~( M.bit )
  • Page 153 MC81F4204 Branch / Jump FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC BBC A.bit, rel Branch if bit clear : -------- If ( bit ) = 0, then pc ← ( pc ) + rel BBC dp.bit, rel BBS A.bit, rel...
  • Page 154 MC81F4204 FLAG BYTE CYCLE MNEMONIC OPERATION CODE NVGBHIZC U-page call M( sp ) ← ( pcH ), sp ← sp – 1, PCALL upage -------- M( sp ) ← ( pcL ), sp ← sp – 1, pcL ← ( upage ), pcH ← “0FFH”...
  • Page 155 MC81F4204 April 24, 2012 Ver.1.41...

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