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FastVision FC40 User And Reference Manual

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FASTCAMERA USB
USER' S AND REFERENCE MANUAL
FVM-00398
1

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  • Page 1 FASTCAMERA USB USER’ S AND REFERENCE MANUAL FVM-00398...

  • Page 2: Copyright Notice

    FastVision LLC. FastVision makes no warranty for the use of its products, assumes no responsibility for any error, which may appear in this document, and makes no commitment to update the information contained herein.
  • Page 3 FastVision LLC. 131 Daniel Webster Highway, #529 Nashua, NH 03060 USA Telephone: 603-891-4317 Fax: 603-891-1881 Web Site: http://www.Fast-Vision.com Email: sales@Fast-Vision.com, or support@Fast-Vision.com...

  • Page 4: Table Of Contents

    Table Of Contents COPYRIGHT NOTICE_____________________________________________ 2 USB2.0 USER’ S GUIDE TO FC13 AND FC40 __________________________ 5 The USB 2.0 Versions of Fast Camera 13 and 40___________________________________________5 Computer System Requirements ________________________________________________________5 Hardware and Software Installation _____________________________________________________6 Cables and Connectors ________________________________________________________________6 DirectX Installation___________________________________________________________________7...

  • Page 5: Usb2.0 User' S Guide To Fc13 And Fc40

    The FastViewer USB application will not interoperate with other USB cameras at the same time. You must use the FastVision camera alone when you intend to use this software. It is sufficient to un-plug your other USB cameras and you do not need to un-install their software.

  • Page 6: Hardware And Software Installation

    ARDWARE AND OFTWARE NSTALLATION Installation of the camera hardware is very simple and has only one hard rule: DO NOT CONNECT THE USB CABLE TO THE CAMERA AND COMPUTER UNTIL THE SOFTWARE HAS BEEN INSTALLED. ABLES AND ONNECTORS Operating the USB-connected FastCamera FV13 or FV40 require the use of only two cables: Standard USB 2.0 AB cable and the Camera specific power cable that can be optionally equipped with a connector for the external hardware trigger.

  • Page 7: Directx Installation

    Figure 2. The USB 2.0 A-B cable Connect the standard USB 2.0 AB computer cable to your computer but do not connect it to the camera until after the FastCamera application software is installed. IRECT NSTALLATION Proper operation of the FastCamera USB requires presence of the up-to-date DirectX support on the computer.

  • Page 8: Fastcamera Usb Operating Modes And States

    Figure 3. Fast Viewer-USB Main screen and camera controls. USB O AMERA PERATING ODES AND TATES Operation of the FastCamera USB is presumed to alternate between three main and one optional state: 1. Continuous capture is the mode when all incoming video data are stored into the circular buffer located in the camera memory.
  • Page 9 Capture state. Continuous capture mode is expected to be used as a main maintenance mode to adjust camera parameters, target and focus the camera on the object. You can end this mode only by asserting the internal or external Trigger and shifting into the Capture Completion mode.
  • Page 10 Figure 4, FastCamera Operating modes and transitions.

  • Page 11: Fast Camera-Usb Application Controls

    -USB A AMERA PPLICATION ONTROLS The Figure 3 shows grouping of camera controls responsible for operation of each camera mode. Continuous Capture and Preview Mode This is the main operating mode of the FastCamera. It is central to its operation and it has the largest set of camera controls available for this mode.
  • Page 12 The ‘ Reset’ button sends a reset command to the camera that restores its internal state from the camera internal flash memory. This is the state you find the camera in every time you power it up. You may want to force it if you find the camera is not operating after your parameter changes as you expect it to or at all.

  • Page 13: Setting Camera Capture Parameters

    Figure 5, Color24 adjustment controls for the Video Preview display. In some cases when the Visual Preview image is too dark or too bright to observe you can do a quick image adjustment using the Display-Digital Gain control. The Display-Digital Gain only affects the preview window images. If it is set to x1 then you are looking at the upper 8 bits of the ten bit pixel (9:2), if it is set to x2 you are looking at the middle 8 bits of the ten bit pixel (8:1), and if it is set to x4 you are looking at the lower eight bits (7:0).
  • Page 14 The type and relative position of the Trigger in the captured video sequence. MAGE SIZE AND POSITION By default the FastCamera is set to capture video with the full resolution of the image sensor in the camera. For various reasons that include increased capture speed and number of image frames that can be stored in the camera internal memory, you may choose to limit capture to a Region-Of-Interest (ROI) smaller than the full image frame.
  • Page 15 the frame period you have selected, after you press 'Apply-(Changes)' button. You will be given a choice between a smaller ROI height and a lower frame rate. Applying your choice the application will make the smallest possible change. Figure 7, Changing ROI of the video capture Any changes you make are not reflected in the camera until the Apply-Changes button is pressed.
  • Page 16 Figure 8, Adjusting exposure to the frame rate The more intuitive method of setting and adjusting exposure is based on observation of the Histogram or the preview video. The Histogram window insert is brought about by clicking on the Histogram button above the Preview Window. It displays the frequency plot of pixels values in the Preview Window with the lowest (darkest) values at the left side.
  • Page 17 Figure 9, Using Image Histogram to adjust exposure RIGGER OSITION IN THE APTURE UFFER The 'Trigger-Settings' button brings up the Trigger Settings dialog which allows you to choose and set the trigger mode of the camera. See Figure 10 below Figure 10, Trigger Settings dialog.
  • Page 18 The Trigger Settings dialog box controls the settings of the trigger in the camera. Normally the camera should be in free-running mode, with P2 TTL Enable checked as in the picture above. That configuration will support both, external and internal Trigger modes.

  • Page 19: Saving And Restoring Camera Settings

    Frame flashing is a sign that the exposure and frame rate are incompatible. Typically you should set this to 160 and do not change. Saving and Restoring Camera Settings The internal flash memory of the FastCamera allows you to define the eight sets of the camera parameters that can be saved and restored as needed.
  • Page 20 The Download button initiates the process of getting the images sequence from the camera memory to the host computer memory. It only works after the camera is triggered and video capture to camera memory is stopped (see preceding explanation of camera states).
  • Page 21 Figure 13, Video sequence list stored as TIFF files The first step in this mode inquires operator about location to store camera images and attributes of the TIFF files, as in the Figures 14 and 15 below.
  • Page 22 Figure 14, Selecting location to download images from the camera memory Figure 15, Selecting image file properties and download type...
  • Page 23 The image files can be recorded as the 8-bit or 16 bit TIFF files (8 or 16 bits per pixel) and the pixel shift can be helpful in adjusting gain for the 8-bit files. The 16-bit TIFF files can not be properly handled by many image viewer programs (notably the one that is shipped by Microsoft with Windows).

  • Page 24: Review Captured Video In The Camera Memory

    Figure 16, The FPN file selection Two read-only indicators in the upper right corner of the window are very useful during the image download: The 'Frame' field indicates the frame number being read back. The 'Block' field indicates the memory block number being read back (only useful to programmers).
  • Page 25 The Review Captured Video mode is only useable when the video sequence capture is finished and the mark on the Write checkbox is off. When the Review Camera button is pressed the FastViewer-USB application inquires the camera about the start of each image in the camera memory.

  • Page 26: Specific Fast Camera Issues

    The shortest exposure is limited by the software to values the camera supports. You can get down to 2 microseconds (FC13) or 2.5 microseconds (FC40). Just make sure your object is bright enough to be visible with a short exposure.
  • Page 27 The optional version of the FastCamera power supply and trigger cable assembly has a DB-9F connector which allows user connection of a TTL trigger input to the camera via the Camera's 12-pin Hirose round power connector. The connections are as follows: FUNCTION Ground.

  • Page 28: Fastcamera Test Data

    The input and outputs are 5V tolerant. Outputs have weak drive above 3.3V but may be pulled up to 5V with an external 470 Ohm resistor. The trigger input is filtered in the camera to remove glitches shorter that about 75 nanoseconds, however it is advisable to provide a 1 microsecond minimum pulse-width for edge-triggered modes and 4 microsecond minimum for the direct exposure mode.
  • Page 29 Monochrome Sensor Color Sensor Master Test Master Test Co-planarity Test Co-planarity Test Darkfield Darkfield Graywedge-16 Graywedge-16 Grayfield White Balance Gretag Macbeth DC...
  • Page 30 SMPTE 130 fps 130 fps 450 fps 450 fps 500 fps 500 fps Figure 20, Fast Camera Test Suite...

  • Page 31: Reference For The Fc13 And Fc40 Cameras

    REFERENCE FOR THE FC13 AND FC40 CAMERAS The FC13 and FC40 cameras are based on a three FPGA design, a Control FPGA which controls the timing of the sensor, a Data FPGA which handles specialized Data processing functions and communication of results via USB or camera link, and a DDR FPGA which controls the memory functions of the camera.
  • Page 32 In free-running mode the minimum frame period depends on the ROI height and the line period. When either the frame period or exposure time setting exceeds the minimum period, extra clocks are inserted between frames. A 32-bit frame time counter allows frame periods from the minimum up to 64 seconds in increments of 15 nsec.
  • Page 33 When viewing high-speed motion, the MV40 works best if the lines are read out at the maximum possible rate while additional time for exposure or frame period is inserted between frames. This maximizes the overlap in the line exposure times. Unfortunately in the non-memory readout modes with reduced output rates just the opposite must be done.
  • Page 34 width. For the MV40, limitations of the rolling shutter limit the exposure timing resolution to the line readout rate unless the exposure time exceeds the readout time. Subsequent exposures can overlap readout of the current frame in this mode. This can place further restrictions on the exposure timing resolution in both sensor types.
  • Page 35 Comparators in the Control FPGA check for changes in the DAC settings and re-load the DAC's whenever the values are changed. This can happen as a result of the host command to set camera state, or the host command to restore state from flash. ALIBRATION Both the MV13 and MV40 sensors have automated ADC calibration to reduce column-wise fixed-pattern noise.

  • Page 36: Flash Memory

    Table 2 shows the layout of flash memory. The first page is used only for main header information. Following this are eight pages for storing up to 8 camera states. FastVision reserves one of these for factory defaults #1. Any of these states can be chosen as the power-up default.
  • Page 37 Camera Control GUI to determine the camera type and its options. This data should only be programmed by FastVision. The camera GUI software must enforce this, as there is no write protection built into the Control FPGA firmware. Multibyte values are little endian.
  • Page 38 Data FPGA initialization data length in bytes Camera State to load at power on (1 to 8) Reserved for additional header / ID info Part Number, ASCII "800??-5????" Part Revision, ASCII "010" Serial Number, ASCII "XXX??????" FPGA bit stream file header from mkbin, Null terminated string Table 3 - Flash Memory Header Page AMERA...
  • Page 39 Vref2: 23 E0 Vbias1: 30 00 Vref3: 32 E8 Vbias2: 40 00 Vref4: 41 36 Vbias3: 50 00 Vln1: 54 D9 Vbias4: 60 00 Vlp: 64 D9 Vunused1: 70 00 Vclamp3: 70 00 Vunused2: 80 00 Vrstpix: 8D 17 ROI Start Pixel ROI End Pixel ROI Start Line ROI End Line...
  • Page 40 Frame Period in Pixel Clocks Exposure Delay in Pixel Clocks Serial Link Bit Period in Pixel Clocks Camera Link Readout Mode Camera Link Clock Frequency Binning Memory Options Sensor Resolution - 8/10 bit Trigger Mode (2nd Byte is Data FPGA dependent) Frame count for Multi-Trigger mode CC Mode: CC2, CC3, CC4 enable and edge select Reserved for Control FPGA / base system...

  • Page 41: Serial Camera Control Interface

    Sensor reference voltages are presented to the DAC's exactly as they are stored in the state. The order listed above is the recommended order, but other orders may work. The format for these is MS byte first with the most significant nibble indicating the command code to the DAC.
  • Page 42 The data within a command or response packet may contain 8-bit binary data with escaping as described below. The camera requires only one stop bit for framing and sends one stop bit when responding. Baud Rate To comply with the Camera Link specification, the default baud rate is 9600. The serial baud rate can be changed with a command on the serial link or via the USB port.
  • Page 43 The intent of the protocol is to allow hand typing of commands from a terminal except for long commands like flash page write that would only be done using the FastVision camera control GUI. Response Protocol Each command signals completion by sending the command character G-Z (always uppercased) followed by any command-specific response and terminated with a non- escaped carriage-return, hex 0d.
  • Page 44 To simplify command processing, commands that are handled in the Control FPGA are assigned in ascending order starting with "G," and commands for the Data FPGA are assigned in descending order starting with "Z." AMERA TATE This command takes no arguments. The camera responds with "G" followed by the current running state of the camera (512 bytes as 1024 hex digits) and a carriage-return.
  • Page 45 are sent indicating the number of bytes remaining when the operation aborted. This is usually zero, unless the FPGA re-asserted the INIT line. URRENT AMERA TATE TO LASH This command takes one argument. The argument can be 01 to 08 and indicates which of the 8 flash storage areas to store the camera settings in.
  • Page 46 0x50 Block Erase 0x82 Main memory page program through buffer 1 0x85 Main memory page program through buffer 2 The following non-write commands are also implemented with Write Flash: 0x53 Main memory Page to Buffer 1 Transfer 0x55 Main memory Page to Buffer 2 Transfer 0x60 Main memory Page to Buffer 1 Compare 0x61...
  • Page 47 the entire array if the Continuous Array Read flash command is used. All arguments are ASCII hex. The exact syntax of the Read Flash command is: 'M' <opcode> <addr> <cmd_len> <data_len> <cr> where opcode is one byte (2 hex digits), addr is 3 bytes (6 hex digits), cmd_len is one byte (2 hex digits), and data_len is four bytes (8 hex digits).
  • Page 48 'N' <addr> <data> <cr> where <addr> is 4 hex digits of offset per Table 4 and <data> is 2 to 1024 hex digits (always a multiple of 2) of data which will be stored sequentially into the current camera state as shown in Table 4. Actual registers affected by the command are updated as the data comes in, except where further synchronization is required such as multibyte values and values that change only between frames.

  • Page 49: Inter-Fpga Communications

    This command can take no arguments or it can take a 32-bit (8 hex digits) address. This command is only effective in the memory readout modes. If enabled, the CC2 line will also initiate this command allowing operation without the GUI. The Data FPGA will respond with "Y"...

  • Page 50: Embedded Soft Processor Core

    Normally the data sent to the Data FPGA from the Control FPGA is limited in bandwidth at the source, either by the host serial baud rate or the flash memory read rate. Response data from the Data FPGA, which always gets forwarded to the host, must be sent at the host baud rate.
  • Page 51 PicoBlaze reads the data at sub address 0x60 this status bit is cleared. The USB host does not have a similar status bit; however it can be safely assumed that the PicoBlaze will process characters as fast as they come in, as long as no transmission occurs between the carriage-return that completes a command and the receipt of the carriage-return that completes the response to that command.
  • Page 52 Register shadow memory for read back of 6F8 - 6FF otherwise write-only bits. 700 - 7FF I2C shared area. LAZE EGISTER All of the following registers can only be accessed when the register access enable signal is set. This is accomplished by making any access to locations 00 through 0xf6. Any access to location 0xf7 clears the register access enable signal.
  • Page 53 response to a serial trigger command Reserved. Calibrate sensor. This is a pulsed signal that schedules a calibration when this bit is written to 1. Writing this bit to zero has no effect. Actual calibration may happen much later, since the sensor control logic schedules calibration only between frames.
  • Page 54 UART FROM AMERA Writing this location sends a byte of serial data to the frame grabber. Reading gets a byte of serial data and acknowledges its receipt. See the status bit descriptions below for more information. UART S LASH ONTROL LASH AND TATUS The Bits are:...
  • Page 55 FPGA C ONFIGURATION The bits are: Bit 7 Read only "Fget8" status. This is high when the sequencer is still running from a prior operation. Bit 6 is reserved. Bit 5 FPGA Loaded on write, FPGA done on read. Writing this bit high indicates that the program has finished loading the data FPGA and enables the pinsaver muxes.
  • Page 56 obviously be overwritten without affecting the sensor registers if the sensor register write enable bit is off. The layout of these registers intentionally matches the flash state storage. TART IXEL BITS TART IXEL HIGH BITS This is the leftmost pixel in the ROI. Pixels are numbered from 0 to the sensor width - 1. This is different from the old ROI settings which worked in pixel clocks.
  • Page 57 This is the line readout time in pixel clocks - 1. I.e. the actual period is one clock more than this number. <7:0> XPOSURE ERIOD BITS <15:8> XPOSURE ERIOD BITS <23:16> XPOSURE ERIOD BITS <31:24> XPOSURE ERIOD BITS This is the desired exposure time in pixel clocks. Actual exposure time may vary, especially if readout overlaps exposure.
  • Page 58 Bit 6 Invert TTL Trigger. Setting this bit to 1 indicates the TTL trigger input on P2 is active low level, or falling edge. Bit 5 Enable TTL trigger. Set this bit to 1 to enable TTL trigger input on P2. Clear to 0 to disable TTL trigger input.

  • Page 59: Data Fpga

    Bit 1 Invert CC2. Setting this bit to 1 indicates the CC2 input is active on falling edge. Setting this bit to 0 indicates the CC2 input is active on rising edge. Bit 0 Enable Camera Link CC2. Set this bit to 1 to enable CC2 Readout Image. When enabled, the active edge of CC2 causes the current memory image to be read out.

  • Page 60: Details Of Implementation

    [2:0] = 0 IRECT FROM THE ENSOR EMORY PTIONS Sensor data is written continuously to memory with each frame overwriting the previous frame at memory location zero. If preview bit is enabled, readout to the USB runs continuously at the maximum rate of the USB port with no attempt to synchronize to the incoming frame rate.
  • Page 61 via the Frame Valid line. Bits 95:64 are the starting address of the previous frame in memory. This is a block address, not a byte address. Because of treating the DDR data as SDR at 128 bits wide, a “ word” is 16 bytes. The block to be read always starts at a 16 word boundary, thus the minimum addressable unit is 256 raw bytes of memory.
  • Page 62 Bit 7 This bit is 1 whenever the memory is enabled for writing new frames. This includes any time the memory mode is programmed for direct or FIFO, and in circular buffer mode from the time memory is reset (Z command) until all post-trigger frames have been written to memory.
  • Page 63 Bit 4 1=preview the selected frame (Y command address). (Bit3=0) The Read back count determines how many frames are returned by each Y command when bits 3 and 4 of the Memory mode are zero. Zero and one give you 1 frame for each command, 2 through 255 give you more.

  • Page 64: Troubleshooting

    TROUBLESHOOTING There are several things you can try before you call FastVision Technical Support for help: _____ Make sure the computer is plugged in. Make sure the power source is on. _____ Go back over the hardware installation to make sure that the system is properly installed.
  • Page 65 FastVision for service or replacement. Service or replacement may be covered by your warranty, depending upon your warranty. The first step is to call FastVision and request a “ Return Materials Authorization” (RMA) number. This is the number assigned both to your returning product and to all records of your communications with Technical Support.

  • Page 66: Reporting Bugs

    We will compile and run the module to track down the anomaly you’ ve found. If you do not have Internet access, or if it is inconvenient for you to get to access, copy the code to a disk, describe the error, and mail the disk to Technical Support at the FastVision address below.
  • Page 67 For documentation errors, photocopy the passages in question, mark on the page the number and title of the manual, and either FAX or mail the photocopy to FastVision. Remember to include the name and telephone number of the person we should contact if we have questions.

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