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APPOTECH CW6632B User Manual

Bluetooth 3.0 audio player soc
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CW6632B
Bluetooth 3.0 Audio Player SOC
User Manual
[CW6632B-UM-EN]
Versions: 1.0.0
Release Date: 2015-8-25

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Summary of Contents for APPOTECH CW6632B

  • Page 1 CW6632B Bluetooth 3.0 Audio Player SOC User Manual [CW6632B-UM-EN] Versions: 1.0.0 Release Date: 2015-8-25...

  • Page 2: Table Of Contents

    CPU and Memory related SFR Description ................15 Reset Generation ..........................25 Power-on Reset (POR) ......................25 System Reset ..........................25 4.2.1 LVD ............................ 26 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright © 2015, www.appotech.com. All Rights Reserved...

  • Page 3: Table Of Content

    Timer0 Features ........................ 62 7.1.2 Timer0 Special Function Registers ..................62 Timer1 ............................63 7.2.1 Timer1 Features ........................ 63 7.2.2 Timer1 Special Function Registers ..................64 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright © 2015, www.appotech.com. All Rights Reserved.
  • Page 4 SPI0 Special Function Registers ..................85 10.1.2 SPI0 Operation Guide ....................... 86 SPI1 ............................87 10.2 10.2.1 SPI1 Special Function Registers ..................88 10.2.2 SPI1 Operation Guide ....................... 90 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright © 2015, www.appotech.com. All Rights Reserved...
  • Page 5 CRC16 Special Function Registers ................... 108 LFSR16 ............................ 109 15.2 15.2.1 Features .......................... 109 15.2.2 LFSR16 Special Function Register ................... 109 LFSR32 ............................ 110 15.3 15.3.1 Features .......................... 110 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright © 2015, www.appotech.com. All Rights Reserved.
  • Page 6 USB PHY Parameters ......................123 18.5 RF Analog Blocks ........................123 18.6 19 Package Outline Dimensions ......................125 SSOP28 ........................... 125 19.1 Revision History ............................i CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright © 2015, www.appotech.com. All Rights Reserved...

  • Page 7: Product Overview

    1 Product Overview 1.1 Outline CW6632B is a highly integrated system on chip for Bluetooth v3.0 with Enhanced Data Rate (EDR). This SOC is backward-compatible with Bluetooth 2.1, 2.0 and 1.2 systems. The Bluetooth chip supports a data rate of 1M/2M/3Mbps.

  • Page 8: Applications

    SMPC/LDO &MIC Amplifier Internal RC POR/LVD Audio ADC Encryption Timing /Decryptio Recovery n Engine Real Time Battery Audio DAC Clock Charger Figure 1-1 CW6632B system architecture CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 9: Pin Definitions

    2 Pin Definitions 2 Pin Definitions 2.1 CW6632B 2.1.1 Package SSOP28 2.1.2 Pin Assignment Figure 2-1 shows the pin assignment of CW6632B. MICN USBDP USBDM MICP/VCM AVSS VDDIO/AVDD VDDHP VDDLDO CW6632B DACL VOUT1V5 DACR VBAT SSOP28 VCM_BUF/P01 XO_N XO_P VCC_VCO/...
  • Page 10 DAC VCM buffer GPIO AUXL0 UARTRX1 SDDAT1 SPI0DIN2 GPIO ADC5 IISBCLK0 GPIO SDDAT0 SPI0DOUT3/DIN3 GPIO SDCMD SPI0DIN3 GPIO ADC4 SDCLK SPI0CLK3 GPIO ADC2 SDDAT3 SPI0DOUT2 TMR3CAP/TMR3PWM CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 11 VOUT1V5 VOUT 1.5V VDDLDO LDO power input 4.2V(typ) VDDIO/AVDD Power output VDDIO 3.3V USBDM USB Negative Input/output USBDP USB Positive Input/output GPIO AUXL2 SDCMD EMIDAT0 LCD_D0 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 12: Cpu Core Information

    3.1 Architecture 3 CPU Core Information 3.1 Architecture The AXC51-CORE of CW6632B is fully compatible with the MCS-51 instruction set. The AXC51-CORE employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12MHz.
  • Page 13 C, bit addr @A+DPTR A, #data data addr, #data @Ri, #data Rn, #data SJMP code addr C, bit addr MOVC* A, @A+PC data addr, data addr CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 14 1 or 3 XCHD A, @Ri DJNZ Rn, code addr 1 or 3 MOVX A, @DPTR MOVX A, @Ri A, data addr A, @Ri CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 15: Memory Mapping

    @DPTR, A MOVX @Ri, A data addr, A @Ri, A Rn, A 3.3 Memory Mapping 3.3.1 Program Memory Mapping As illustrated in CW6632B program space is divided into 3 regions: SRAM1, SRAM2, and IROM. 0xFFFF IROM 0x6400 0x63FF SRAM2 SRAM1 0x0000...

  • Page 16: External Data Memory Mapping

    F igure 3-3. The memory space is shown divided into three blocks, which are generally referred to as the Lower 128, the Upper 128, and SFR space. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 17: Interrupt Processing

    Setting EA to logic 0 disables all interrupts regardless of the individual interrupt-enable settings. The interrupt enables and priorities are functionally identical to those of the 80C52. The CW6632B provides 3 sets of vectors entry addresses, starting from 0x0003, 0x4003 and 0x8003. The vector base address is set by DPCON [7:6].
  • Page 18 IP1.1 0x8043 0x004B IPH1.2 PORT 0x404B WKPND IE1.2 IP1.2 0x808B 0x0053 IPH1.3 SPI0 0x4053 SPI0CON.7 IE1.3 IP1.3 0x8053 0x005B IPH1.4 Timer 3 TMR3CON.7 IE1.4 0x405B IP1.4 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 19: Interrupt Priority

    0XC0 IIS_CON0 TMR2CON0 TMR2CON1 IIS_CON1 RTCON1 SECCNT OTP_ADR IRAM_ADR 0XC8 HFMCON USBCON0 USBCON1 USBCON2 USBDATA USBADR OIRAMCNT OIRAMCON 0XD0 HFMCNT ADCCON PCON2 ADCDATAL ADCDATAH COS_VALH COS_VALL CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 20: Extend Special Function Registers Mapping (Xsfr)

    PLL1DIV SDADCDON IIS_WSCNT1 PMUXCON1 IIS_ADR0 7830H IIS_DAT7 IIS_DAT6 IIS_DAT5 IIS_DAT4 IIS_DAT3 IIS_DAT2 IIS_DAT1 IIS_DAT0 IIS_DMA_RD_C IIS_DMA_RD_ IIS_DMA_WR_ IIS_DMA_WR_ 7828H IIS_BAUD SPI1CON1 IIS_ALLBIT P3DRV0 CNT0 CNT1 CNT0 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 21: Cpu And Memory Related Sfr Description

    1 = Auto increment enable DPTSL: DPSEL toggle enable 0 = DPSEL toggle disable 1 = DPSEL toggle enable EINSTEN: Extern instruction enables 0 = Disable 1 = Enable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 22 DPTR. The CW6632B offers a programmable option that allows any instructions related to data pointer to toggle the DPSEL bit automatically. This option is enabled by setting the toggle-select-enable bit (DPTSL) to logic 1.
  • Page 23 In a standard 8051, there is only an 8-bit stack pointer (SP). It can only use the internal 256 byte data memory as stack memory. To increase the stack space for more complex application, CW6632B supports a 16-bit extend stack pointer, it can use both internal data RAM and the 20K byte on-chip SRAM as stack memory.
  • Page 24 0 = Always stay at 0 1 = Normal IROMCEM: IROM CE mode control 0 = Always stay at 0 1 = Normal Register 3-10 SPMODE1 – Special mode 1 Position CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 25 Register 3-11 MEMCON – Memory Mapping Configure Position Name Default Access CC0: MIX_CODE2 mapping 0 = IROM32 map to address 0x4000~0x6fff 1 = SRAM2 map to address 0x4000~0x6fff CC1: MIX_CODE3 mapping CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 26 IE00: SINT0 interrupt enable 0 = Disable 1 = Enable Register 3-13 IE1 – Interrupt Enable 1 Position Name IE17 IE16 IE15 IE14 IE13 IE12 IE11 IE10 Default Access CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 27 IP02 IP01 IP00 Default Access IPH07, IP07: Watch Dog interrupt Priority select 11 = level 3 highest priority 10 = level 2 01 = level 1 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 28 11 = level 3 highest priority 10 = level 2 01 = level 1 00 = level 0 lowest priority Register 3-16 IPH1 – Interrupt Priority high 1 Position CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 29 IPH12, IP12: Port interrupts priority 11 = level 3 highest priority 10 = level 2 01 = level 1 00 = level 0 lowest priority IPH11, IP11: SDC interrupt priority CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 30 IPH10, IP10: USB control interrupts priority 11 = level 3 highest priority 10 = level 2 01 = level 1 00 = level 0 lowest priority CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 31: Reset Generation

    4 Reset Generation 4.1 Power-on Reset (POR) CW6632B provides an on-chip Power-On-Reset (POR) circuit to detect power-on and to reset internal logic before VDD reaches the pre-determined POR threshold voltage. When VDD=1.2V, the POR threshold voltage is set to be about 0.7V~0.9V.

  • Page 32: Lvd

    Low-Drop-Out regulator (LDO) and that supplies power to internal VDDCORE. User for such reason can momentarily monitor the VDDLDO power if externally connects to some batteries and detect if external power source starts dropping to a level that CW6632B LDO cannot tolerate and can do proper actions in the system program.

  • Page 33: Cw6632B Bluetooth 3.0 Audio Player Soc Version

    1 = LVD output is disabled 4.2.2 RTCC Reset CW6632B can be reset by RTCC second and alarm interrupt when IRTRSTEN bit in RTCON is set to 1. 4.2.3 Watchdog Reset If Watchdog timer is enabled, and WDTCON [5] is not written by 1 within watchdog overflow time period, CW6632B will be reset by Watchdog overflow.

  • Page 34: Port Wakeup Reset

    4.3 Clock System 4.3.1 Clock Control CW6632B embeds 32K/4M/12M/24M OSC internal oscillator circuits. External crystal is needed to generate a clock source. One internal PLL can generate 48MHz from the crystal clock source. One internal RC oscillator is also embedded.
  • Page 35 0 = Enable 1 = Disable Register 4-4 PCON2 – Power control 2 Position Name USBCEN TSCLK_OUT_EN EMICEN RTCCEN WDTCEN LVDCEN ADCCEN Default Access USBCEN: USB clock enable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 36 1 = Enable BASSCEN: Bass clock enable 0 = Enable 1 = Disable AUALUEN: Audio clock enable 0 = Disable 1 = Enable AGCEN: AGC clock enable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 37 10 = Select 32 KHz clock source derived from external 12MHz crystal oscillator 11 = Reserve SCSEL: System clock select 00 = Internal 512 KHz RC oscillator output CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 38 01 = Select 24MHz output 10 = Select 16MHz output 11 = Select 12MHz output Register 4-8 CLKCON2 – Clock control 2 Position Name IISREFCSEL IISBCSEL TSCLK_OUT_SEL IR32K_SEL IR_CLK_SEL Default CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 39 00 = 1MHz PLL 01 = 1MHz RC 10 = External 32 KHz or 12MHz crystal oscillator controlled by CLKCON2 [6] and CLKCON2 [7] as shown in F igure CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 40: Clock Gating

    4.3.3 Phase Lock Loop (PLL) CW6632B provides one on-chip Phase Locked Loop (PLL 48M) clock generators. The PLL has reference clock from external 32 KHz/4M/12 M crystal oscillators to provide a stable reference clock and the reference clock is multiplied to provide the final PLL output.
  • Page 41 Register 4-11 PLL1DIV – PLL1 clock div for PLL2 Position Name PLL1DIV Default Access PLL1IDV Clock = 48MH/PLL1DIV; Register 4-12 PLL1INT – PLL1 integer low Position Name PLL1INT Default CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 42 1 = enable PLL1_DIVEN: PLL1 divide enable 0 = disable 1 = enable PLL2AREF_SEL: PLL2 input reference clock analog select 00 = 12M XOSC 01 = 4M XOSC CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 43 If f0=4M, frequency dividing ratio is 15, decimal fraction part set 0. If frequency dividing ratio is 58.a, then integer set 58, decimal fraction is a*65535. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 44 4.3 Clock System PLL2 same as PLL1 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 45: Low Power Management

    (ISR), else CW6632B will execute the instruction following HOLD. When wakeup from HOLD Mode by watchdog, if watchdog reset enable, CW6632B will be reset, else if watchdog interrupt is enabled, CW6632B will enter watchdog‟s ISR. Else CW6632B will execute the instruction following HOLD.

  • Page 46: Power Down Mode

    TO enter IDLE mode, user need to write a „1‟ to IDLE register (Bit2 of PCON0). When exit IDLE mode, CW6632B will enter interrupt service subroutine if EA is enable. If EA is disabled, the instruction next to IDLE will be executed.
  • Page 47 10 = 2.2V 11 = 2.3V VDDLDO detection voltage selection（VLVDR/VLVDS V）. BORS2~BORS0： S=000 : 2.26/2.41 S=001 : 2.39/2.54 S=010 : 2.54/2.68 S=011 : 2.66/2.81 S=100 : 2.79/2.96 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 48 VD1_ENB：VDDLDO voltage detection enable 0=enable 1=disable VD2_ENB：External pin voltage detection enable. 0=enable 1=disable CURRENTSEL_R1~CURRENTSEL_R0：Modulate 3.3v LDO sleep current V18SELR1~ V18SELR0：RF part LDO output voltage selection: 00 = 1.67 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 49 Name V18SELD1 V18SELD0 Default Access V18SELD1~ V18SELD0：VDD core part LDO output voltage selection 00 = 1.67 01 = 1.75 10 = 1.83 default 11 = 1.91 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 50: General Purpose Input/Output (Gpio)

    Several GPIO are multiplexed with analog module. GPIO digital input and output must be disabled when the corresponding analog module is enabled. Table 6-2 Ports multiplexed mapping CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 51 SDDAT0 EMIDAT7 SPI0DOUT0 ADC4 SDCLK SPI0CLK3 SDCMD SPI0DIN3 SDDAT0 SPI0DOUT3/DIN3 ADC0 Ir_input 32K/xosc12m SysClk TRM1CAP UARTRX0 PORTINT/WKUP2 SPI0CLK2 TMR0PWM MUTE GPIO Ir_input SPI0CLK4 SPI1DIN1‟ DACL DACR CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 52: Port Interrupt And Wakeup

    6.4 Port interrupt and wakeup 6.4 Port interrupt and wakeup CW6632B supports Port interrupt and wakeup function. The PWKEN registers (Wakeup Enable Register) allow port to cause wakeup. The PWKEN registers are set to 0Fh upon reset. Clearing bit0-3 in the PWKEN register enables wakeup on corresponding pin.
  • Page 53 P1[x]: P1x data. Valid when P1x is used as GPIO 0 = P1x is in low state when read and output low at P1x when write CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 54 Table 6-4 PUPx register setting Set bit “x” of PxPU0 as “1” Clear bit “x” of PxPU0 as “0” Register Address Initial value P0PU Enable pull-up Disable pull-up CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 55 01 = select 500Ω pull up 1x = select 200K pull up P15PUS1,P15PUS0: 00 = select 10K pull up 01 = select 200Ω pull up 1x = reverse CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 56 P24PUS1 P23PUS1 P22PUS1 P21PUS1 P20PUS1 Default Access P27PUS1,P27PUS0: 00 = select 10K pull up 01 = select 500Ω pull up 1x = select 200K pull up CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 57 Register 6–15 P3PUS0– P3 pull up select Position Name P37PUS0 P36PUS0 P35PUS0 P34PUS0 P33PUS0 P32PUS0 P31PUS0 P30PUS0 Default Access Register 6–16 P3PUS1– P3 pull up select Position CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 58 01 = select 500Ω pull up 1x = select 200K pull up P30PUS1,P30PUS0: 00 = select 10K pull up 01 = select 500Ω pull up 1x = select 200K pull up CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 59 P12PDS1,P12PDS0: 00 = select 10K pull down 01 = select 500Ω pull down 1x = select 330Ω pull down P11PDS1,P11PDS0: 00 = select 10K pull down CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 60 00 = select 10K pull down 01 = select 500Ω pull down 1x = select 330Ω pull down P23PDS1,P23PDS0: 00 = select 10K pull down 01 = select 500Ω pull down CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 61 P36PDS1,P36PDS0: 00 = select 10K pull down 01 = reverse 1x = reverse P35PDS1,P35PDS0: 00 = select 10K pull down 01 = reverse 1x = reverse CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 62 0 = P14 Input Disabled 1 = P14 Input Enabled PIE04: P13 digital input enables bit (For ADC5 input) 0 = P13 Input Disabled 1 = P13 Input Enabled CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 63 PIE11: P21 Digital Input Enable Bit (For AUXR2 or ADC1 input) 0 = P21 digital Input Disabled 1 = P21 digital Input Enabled PIE10: P20 Digital Input Enable Bit (For AUXL2) CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 64 P07WK_EN: P07 wakeup pin3 enable bit 0 = disable 1 = enable WBEDGES: wire less board wake pin edge selection 0 = falling edge 1 = rising edge CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 65 PMUXCON4_74 PMUXCON4_30 Default Access PMUXCON4_76: P12/P13/P16/P17 Wake up enable 0 = disable 1 = enable PMUXCON4_30: P00/P01/P02/P03 Wake up enable 0 = disable 1 = enable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 66: 4 9 B W Akeup Registers

    To clear WKPNDx, write „0‟ to WKPNDx. WKPNDx will be „0‟ 2 clocks later after write „0‟ to WKPNDx. WKPNDx is cleared when PWKENx is „1‟. Register 6-31 PWKEDGE – Port wakeup Event select Position Name LDOBGOE SPI0PS1 COSEL WKEDG3 WKEDG2 WKEDG1 WKEDG0 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 67: Operation Guide

    (P0), which controls the output levels of the Port 0 pins, P00 through P07. Figure 8-1 shows the internal hardware structure and configuration registers for each pin of Port 0~3. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 68: Timers

    001 = Timer0 counts at every 2 counting source events 010 = Timer0 counts at every 4 counting source events 011 = Timer0 counts at every 8 counting source events CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 69: Timer1

    7bits pre-scaler  Counter mode (clock source from system clock or TMR1)  Capture mode (event source from CAP1)  PWM mode (PWM signal output to PWM1) CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 70: Timer1 Special Function Registers

    T1CPND: Timer1 Capture mode Pending Bit 0 = Not Pending 1 = Pending T1TIE: Timer1 over Flow Interrupt Enable Bit 0 = Interrupt Disable 1 = Interrupt Enable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 71: Timer2

    TMR1CNT will be captured to TMR1PWM when selected event occurs. 7.3 Timer2 Timer2 is a 16-bit timer/counter with a 7-bit prescaler. It can be configured as timer, counter or PWM generator. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 72: Timer2 Features

    T2TPND T2CPND T2TIE T2CIE T2PSR Default Access T2TPND: Timer2 over Flow Pending Bit 0 = Not Pending 1 = Pending T2CPND: Timer2 Capture mode Pending Bit CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 73 Note: TMR2PWM is reserved in timer/counter mode. In PWM mode, it is used as duty cycle setting. In capture mode, the value of TMR2CNT will be captured to TMR2PWM when selected event occurs. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0...

  • Page 74: Timer3

    011 = Timer3 counts at every 8 counting source events 100 = Timer3 counts at every 16 counting source events 101 = Timer3 counts at every 32 counting source events CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 75: Watchdog Timer (Wdt)

    7.5.1 Watchdog Wake up WDT can be used to wake up CW6632B from Idle, Hold or Sleep mode. RSTEN bit (WDTCON [3]) is used to determine the actions after WDT wake up. When RSTEN sets to 0, the watchdog will generate a non-reset wake up after counter overflows.

  • Page 76: Watchdog Sfr

    7.5 Watchdog Timer (WDT) next instruction.  During Sleep mode, CW6632B can be wakeup by WDT with reset.  During Deep Sleep mode, CW6632B cannot be wakeup by WDT. 7.5.2 Watchdog SFR Register 7-19 WDTCON – Watchdog control Position Name...

  • Page 77: Universal Asynchronous Receiver/Transmitter (Uart)

    0 = Disable UART module 1 = Enable UART module UTTXINV: Transmit Invert Selection Bit 0 = Transmitter output without inverted 1 = Transmitter output inverted CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 78 UART0TX0: P16 1 = Select UART0RX1 and UART0TX1 UART0RX1: P00 UART0TX1: P01 Register 8-3 UARTBAUDL – UART0 Baud Rate Low Byte Position Name UARTBAUDL Default Access CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 79: Uart1

    Transmit pin (TX) – UART1TX1 (BT_RX)  8.2.2 UART1 Special Function Registers Register 8-7 UART1CON – UART1 control Position Name UTSBS UTTXNB NBITEN UTEN TXIE RXIE OVERFLOWIE DMASEL Default CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 80 RXIF: UART RX Interrupt Flag 0 = Normal Receive or AUTO DMA mode Receive one word not done 1 = Normal Receive or AUTO DMA mode Receive one word done CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 81 Write this location will load the data to transmitter buffer. And read this location will read the data from the receiver buffer. Register 8-12 UARTDMATXCNT –UART1 DMA Transmit counter Portion Name UARTDMATXCNT Default Access Nbyte = UARTDMATXCNT + 1 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 82 Access Register 8-18 UART1LOOPCNT–UART1 DMA loop count Position Name overlowcnt dma_loop_cnt Default Access overlowcnt: less than bytes UART receive data ram size 00 = 4 bytes CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 83: Operation Guide

    Wait for PND to change to „1‟, or wait for interrupt Read received data from UART1DATA if needed Go to Step 5 to start another process if needed or turn off UART1 by UTEN. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 84 Write the start DMA address. For transmission, Write data to UARTDMATXPTR Write data to UARTDMATXCNT to kick-start a DMA transmit process 10. Wait for PND to change to „1‟, or wait for interrupt CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 85: Bt Control Register

    Register 8-22 BTCON2 – BT control register2 Position Name BTTX BTRX BTCTS Reserved BTGPIO10 BTGPIO9 BTGPIO5 BTGPIO4 Default Access write: write date to BT read: depend on BTCON1[5] CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 86: Ir Receiver

    9.1 IR frame format 9 IR receiver CW6632B provides digital IR receiver, it can receiver IR data then CPU can read IR data from IR data buffer. 9.1 IR frame format Figure 9-1 shows the IR data frame format 45ms...

  • Page 87: Ir Receiver Control Registers

    When IR clock is 32 KHz, ONEFULL*CLKCYC us is the time of IRDATA error. It is recommended to set ONEFULL to 0x5E(NOTE: ONEFULL*8 > BIT 1 cycle) Second time for the ZEROCYC. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 88 NOTE: when IR clock is 32 KHz and BEGINCNT or ENDCNT or REPEATCNT is configured to N， the detect range is N*32*cycle ~ (N*32+31)*cycle Register 9-3 IRDAT0 – IR receiver data buffer0 register CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 89: Ir Receiver Operation Guide

    9.3 IR Receiver Operation Guide 1) Configure IR clock (CLKCON2); 2) Configure IRCON1 if needed; 3) Configure IRCON0; 4) Wait IRPND or IR interrupt; 5) Read IRDAT0/1/2/3. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 90: Spi

    SPICLK (SPIIDST = 0) SPICLK (SPIIDST = 1) SAMPLE INPUT DATA OUT (SPIEDGE = 0) SAMPLE INPUT DATA OUT (SPIEDGE = 1) Figure 10-1 SPI timing CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 91: Spi0 Special Function Registers

    1 = Clock signal stay at 1 when idle SPI0EN: SPI0 enable bit 0 = SPI0 disable 1 = SPI0 enable Register 10-2 SPIBAUD – SPI0 Baud Rate CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 92: Spi0 Operation Guide

    Select master mode or slave mode Configure clock frequency when master mode is selected in step 3 Select one of the four timing mode (refer to F igure 10-1 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 93: Spi1

    11. Go to Step 8 to start another DMA process if needed or turn off SPI0 by clearing SPI0IE and SPI0EN SPI1 10.2 CW6632B SPI1 is an accelerated SPI. It can serve as master only. It can operate in normal or DMA mode. Please see PMUXCON0 bit 5 descriptions SPI1 uses 2 pins for 2 wire mode: Serial Data (SPIDIDO1) –...

  • Page 94: Spi1 Special Function Registers

    1 = Enabled ENCRYPT: SPI1 output encryption function enable 0 = Disabled 1 = Enabled NOTE: ENCRYPT and SPI1DEC cannot be 1 at the same time. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 95 Write this location will enable DMA and kick start a DMA process .Caution: do not write 0 to this register. Note Must write SPIDMACNTH, then write SPIDMACNTL, this order can‟t change ! ! ! Register 10–14 SPI1BAUD – SPI1 BAUD RATE Position CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 96: Spi1 Operation Guide

    Wait for bit SPI1PND to change to „1‟, or wait for interrupt 10. Go to Step 7 to start another DMA process if needed or turn off SPI by clearing SPI1PND and SPI1EN CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0...

  • Page 97: External Memory Interface (Emi)

    11 External Memory Interface (EMI) 11 External Memory Interface (EMI) CW6632B provides External Memory Interface (EMI) to accelerate data transfer. Figure 11-1 shows EMI timing. EMI_WEN(P3.3) EMI_DATA(P2) EMIST EMIPW EMIHT Figure 11-1 EMI timing 11.1 EMI Control Registers Register 11-1 EMICON0 – EMI control0...
  • Page 98 EMIM: EMI mode 0 = work when CPU kick start 1 = work with SPI1 DMA Register 11-3 EMIBUF – EMI output buffer Position Name EMIBUF Default Access CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 99 When EMIM = 1 and EMIEN = 1, EMI transfer will be started by SPI DMA. PWM Operation Guide Configure EMICON1 register; Read data from FFT output buffer; Write data to PWMDAT register. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 100: Sd Card Host Controller (Sdc)

    12.1 Features 12 SD Card Host Controller (SDC) 12.1 Features The CW6632B SD card host controller can support SD/MMC card devices. SD memory Card Spec （Ver2.0）/ MMC Spec （Ver4.3） compatible;   CRC7 and CRC16 Generator;  Support Interrupt and DMA Data transfer mode;...
  • Page 101 1 = Clear pending DPCLR: Data interrupt pending clear bit 0 = Inactive 1 = Clear pending 8CKE: Send eight SD clocks after command or data 0 = Disable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 102 Update when the CRC status is receiving, so it is only valid after operation “write data” is done. 101 = Error transmission 010 = Non-erroneous transmission 111 = Flash error Register 12-4 SDBAUD – SD host baud rate Position Name SDBAUD Default CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 103: Sdc Operation Guide

    At this moment, if RCRCE (SDCFG2 [7]) is set to 1, the received response has CRC error. The previous command should be resent. Note: RCRCE bit is valid only when receiving R1 or R1b response. RCRCE bit can be ignored for other types of CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 104: 0 7 B D Ata Operation

    Wait for DPND (SDCFG1 [4]) to become „1‟ or wait for interrupt. Read DCRCE (SDCFG2 [6]) to determine if the data received has any error. Read the data received from IRAM. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 105: Audio Terminal (Dac)

    13 Audio Terminal (DAC) 13 Audio Terminal (DAC) 13.1 Features CW6632B provides a high performance stereo 16-bit resolution audio DAC:  Sample Rate 8 / 11.025 / 12 / 16 / 22.05 / 24 / 32 / 44.1 / 48KHz ...

  • Page 106: Function Of Dac Control Registers

    0 = Disabled 1 = Enabled OSSL: DAC over sample mode select 0 = Normal speed mode 1 = Double speed mode DACEN: DAC digital filter/delta-sigma modulator enable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 107 Register 13-6 DACVOLH – DAC volume setting high byte register Position Name DACVPND DACVOLH Default Access DACVPND: DAC volume adjust done pending Read “0”: not done CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 108 TRIMSPEED: DAC trim speed control 00 = trim 1 step every 1 sample 01 = trim 1 step every 2 samples 10 = trim 1 step every 3 samples CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 109 TRIMKST: DAC trimming kick start Write 1 to kick start DAC trimming Register 13-11 TRREGLL – DAC left channel trim data reg law byte Position Name TRIMREGLL Default Access TRIMREGLL: CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 110: Operation Guide

    Read: DAC real trimming data high byte 13.3 Operation Guide 13.3.1 BDAC Operation Guide Configure DACVOLL & DACVOLH Configure DACVCON Clear DACVPND to kick start adjust volume CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 111: Saradc

    14 SARADC 14 SARADC 14.1 Features CW6632B provides an 11-channel moderate conversion speed and a moderate resolution 10-bit successive approximated register Analog to Digital Converter (SARADC) for users to develop applications in the following areas:  Voice grade applications ...
  • Page 112 AUTOS: Auto channel switching mode 0 = Not switch 1 = Auto load ADCSEL_SH into ADCSEL after conversion finished Register 14-3 ADCBAUD– SARADC baud rate control CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 113 Register 14-4 ADCDATAL– SARADC Buffer low byte control Position Name ADCDATAL Default Access Register 14-5 ADCDATAH– SARADC Buffer high byte control Position Name ADCDATAH Default Access CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 114: Crc16 /Lfsr16/Lfsr32

    Write this location will initial CRC register. Note: To initial the CRC register, user need to write 2 bytes to CRCREG for CRC16 (High byte first). CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 115: Lfsr16

    Note: To initial the LFSR16 register, user need to write this register 2 times to LFSR16 register for LFSR16 (High byte first).Reading will output LFSR16 data0 Register 15-6 LFSR16_DAT1– LFSR16 data 1 Position Name LFSR16_DAT1 Default CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 116: Lfsr32

    Access Note: Reading will output LFSR32 data 2 Register 15-10 LFSR32_DAT3– LFSR32 data 3 Position Name LFSR32_DAT3 Default Access Note: Reading will output LFSR32 data 3 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 117: Integrated Interchip Sound (Iis)

    Register 16–1 IIS_CON0 Position Name DATA_FMT CH_SEL LTHWS SMP_EDGE SLAVE IIS_EN Default Access DATA_FMT: 00 = IIS format 01 = left align 10 = right align CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 118 01 = data source come by DMA(to or from memorys) 10 = data source come from internal DAC output 11 = data source come from IO and to IO;LOOP_OP; CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 119 1 = not clear WR_OV_PND:number of dma write is equal to (IIS_DMA_CNT0~1) R：0 = not finish 1 = finish W：0 = clear 1 = not clear CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 120 IIS_HF_RD_IE: IIS dma read half number of data interrupt enable 0 = disable 1 = enable IIS_HF_WR_IE: IIS dma write half number of data interrupt enable 0 = disable CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 121 IIS_ALLBIT：the bclk counts inside WS L or H user must configure this count,which is all bclks receive. During WS High or Low Register 16–8 IIS_VALBIT: Position Name IIS_VALBIT Default Access CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 122 IIS_REFCLK, the bit 5 of this register should be written 1; the Fiis_refclk = Fiis/( IIS_REFCLK_CFG[4:0]+1); Register 16–12 IIS_ADR0:DMA write addr Position Name IIS_ADR0 Default Access CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 123 For iis dma one time is two buffers, IIS_DMA_WR_CNT should be odd the real data bits is : ({IIS_DMA_WR_CNT1,IIS_DMA_WR_CNT0}+1) * 16 bits Register 16–16 IIS_DMA_RD_P_CNT0-1: Position Name IIS_DMA_RD_P_CNT CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 124: Operation Guide

    IIS support loop operation mode.that is send out data come from RX pin. And the tx data will delay 2-4 sample before really data come out.and the first 2-4 sample being send out is all 0s.must config OP_MOD=2‟b11; CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0...

  • Page 125: Dma Mode

    2.conf IIS_BAUD,IIS_BCLK_CFG,IIS_VALBIT,IIS_ALLBIT 3.conf IIS_CON0-1 4. conf IIS_DMA_RD_CNT and IIS_DMA_WR_CNT to kick start dma . 5.read DMA_CNT_PND which means 1 or 0.5 (IIS_DMA_CNT*16) bits data transmit had finished. CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 126: Polyfuse Control

    PF SCLK low pulse = 1 X system clock Note: This register can‟t set to zero Register 17–3 PFDAT Position Name PFDAT Default Access PFDAT: write this register will trigger access PF CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 127: Pf User Guideline

    3: read PFDAT for 8bit polyfuse data output steps 4: repeat 1, 2,3 for finish 64 bit polyfuse read steps 5: set rd_enc for protect polyfuse CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 128: Characteristics

    PUP2 KΩ Internal pull-down resister 0 PDN0 KΩ Internal pull-down resister 1 0.33 PDN1 KΩ Internal pull-down resister 2 PDN2 Level1 current driving For PORT1 LEVEL1 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 129: Audio Adda Parameters

    F=2 MHz Phase Noise Fc=2.4GHz -118 dBc/Hz F3 MHz -123 dBc/Hz XTAL Oscillator Frequency range Frequency Trimming Range 6 bits Table 18-7 Receive path Parameters CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 130 Available output power Side Band Suppression Low pass -3 dB BW Figure 2. TXVGA Gain Step Set paPWR[2:0] of GFSK Gain Range Control Register #16 DPSK CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 131: Package Outline Dimensions

    19 Package Outline Dimensions 19 Package Outline Dimensions 19.1 SSOP28 CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.
  • Page 132 19.1 SSOP28 Figure 19-1 SSOP28 Package Outline Dimension CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

  • Page 133: Revision History

    19 Package Outline Dimensions Revision History Date Version Comments Revised by 2015-8-28 0.0.1 Initial version 2015-8-28 0.0.2 Modify 2015-8-28 1.0.0 Released CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0 Copyright ©2015, www.appotech.com. All Rights Reserved.

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