Table of Contents
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VCC1.5V_U3_DDR
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
VCC1.5V_U3_DDR
VCC1.5V_U3_DDR
C-MVREFDQ
CLose to DDR3
CLose to Saturn7M IC
IC301
H5TQ1G63BFR-12C
FRC_DDR_1600
M8
N3
C-MVREFCA
VREFCA
A0
P7
A1
P3
A2
H1
N2
C-MVREFDQ
VREFDQ
A3
P8
A4
P2
R303
A5
L8
R8
ZQ
A6
R2
240
A7
1%
T8
A8
B2
R3
VDD_1
A9
D9
L7
VDD_2
A10/AP
G7
R7
VDD_3
A11
K2
N7
VDD_4
A12/BC
K8
T3
VDD_5
A13
N1
VDD_6
N9
M7
VDD_7
A15
R1
VDD_8
R9
M2
VCC1.5V_U3_DDR
VDD_9
BA0
C-MBA0
N8
C-MBA1
BA1
M3
BA2
C-MBA2
A1
VDDQ_1
A8
J 7
VDDQ_2
CK
C1
K7
VDDQ_3
CK
C9
K9
VDDQ_4
CKE
D2
VDDQ_5
E9
L2
VDDQ_6
CS
F1
K1
VDDQ_7
ODT
H2
J 3
VDDQ_8
RAS
H9
K3
VDDQ_9
CAS
L3
WE
J 1
NC_1
J 9
T2
NC_2
RESET
L1
NC_3
L9
NC_4
T7
F3
NC_6
DQSL
G3
DQSL
A9
C7
VSS_1
DQSU
B3
B7
VSS_2
DQSU
E1
VSS_3
G8
E7
VSS_4
DML
J 2
D3
VSS_5
DMU
J 8
VSS_6
M1
E3
VSS_7
DQL0
M9
F7
VSS_8
DQL1
P1
F2
VSS_9
DQL2
P9
F8
VSS_10
DQL3
T1
H3
VSS_11
DQL4
T9
H8
VSS_12
DQL5
G2
DQL6
H7
DQL7
B1
VSSQ_1
B9
D7
VSSQ_2
DQU0
D1
C3
VSSQ_3
DQU1
D8
C8
VSSQ_4
DQU2
E2
C2
VSSQ_5
DQU3
E8
A7
VSSQ_6
DQU4
F9
A2
VSSQ_7
DQU5
G1
B8
VSSQ_8
DQU6
G9
A3
VSSQ_9
DQU7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+1.5V_FRC_DDR
L301
C324
10uF
10V
C-MVREFCA
AR301
C-MA9
C-TMA9
C-MA2
C-TMA2
C-MA0
C-TMA0
C-MBA2
C-TMBA2
10
AR302
C-MA8
C-TMA8
C-MA6
C-TMA6
C-MA4
C-TMA4
C-MBA1
C-TMBA1
10
AR303
C-TMA10
C-MA10
C-MA12
C-TMA12
C-TMA1
C-MA1
C-MA0
C-MA11
C-TMA11
C-MA1
10
C-MA2
AR304
C-MA3
C-MA3
C-TMA3
C-MA4
C-MA5
C-TMA5
C-MA5
C-MA7
C-TMA7
C-MA6
C-MRESETB
C-TMRESETB
C-MA7
10
C-MA8
R307
C-MA9
C-MCK
C-TMCK
C-MA10
10
R308
C-MA11
C-MCKB
C-TMCKB
C-MA12
10
R309
C-MCKE
C-TMCKE
10
R310
C-TMRASB
C-MRASB
C-TMRESETB
10
AR305
C-MCASB
C-TMCASB
C-MCK
C-TMODT
C-MODT
C-TMDQSLB
C-MWEB
C-TMWEB
C-TMBA0
C-MCKB
C-MBA0
10
C-TMDQSUB
C-MCKE
R311
C-TMDQSL
C-MDQSL
C-MODT
10
R312
C-MRASB
C-MDQSLB
C-TMDQSLB
C-MCASB
10
VCC1.5V_U3_DDR
C-MWEB
R313
R333
10K
C-MDQSU
C-TMDQSU
10
C-MRESETB
R314
C-TMDQSUB
C-MDQSUB
10
R315
C-MDQSL
C-MDMU
C-TMDMU
C-MDQSLB
10
AR306
C-MDQSU
C-MDQL7
C-TMDQL7
C-MDQSUB
C-MDQL3
C-TMDQL3
C-MDQL1
C-TMDQL1
C-MDML
C-MDML
C-TMDML
C-MDMU
10
AR307
C-MDQL0
C-MDQL0
C-TMDQL0
C-MDQL1
C-MDQL2
C-TMDQL2
C-MDQL2
C-MDQL6
C-TMDQL6
C-MDQL3
C-MDQL4
C-TMDQL4
C-MDQL4
10
C-MDQL5
R316
C-MDQL6
C-MDQL5
C-TMDQL5
10
C-MDQL7
AR308
C-MDQU2
C-TMDQU2
C-MDQU0
C-MDQU6
C-TMDQU6
C-MDQU1
C-MDQU0
C-TMDQU0
C-MDQU2
C-MDQU4
C-TMDQU4
C-MDQU3
10
C-MDQU4
AR309
C-MDQU5
C-MDQU7
C-TMDQU7
C-MDQU6
C-MDQU1
C-TMDQU1
C-MDQU7
C-MDQU5
C-TMDQU5
C-MDQU3
C-TMDQU3
10
VCC1.5V_U3_DDR
C325
0 . 1 u F
16V
S7M_DIVX & MS10
IC101
LGE107D (S7M Divx_Non RM)
AE1
W26
C-TMA0
FRC_DDR3_A0/DDR2_NC
ACKP/RLV3P/RED[3]
AF16
W25
C-TMA1
FRC_DDR3_A1/DDR2_A6
ACKM/RLV3N/RED[2]
AF1
U26
C-TMA2
FRC_DDR3_A2/DDR2_A7
A0P/RLV0P/RED[9]
AE3
U25
C-TMA3
FRC_DDR3_A3/DDR2_A1
A0M/RLV0N/RED[8]
AD14
U24
C-TMA4
FRC_DDR3_A4/DDR2_CASZ
A1P/RLV1P/RED[7]
AD3
V26
C-TMA5
FRC_DDR3_A5/DDR2_A10
A1M/RLV1N/RED[6]
AF15
V25
C-TMA6
FRC_DDR3_A6/DDR2_A0
A2P/RLV2P/RED[5]
AF2
V24
C-TMA7
FRC_DDR3_A7/DDR2_A5
A2M/RLV2N/RED[4]
AE15
W24
C-TMA8
FRC_DDR3_A8/DDR2_A2
A3P/RLV4P/RED[1]
AD2
Y26
C-TMA9
FRC_DDR3_A9/DDR2_A9
A3M/RLV4N/RED[0]
AD16
Y25
C-TMA10
FRC_DDR3_A10/DDR2_A11
A4P/RLV5P/GREEN[9]
AD15
Y24
C-TMA11
FRC_DDR3_A11/DDR2_A4
A4M/RLV5N/GREEN[8]
AE16
C-TMA12
FRC_DDR3_A12/DDR2_A8
AC26
BCKP/TCON13/GREEN[1]
AC25
BCKM/TCON12/GREEN[0]
AA26
B0P/RLV6P/GREEN[7]
AF3
AA25
C-TMBA0
FRC_DDR3_BA0/DDR2_BA2
B0M/RLV6N/GREEN[6]
AF14
AA24
C-TMBA1
FRC_DDR3_BA1/DDR2_ODT
B1P/RLV7P/GREEN[5]
AD1
AB26
C-TMBA2
FRC_DDR3_BA2/DDR2_A12
B1M/RLV7N/GREEN[4]
AB25
B2P/RLV8P/GREEN[3]
AD13
AB24
C-TMCK
FRC_DDR3_MCLK/DDR2_MCLK
B2M/RLV8N/GREEN[2]
AE14
AC24
C-TMCKE
FRC_DDR3_CKE/DDR2_RASZ
B3P/TCON11/BLUE[9]
AE13
AD26
C-TMCKB
FRC_DDR3_MCLKZ/DDR2_MCLKZ
B3M/TCON10/BLUE[8]
AD25
B4P/TCON9/BLUE[7]
AD24
B4M/TCON8/BLUE[6]
AE4
C-TMODT
FRC_DDR3_ODT/DDR2_BA1
AD5
C-TMRASB
FRC_DDR3_RASZ/DDR2_WEZ
AF4
AD23
C-TMCASB
FRC_DDR3_CASZ/DDR2_CKE
CCKP/LLV3P
AD4
AE23
C-TMWEB
FRC_DDR3_WEZ/DDR2_BA0
CCKM/LLV3N
AE26
C0P/LLV0P/BLUE[5]
AE2
AE25
FRC_DDR3_RESETB/DDR2_A3
C0M/LLV0N/BLUE[4]
AF26
C1P/LLV1P/BLUE[3]
AF25
C1M/LLV1N/BLUE[2]
AF8
AE24
C-TMDQSL
FRC_DDR3_DQSL/DDR2_DQS0
C2P/LLV2P/BLUE[1]
AD9
AF24
FRC_DDR3_DQSLB/DDR2_DQSB0
C2M/LLV2N/BLUE[0]
AF23
C3P/LLV4P
AE9
AD22
C-TMDQSU
FRC_DDR3_DQSU/DDR2_DQS1
C3M/LLV4N
AF9
AE22
FRC_DDR3_DQSUB/DDR2_DQSB1
C4P/LLV5P
AF22
C4M/LLV5N
AE11
C-TMDML
FRC_DDR3_DML/DDR2_DQ7
AF6
C-TMDMU
FRC_DDR3_DMU/DDR2_DQ11
AD19
DCKP/TCON5
AE6
AE19
C-TMDQL0
FRC_DDR3_DQL0/DDR2_DQ6
DCKM/TCON4
AF11
AD21
C-TMDQL1
FRC_DDR3_DQL1/DDR2_DQ0
D0P/LLV6P
AD6
AE21
C-TMDQL2
FRC_DDR3_DQL2/DDR2_DQ1
D0M/LLV6N
AD12
AF21
C-TMDQL3
FRC_DDR3_DQL3/DDR2_DQ2
D1P/LLV7P
AE5
AD20
C-TMDQL4
FRC_DDR3_DQL4/DDR2_DQ4
D1M/LLV7N
AF12
AE20
C-TMDQL5
FRC_DDR3_DQL5/DDR2_NC
D2P/LLV8P
AF5
AF20
C-TMDQL6
FRC_DDR3_DQL6/DDR2_DQ3
D2M/LLV8N
AE12
AF19
C-TMDQL7
FRC_DDR3_DQL7/DDR2_DQ5
D3P/TCON3
AD18
D3M/TCON2
AE10
AE18
C-TMDQU0
FRC_DDR3_DQU0/DDR2_DQ8
D4P/TCON1
AF7
AF18
C-TMDQU1
FRC_DDR3_DQU1/DDR2_DQ14
D4M/TCON0
AD11
C-TMDQU2
FRC_DDR3_DQU2/DDR2_DQ13
AD7
C-TMDQU3
FRC_DDR3_DQU3/DDR2_DQ12
AD10
AB22
C-TMDQU4
FRC_DDR3_DQU4/DDR2_DQ15
GPIO0/TCON15/HSYNC/VDD_ODD
AE7
AB23
C-TMDQU5
FRC_DDR3_DQU5/DDR2_DQ9
GPIO1/TCON14/VSYNC/VDD_EVEN
AF10
AC23
C-TMDQU6
FRC_DDR3_DQU6/DDR2_DQ10
GPIO2/TCON7/LDE/GCLK4
AD8
AC22
C-TMDQU7
FRC_DDR3_DQU7/DDR2_DQM1
GPIO3/TCON6/LCK/GCLK2
AB16
FRC_GPIO0/UART_RX
AA14
FRC_GPIO1
AC15
R300
FRC_GPIO3
Y16
FRC_GPIO8
AC16
FRC_GPIO9/UART_TX
AE8
AC14
FRC_DDR3_NC/DDR2_DQM0
FRC_GPIO10
R317
820
Y11
AA16
FRC_REXT
FRC_I2CM_DA
Y19
AA15
FRC_TESTPIN
FRC_I2CM_CK
Y10
FRC_I2CS_DA
AA11
FRC_I2CS_CK
AB15
FRC_PWM0
AB14
FRC_PWM1
R332
IC301-*1
H5TQ1G63BFR-H9C
FRC_DDR_1333_HYNIX
N3
M8
A0
VREFCA
P7
A1
P3
A2
N2
H1
A3
VREFDQ
P8
A4
P2
A5
R8
L8
A6
ZQ
R2
A7
T8
A8
R3
B2
A9
VDD_1
L7
D9
A10/AP
VDD_2
R7
G7
A11
VDD_3
N7
K2
A12/BC
VDD_4
T3
K8
A13
VDD_5
N1
VDD_6
M7
N9
A15
VDD_7
R1
VDD_8
M2
R9
BA0
VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J 7
A8
CK
VDDQ_2
K7
C1
CK
VDDQ_3
K9
C9
CKE
VDDQ_4
D2
VDDQ_5
L2
E9
CS
VDDQ_6
K1
F1
ODT
VDDQ_7
J 3
H2
RAS
VDDQ_8
K3
H9
CAS
VDDQ_9
L3
RXBCK+
WE
J 1
NC_1
RXBCK-
T2
J 9
RXB0+
RESET
NC_2
L1
NC_3
RXB0-
L9
NC_4
RXB1+
F3
T7
DQSL
NC_6
RXB1-
G3
DQSL
RXB2+
RXB2-
C7
A9
DQSU
VSS_1
RXB3+
B7
B3
DQSU
VSS_2
RXB3-
E1
VSS_3
RXB4+
E7
G8
DML
VSS_4
RXB4-
D3
J 2
DMU
VSS_5
J 8
VSS_6
E3
M1
DQL0
VSS_7
RXACK+
F7
M9
DQL1
VSS_8
RXACK-
F2
P1
DQL2
VSS_9
RXA0+
F8
P9
RXA0-
DQL3
VSS_10
H3
T1
DQL4
VSS_11
RXA1+
H8
T9
RXA1-
DQL5
VSS_12
G2
DQL6
RXA2+
H7
RXA2-
DQL7
B1
VSSQ_1
RXA3+
D7
B9
RXA3-
DQU0
VSSQ_2
C3
D1
DQU1
VSSQ_3
RXA4+
C8
D8
RXA4-
DQU2
VSSQ_4
C2
E2
DQU3
VSSQ_5
A7
E8
DQU4
VSSQ_6
A2
F9
DQU5
VSSQ_7
RXCCK+
B8
G1
DQU6
VSSQ_8
RXCCK-
A3
G9
DQU7
VSSQ_9
RXC0+
RXC0-
RXC1+
RXC1-
RXC2+
RXC2-
RXC3+
RXC3-
RXC4+
RXC4-
RXDCK+
RXDCK-
RXD0+
RXD0-
<U3 CHIP Config>
RXD1+
(FRC_CONF0)
RXD1-
RXD2+
HIGH : I2C ADR = B8
RXD2-
LOW : I2C ADR = B4
RXD3+
(FRC_CONF1,FRC_PWM1, FRC_PWM0)
RXD3-
RXD4+
3 ' d 5 : b o o t f r o m i n t e r n a l S R A M
3 ' d 6 : b o o t f r o m E E P R O M
RXD4-
3 ' d 7 : b o o t f o r m S P I f l a s h
GVDD_ODD
+3.3V_Normal
GVDD_EVEN
GCLK4
GCLK2
UART_FRC_RX
R336
0
DPM_A
FRC_CONF0
MINI_LVDS
0
OPT
FRC_CONF1
UART_FRC_TX
TP301
OPT
R334
22
0
R327
FRC_SDA
R335
22
R328
FRC_SCL
OPT
0
TP302
R326
22
FRC
I2C_SDA
R331
22
FRC
I2C_SCL
FRC_PWM0
FRC_PWM1
V_SYNC
0
IC301-*2
IC301-*3
K4B1G1646E-HCH9000
NT5CB64M16AP-CG
FRC_DDR_1333_SS
FRC_DDR_1333_NY
N3
M8
N3
M8
A0
VREFCA
A0
VREFCA
P7
P7
A1
A1
P3
P3
A2
A2
N2
H1
N2
H1
A3
VREFDQ
A3
VREFDQ
P8
P8
A4
A4
P2
P2
A5
A5
R8
L8
R8
L8
A6
ZQ
A6
ZQ
R2
R2
A7
A7
T8
T8
A8
A8
R3
B2
R3
B2
A9
VDD_1
A9
VDD_1
L7
D9
L7
D9
A10/AP
VDD_2
A10/AP
VDD_2
R7
G7
R7
G7
A11
VDD_3
A11
VDD_3
N7
K2
N7
K2
A12/BC
VDD_4
A12
VDD_4
T3
K8
T3
K8
A13
VDD_5
NC_6
VDD_5
N1
N1
VDD_6
VDD_6
M7
N9
M7
N9
NC_5
VDD_7
NC_5
VDD_7
R1
R1
VDD_8
VDD_8
M2
R9
M2
R9
BA0
VDD_9
BA0
VDD_9
N8
N8
BA1
BA1
M3
M3
BA2
BA2
A1
A1
VDDQ_1
VDDQ_1
J 7
A8
J 7
A8
CK
VDDQ_2
CK
VDDQ_2
K7
C1
K7
C1
CK
VDDQ_3
CK
VDDQ_3
K9
C9
K9
C9
CKE
CKE
VDDQ_4
VDDQ_4
D2
D2
VDDQ_5
VDDQ_5
L2
E9
L2
E9
CS
VDDQ_6
CS
VDDQ_6
K1
F1
K1
F1
ODT
VDDQ_7
ODT
VDDQ_7
J 3
H2
J 3
H2
RAS
VDDQ_8
RAS
VDDQ_8
K3
H9
K3
H9
CAS
VDDQ_9
CAS
VDDQ_9
L3
L3
WE
WE
J 1
J 1
NC_1
NC_1
T2
J 9
T2
J 9
RESET
NC_2
RESET
NC_2
L1
L1
NC_3
NC_3
L9
L9
NC_4
NC_4
F3
T7
F3
T7
DQSL
NC_6
DQSL
NC_7
G3
G3
DQSL
DQSL
C7
A9
C7
A9
DQSU
VSS_1
DQSU
VSS_1
B7
B3
B7
B3
DQSU
VSS_2
DQSU
VSS_2
E1
E1
VSS_3
VSS_3
E7
G8
E7
G8
DML
VSS_4
DML
VSS_4
D3
J 2
D3
J 2
DMU
VSS_5
DMU
VSS_5
J 8
J 8
VSS_6
VSS_6
E3
M1
E3
M1
DQL0
VSS_7
DQL0
VSS_7
F7
M9
F7
M9
DQL1
VSS_8
DQL1
VSS_8
F2
P1
F2
P1
DQL2
VSS_9
DQL2
VSS_9
F8
P9
F8
P9
DQL3
VSS_10
DQL3
VSS_10
H3
T1
H3
T1
DQL4
VSS_11
DQL4
VSS_11
H8
T9
H8
T9
DQL5
VSS_12
DQL5
VSS_12
G2
G2
DQL6
DQL6
H7
H7
DQL7
DQL7
B1
B1
VSSQ_1
VSSQ_1
D7
B9
D7
B9
DQU0
VSSQ_2
DQU0
VSSQ_2
C3
D1
C3
D1
DQU1
VSSQ_3
DQU1
VSSQ_3
C8
D8
C8
D8
DQU2
VSSQ_4
DQU2
VSSQ_4
C2
E2
C2
E2
DQU3
VSSQ_5
DQU3
VSSQ_5
A7
E8
A7
E8
DQU4
VSSQ_6
DQU4
VSSQ_6
A2
F9
A2
F9
DQU5
VSSQ_7
DQU5
VSSQ_7
B8
G1
B8
G1
DQU6
VSSQ_8
DQU6
VSSQ_8
A3
G9
A3
G9
DQU7
VSSQ_9
DQU7
VSSQ_9
FRC_CONF0
FRC_CONF1
FRC_PWM1
FRC_PWM0
GP2_Saturn7M
V e r . 1 . 4
DDR3(FRC)
3
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