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Features
■
Combination real-time clock with audio
– Serial RTC based on M41T00
– Audio section provides:
–
300mW differential audio amplifier
–
256 and 512Hz tone generation
–
-33 to +12dB gain, 3dB steps (16 steps
plus MUTE)
■
Real-time clock details:
– Superset of M41T00
– 3.0 to 3.6V operation
–
Timekeeping down to 1.7V
– Automatic backup switchover circuit
–
Ultra low 400nA backup current at 3.0V
(typ)
–
Suitable for battery or capacitor backup
–
On-chip trickle charge circuit for backup
capacitor
2
– 400kHz I
C bus
– M41T00 compatible register set with
counters for seconds, minutes, hours, day,
date, month, years, and century
–
Automatic leap year compensation
–
HT bit set when clock goes into backup
mode
– RTC operates using 32,768Hz quartz
crystal
–
Calibration register provides for
adjustments of -63 to +126ppm
–
Oscillator supports crystals with up to
40kΩ series resistance, 12.5pF load
capacitance
– Oscillator fail detect circuit OF bit indicates
when oscillator has stopped for four or
more cycles
December 2007
Serial real-time clock with audio
DFN16 (5mm x 4mm)
■
Audio section
– Power amplifier
–
Differential output amplifier
–
Provides 300mW into 8Ω (THD+N = 2%
(max), f
– Summing node at audio input
–
Inverting configuration with summing
resistors into the minus (-) terminal
–
0dB gain with 10kΩ feedback resistor
and 20kΩ input summing resistors
–
Signal input centered at V
–
1.6V
P-P
– 256 or 512 Hz signal multiplexing with
analog input to provide audio with beep
tones
– Volume control, 4-bit register
–
Allows gain adjustment from -33dB to
+12dB
–
3dB steps
–
MUTE bit
– Audio automatically shuts off in backup
mode
■
0°C to 70°C operation
■
Small DFN16 package (5mm x 4mm)
Rev 2
M41T00AUD
"D" Suffix
= 1kHz)
in
/2
DD
analog input range (max)
1/44
www.st.com
1
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Table of Contents
Summary of Contents for ST M41T00AUD
- Page 1 M41T00AUD Serial real-time clock with audio Features ■ Combination real-time clock with audio – Serial RTC based on M41T00 – Audio section provides: – 300mW differential audio amplifier – 256 and 512Hz tone generation – -33 to +12dB gain, 3dB steps (16 steps...
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Page 2: Table Of Contents
Data retention mode ......... 15 M41T00AUD clock operation ....... . . 16 Clock registers . - Page 3 M41T00AUD Contents Initial conditions ......... . . 33 Maximum ratings .
- Page 4 M41T00AUD register map ........
- Page 5 M41T00AUD List of figures List of figures Figure 1. Logic diagram ............6 Figure 2.
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Page 6: Description
M41T00AUD Description The M41T00AUD is a low power serial real-time clock (RTC) with an integral audio section with tone generator and 300mW output amplifier. The RTC is a superset of the M41T00 with enhancements such as a precision reference for switchover, an oscillator fail detect circuit and storing of the time at power down. -
Page 7: Pin Settings
M41T00AUD Pin settings Pin settings Pin connection Figure 2. Pin connection OSCI AOUT– V CC OSCO V SS V SS V CC AOUT+ IRQ/FT/OUT V BACK V BIAS ai13323 Pin description Table 1. Pin description Symbol Name and function Supply voltage... -
Page 8: Application
Application M41T00AUD Application Figure 3. Application diagram M41T00AUD V CC V BACK V CC TRICKLE CHARGE AUTOMATIC V CC BATTERY V INT SECS SWITCHOVER MINS & DESELEC T HOURS DATE REFERENCE V PFD =2.80V MONTH I 2 C WRITE YEAR... -
Page 9: Figure 4. Typical Hookup Example
M41T00AUD Application Figure 4. Typical hookup example 3.3V Place near Place near pin 4 pin 15 0.1μF 1.0μF Either/or, but not both M41T00AUD V BACK TRICKLE 3.3V 3.3V CHARGE Lithium BATTERY Cell V INT SWITCHOVER Battery (alternative) 3.3V SCL 7 4.7kΩ... -
Page 10: Operation
M41T00AUD Operation The M41T00AUD clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 10 bytes contained in the device can then be accessed sequentially in the following order: Table 2. -
Page 11: 2-Wire Bus Characteristics
M41T00AUD Operation 2-wire bus characteristics This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. -
Page 12: Figure 5. Serial Bus Data Transfer Sequence
Operation M41T00AUD Figure 5. Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK DATA START CHANGE OF STOP CONDITION DATA ALLOWED CONDITION AI00587 Figure 6. Acknowledgement sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER... -
Page 13: Characteristics
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL. READ mode In this mode, the master reads the M41T00AUD slave after setting the slave address (see Figure 8). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the word (register) address An is written to the on-chip address pointer. -
Page 14: Figure 8. Slave Address Location
Operation M41T00AUD Figure 8. Slave address location START SLAVE ADDRESS AI00602 Figure 9. READ mode sequence BUS ACTIVITY: MASTER WORD SDA LINE DATA n DATA n+1 ADDRESS (An) BUS ACTIVITY: SLAVE SLAVE ADDRESS ADDRESS DATA n+X AI00899 Figure 10. Alternate READ mode sequence... -
Page 15: Write Mode
The M41T00AUD slave receiver will send an acknowledge clock to the master transmitter after it has received the... -
Page 16: M41T00Aud Clock Operation
Setting the ST bit to a 1 will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain on the backup battery. -
Page 17: Halt Bit Operation
M41T00AUD M41T00AUD clock operation Register 08 is the calibration register. Calibration is described in detail in the Clock calibration section. Bit D7 is the OUT bit and controls the discrete output pin IRQ/FT/OUT as described in Table 5.1.1 Halt bit operation Bit D7 of register 09 h is the HT or halt bit. -
Page 18: Reading And Writing The Clock Registers
M41T00AUD clock operation M41T00AUD Reading and writing the clock registers The counters used to implement the timing chain in the real-time clock are not directly accessed by the serial interface. Instead, as depicted in Figure 12, reads and writes are buffered through a set of transfer registers. -
Page 19: Table 4. M41T00Aud Register Map
M41T00AUD M41T00AUD clock operation Table 4. M41T00AUD register map Register name Range Addr 10 seconds Seconds Seconds 00-59 10 minutes Minutes Minutes 00-59 10 hours Hours (24 hour format) Century/hours 0-1/00-23 Day of week 10 date Date: day of month... -
Page 20: Figure 12. Counter Update Diagram
M41T00AUD clock operation M41T00AUD Figure 12. Counter update diagram 32KHz READ/WRITE BUFFER DIVIDE BY 32768 TRANSFER REGISTERS 1 Hz SECONDS COUNTER REGISTER MINUTES COUNTER REGISTER HOURS REGISTER COUNTER SERIAL 1 2 C SERIAL BUS TRANSFER REGISTER REGISTER COUNTER DATE MONTHS... -
Page 21: Priority For Irq/Ft/Out Pin
M41T00AUD clock operation Priority for IRQ/FT/OUT pin Three functions share pin 5 of the M41T00AUD. The oscillator fail interrupt (IRQ), the calibration frequency test output (FT) and the discrete logic output (OUT) all use this pin. In normal operation, when operating from V , the interrupt function has priority over the frequency test function which in turn has priority over the discrete output function. -
Page 22: Switchover Thresholds
M41T00AUD clock operation M41T00AUD Switchover thresholds While the M41T00AUD includes a precision reference for the backup switchover threshold, it is not a fixed value, but depends on the backup voltage, V . The device will always BACK switchover at the lesser of the reference voltage (V , approximately 2.8V) and V... -
Page 23: Trickle Charge Circuit
M41T00AUD M41T00AUD clock operation Trickle charge circuit The M41T00AUD includes a trickle charge circuit to be used with a backup capacitor. It is illustrated in Table 14. V is a bi-directional pin. Its primary function is as the backup BACK supply input. -
Page 24: Clock Calibration
The M41T00AUD oscillator is designed for use with a 12.5pF crystal load capacitance. With a nominal ±20 ppm crystal, the M41T00AUD will be accurate to ±35 ppm. When the calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C. - Page 25 M41T00AUD Clock calibration Example 2: Sign is 0 and N is 3 (00010b). The 16-minute interval will be: 3 * 513 + (60-3) * 512 + 15 * 60 * 512 = 491523 cycles long out of a possible 512 * 60 * 16 = 491520 cycles of the 512Hz clock in an 16-minute span.
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Page 26: Table 6. Digital Calibration Values
Clock calibration M41T00AUD Table 6. Digital calibration values Calibration value Calibration result, in ppm, rounded to the nearest integer DC4-DC0 Slowing Speeding Decimal Binary sign DCS = 0 sign DCS = 1 00000 + 0 ppm – 0 ppm 00001 + 2 ppm –... -
Page 27: Figure 15. Crystal Accuracy Across Temperature
M41T00AUD Clock calibration Figure 15. Crystal accuracy across temperature Frequency (ppm) –20 –40 –60 –80 DF = K x (T –T –100 K = –0.036 ppm/˚C 2 ± 0.006 ppm/˚C 2 –120 T O = 25˚C ± 5˚C –140 –160 –40... -
Page 28: Audio Section Operation
Audio section operation M41T00AUD Audio section operation The audio section is comprised of five main parts. The input includes a summing amplifier. A minimum 10kΩ feedback resistor is required. With that and 20kΩ input resistors, the input signals will be summed at unity gain. -
Page 29: Figure 16. Audio Section Diagram
M41T00AUD Audio section operation Figure 16. Audio section diagram 0.1μF 29/44... -
Page 30: Table 7. Mute And Gain Values (Vcc = 3.3V And Ambient Temperature = 25°C)
Audio section operation M41T00AUD Table 7. MUTE and GAIN values (V = 3.3V and ambient temperature = 25°C) MUTE GAIN Audio gain (dB) . scalar gain Binary XXXX 1111 1110 1101 1100 1011 1010 0.708 1001 1000 0.355 0111 0.251 0110 0.178... -
Page 31: Gain
The final section is the output driver. It has a differential output capable of driving 300mW into an 8Ω load. The overall gain of the M41T00AUD is defined as the ratio of the AC output voltage, A and the AC input voltage, S... -
Page 32: Wake-Up Time: Twu
Audio section operation M41T00AUD The other parameter pertains to the gain step size, a relative measurement. It is shown in Table 16 as 3±1dB. For any gain setting in Table 7, the next higher (or lower) setting is guaranteed to be between 2 and 4 dB higher (or lower). For example, even though no upper and lower limits are shown for GAIN = Ch, it is tested to be at 3±1dB of the case when... -
Page 33: Initial Conditions
ST, the stop bit, is a 0 at first power up thus enabling the oscillator to run without need of user intervention. On subsequent power ups, it is not altered by the device and remains at the last value programmed by the user. -
Page 34: Maximum Ratings
Maximum ratings M41T00AUD Maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. -
Page 35: Dc And Ac Parameters
M41T00AUD DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. -
Page 36: Table 12. Dc Characteristics
2. Load capacitors are integrated within the M41T00AUD. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. -
Page 37: Table 14. Rtc Power Down/Up Ac Characteristics
M41T00AUD DC and AC parameters Figure 18. Power down/up mode AC waveforms V CC V SO tREC DON'T CARE AI00596 Table 14. RTC power down/up AC characteristics (1)(2) Symbol Unit Parameter SCL and SDA at VIH before power down SCL and SDA at VIH after power up µs... -
Page 38: Table 16. Audio Section Electrical Characteristics, Valid For
DC and AC parameters M41T00AUD Table 16. Audio section electrical characteristics, valid for V = 3.3V and = 25°C (except where otherwise noted) Symbol Parameter Condition Unit No input signal, Output offset voltage Ω RL = 8 THD = 2% Max, f = 1kHz,... -
Page 39: Package Mechanical Data
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com... -
Page 40: Figure 19. Dfn16 (5Mm X 4Mm) Package Outline
Package mechanical data M41T00AUD Figure 19. DFN16 (5mm x 4mm) package outline SEATING PLANE SIDE VIEW PIN 1 BTM VIEW DFN16_ME 1. Drawing is not to scale. 40/44... -
Page 41: Table 17. Dfn16 (5Mm X 4Mm) Package Mechanical Data
M41T00AUD Package mechanical data Table 17. DFN16 (5mm x 4mm) package mechanical data inches 0.80 0.90 1.00 0.032 0.035 0.040 0.00 0.02 0.05 0.00 0.0007 0.002 0.20 0.008 0.20 0.25 0.30 0.008 0.010 0.012 5.00 0.197 4.00 0.157 4.20 4.35 4.45... -
Page 42: Part Numbering
Part numbering M41T00AUD Part numbering Table 18. Ordering information scheme Example: M41T00AUD Device type M41T00AUD Package D = Lead-free 5mm x 4mm DFN Temperature range 1 = 0°C to 70°C Shipping method ® E = ECOPACK lead-free ICs in tube ®... -
Page 43: Revision History
M41T00AUD Revision history Revision history Table 19. Document revision history Date Revision Changes 01-May-2007 Initial release. 13-Dec-2007 Minor text changes; updated footnote 1 in Table 43/44... - Page 44 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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