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IDT Tsi310TM User Manual

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User Manual

80B6020_MA001_05
September 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.

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Summary of Contents for IDT Tsi310TM

  • Page 1: User Manual

    ® Tsi310 PCI-X Bridge ™ ® User Manual 80B6020_MA001_05 September 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Contents About this Document........... . 13 Revision History .
  • Page 4 Contents 2.3.4 Non-Prefetchable and DWord Reads........35 2.3.5 Prefetchable Reads .
  • Page 5 Contents Register Summary ............68 PCI Configuration Space Header Registers .
  • Page 6 Contents 5.5.2 Secondary Data Buffering Control Register ....... . 108 5.5.3 Miscellaneous Control Register .
  • Page 7 Contents 6.6.1 Filter Requirements for P_VDDA and S_VDDA......161 Pinout ..............163 6.7.1 Pinout —...
  • Page 8 Contents Tsi310 User Manual 80B6020_MA001_05...
  • Page 9 List of Figures Figure 1: Block Diagram ............. . . 20 Figure 2: Configuration Transaction Address Formats .
  • Page 10 List of Figures Tsi310 User Manual 80B6020_MA001_05...
  • Page 11 List of Tables Table 1: PCI Transactions ............. . 28 Table 2: PCI-X Transactions .
  • Page 12 List of Tables Tsi310 User Manual 80B6020_MA001_05...

  • Page 13: About This Document

    “Related Information” on page 17 Revision History 80B6020_MA001_05, Formal, September 2009 This version of the document was rebranded as IDT. It does not include any technical changes. 80B6020_MA001_04, Formal, December 2004 This document was updated to address the following changes: •...

  • Page 14: Document Conventions

    80B6020_MA001_01, Formal, February 2004 This document supports the Tsi310 (part numbers Tsi310A-133CE and Tsi310-133CE). For information about the differences between these devices, see the Tsi310 Differences Document. This document differs from the 80B6000_MA001_03 user manual in the following ways: • Updated the Revision ID number (see Section 5.4.5 on page •...
  • Page 15 Bit Ordering Notation When referring to PCI-X transactions, this document assumes the most significant bit is the largest number (also known as little-endian bit ordering). For example, the PCI address/data bus consists of AD[31:0], where AD[31] is the most significant bit and AD[0] is the least-significant bit of the field (see the following graphic).
  • Page 16 Units of Measure The following units of measure are used in this manual: • Prefixes: K=1024, k=1000 • Bits and bytes: An uppercase “B” stands for bytes. For example, 1 KB means 1024 bytes. • A lowercase “b” refers to bits. For example, 1 Kb means 1024 bits. Symbols Used The following symbols are used in this manual: This symbol indicates important configuration information or suggestions.

  • Page 17: Related Information

    Related Information The following information is useful for reference purposes when using this manual: PCI Local Bus Specification This document defines the PCI hardware system including (Revision 2.2) the protocol, electrical, mechanical and configuration specification for the PCI local bus components and expansion boards.
  • Page 18 Tsi310 User Manual 80B6020_MA001_05...

  • Page 19: Functional Overview

    Functional Overview  This chapter describes the main features and functions of the Tsi310 . The following topics are discussed: • “Overview of the Tsi310” on page 19 • “Features” on page 22 • “Technology Highlights” on page 26 • “Operation Overview”...

  • Page 20: Figure 1: Block Diagram

    1. Functional Overview Figure 1: Block Diagram Secondary Primary Configuration Registers Clock PLL Clock PLL Data/Control Unit PCI-X PCI-X Interface Interface Burst Read Posted Write Single Data Buffer Buffer Phase Buffer 4 Kbytes 1 Kbyte 4 Bytes Read Queue PW Queue Slave Master 8 entries...
  • Page 21 1. Functional Overview • Two data/control units, one for downstream transactions and one for upstream transactions. These symmetric units each contain separate buffers for burst read, posted write, and single data phase operations. Read and write queues, queue compare logic, address decoding, control logic, and other control functions are also included in these blocks.

  • Page 22: Features

    1. Functional Overview Features The Tsi310 has the following key features: 1.2.1 PCI-X Interfaces • Complies with the following specifications: — PCI Local Bus Specification (Revision 2.2) — PCI-to-PCI Bridge Architecture Specification (Revision 2.0) — PCI-X Addendum to PCI Local Bus Specification (Revision 1.0a) •...

  • Page 23: Transaction Forwarding

    1. Functional Overview 1.2.4 Transaction Forwarding • I/O, Memory, and Prefetchable Memory base and limit registers for downstream forwarding • Inverse address decoding for upstream forwarding • Flat addressing model • Supports VGA-compatible addressing and palette snooping for upstream transactions •...

  • Page 24: Operation Overview

    1. Functional Overview Operation Overview This section briefly describes the operation of various aspects of the Tsi310. For more information on each topic, refer to subsequent chapters. 1.3.1 Supported Modes The Tsi310 is a full-function transparent PCI-X to PCI-X bridge. As such, either interface may be configured to operate using the conventional PCI bus protocol or the PCI-X bus protocol.

  • Page 25: Address Decoding

    1. Functional Overview Every 512-byte buffer is further divided into four 128-byte subsections. Activity generally occurs on these 128-byte boundaries. Filling and/or emptying 128 bytes causes bus transactions to be initiated. While each read queue entry has up to 512 bytes of buffer space associated with it, to keep data flowing efficiently the 128-byte subsections are re-used as needed when they are emptied.

  • Page 26: Bus Arbitration

    1. Functional Overview 1.3.4 Bus Arbitration The Tsi310 contains an arbiter for the secondary interface that is enabled or disabled through an input signal pin. It provides bus arbitration for up to six additional masters, each of which may be assigned high or low priority or may be masked off. When the internal arbiter is used and the Tsi310 request is not masked off, the bus is parked at the bridge whenever there are no pending requests.

  • Page 27: Bus Operation

    Bus Operation This chapter discusses the following topics: • “Overview of Bus Operation” on page 27 • “Write Transactions” on page 30 • “Read Transactions” on page 33 • “Configuration Transactions” on page 37 Overview of Bus Operation This chapter presents a summary of the PCI and PCI-X transactions, transaction forwarding across the Tsi310, and transaction termination.

  • Page 28: Types Of Transactions

    2. Bus Operation 2.1.1 Types of Transactions Tables 1 list the command code and name for each PCI and PCI-X transaction. For each transaction type, the middle two columns indicate whether the Tsi310 can initiate the transaction as a master on the primary bus and on the secondary bus. The last two columns indicate whether the bridge responds to the transaction as a target on the primary bus and on the secondary bus.

  • Page 29: Table 2: Pci-X Transactions

    2. Bus Operation Table 2: PCI-X Transactions Initiates as Master Responds as Target Command Code Type of Transaction Primary Secondary Primary Secondary 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000...

  • Page 30: Write Transactions

    2. Bus Operation • The Tsi310 does not generate Type 0 configuration transactions on the primary interface. • The Tsi310 never initiates a Memory Write and Invalidate command on either interface. As a target, the bridge will accept a Memory Write and Invalidate command and forward it to the destination interface as a Memory Write command.
  • Page 31 2. Bus Operation 2.2.1.1 PCI to PCI-X Transactions When the originating bus is operating in the conventional PCI mode and the destination bus is operating in PCI-X mode, the Tsi310 must buffer memory write transactions from the conventional PCI interface and count the number of bytes to be forwarded to the PCI-X interface.

  • Page 32: Delayed/Split Write Transactions

    2. Bus Operation 2.2.1.4 PCI-X to PCI-X Transactions When both buses are operating in PCI-X mode, the Tsi310 passes the memory write command that it receives to the destination interface along with the originating byte count and transaction The Tsi310 attempts to transfer a memory write command when the transaction ends or a 128-byte boundary is crossed, whichever comes first.

  • Page 33: Read Transactions

    2. Bus Operation Read Transactions Read transactions are treated as either delayed (PCI), split (PCI-X), or immediate read transactions, as shown in the following table. Table 4: Read Transaction Handling Type of Transaction Type of Handling Memory Read Delayed Memory Read Line Delayed Memory Read Multiple Delayed...
  • Page 34 2. Bus Operation The Tsi310 must translate the conventional memory read multiple command to the memory read block PCI-X command. The prefetching algorithm is controlled by bits 5:4 of the primary and secondary data buffering control registers. The default value of these bits indicates that a full prefetch will be done, subject to the limit imposed by the maximum memory read byte count value set by bits (14:12) of the same register.

  • Page 35: I/O Read

    2. Bus Operation For the memory read multiple command, the prefetching algorithm is controlled by bits 5:4 of the primary and secondary data buffering control registers. The default value of these bits indicates that a full prefetch will be done, subject to the limit imposed by the maximum memory read byte count value set by bits (14:12) of the same register.

  • Page 36: Prefetchable Reads

    2. Bus Operation 2.3.5 Prefetchable Reads A prefetchable read transaction is a read transaction where the Tsi310 performs speculative reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. For prefetchable read transactions, all byte enables are asserted for all data phases.

  • Page 37: Configuration Transactions

    2. Bus Operation 2.3.5.3 Algorithm for PCI-X-to-PCI and PCI-X-to-PCI-X Mode The algorithm for transfers in these modes is to transfer the amount of requested data. In the PCI-X-to-PCI mode, the Tsi310 continues to generate data requests to the PCI interface and keeps the prefetch buffer full until the entire amount of data requested is transferred.

  • Page 38: Configuration Type 0 Access To Bridge

    2. Bus Operation Figure 2: Configuration Transaction Address Formats AD(31:0) 11 10 Function Reserved Bus Number Device Number Register Number Number PCI Type 1 11 10 Function See PCI 2.2 Specification and table below Register Number Number AD(31:0) PCI Type 0 AD(31:0) 11 10 Function...
  • Page 39 If a user needs to access the Tsi310 from the Secondary interface after reset (for example, to set up Opaque regions), IDT recommends completing a configuration read of offset 0x84 to determine the Tsi310's device number assigned upon initial configuration.

  • Page 40: Type 1 To Type 0 Translation By Bridge

    2. Bus Operation 2.4.2 Type 1 to Type 0 Translation by Bridge Type 1 configuration transactions are used to configure devices in a hierarchical bus structure having one or more bridges. A bridge is the only type of device that should respond to a Type 1 configuration transaction.

  • Page 41: Table 5: Idsel Generation

    2. Bus Operation Table 5: IDSEL Generation Primary Address Device Number P_AD(15:11) Secondary Address S_AD(31:16) x’00’ 00000 0000 0000 0000 0001 x’01’ 00001 0000 0000 0000 0010 x’02’ 00010 0000 0000 0000 0100 x’03’ 00011 0000 0000 0000 1000 x’04’ 00100 0000 0000 0001 0000 x’05’...

  • Page 42: Type 1 To Type 1 Forwarding By Bridge

    2. Bus Operation 2.4.3 Type 1 to Type 1 Forwarding by Bridge Type 1 to Type 1 transaction forwarding provides a means to configure devices when a hierarchical bus structure containing two or more levels of bridges is used. When the Tsi310 accepts a Type 1 configuration transaction destined for a PCI/PCI-X bus downstream from its secondary interface, the bridge forwards the transaction unchanged to the secondary bus.
  • Page 43 2. Bus Operation When the Tsi310 initiates the transaction on the destination interface, the command is changed from a configuration write to a special cycle. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction in PCI mode and as a split transaction in PCI-X mode.
  • Page 44 2. Bus Operation Tsi310 User Manual 80B6020_MA001_05...

  • Page 45: Clocking And Reset Options

    Clocking and Reset Options This chapter discusses the following topics: • “Clocking Domains” on page 45 • “Clock Jitter” on page 46 • “Mode and Clock Frequency Determination” on page 46 • “Clock Stability” on page 48 • “Driver Impedance Selection” on page 49 •...

  • Page 46: Clock Jitter

    3. Clocking and Reset Options Clock Jitter Clock jitter is defined as the relationship of one clock edge to a subsequent clock edge, measured at the same point. If these two edges are separated by one clock cycle, it is called cycle-to-cycle or short-term jitter.

  • Page 47: Secondary Interface

    3. Clocking and Reset Options The Tsi310 does not have I/O pins for the M66EN or PCIXCAP signals on its primary interface. The bridge adjusts its internal configuration (including its internal PLLs, if appropriate) solely on the basis of the initialization pattern it detects on the signals P_DEVSEL#, P_STOP#, and P_TRDY# at the rising edge of P_RST#.

  • Page 48: Clock Stability

    3. Clocking and Reset Options Figure 3: Programmable Pull-up Circuit 3.3V Tsi310 Weak 56k Pull-up S_PCIXCAP Strong 1k Pull-up 3.3V 10k 0.01uF 0.01uF 0.01uF S_PCIXCAP_PU Enabled During Bus Capability Determination 3.3V For PCI-X For PCI For PCI-X 66 MHz Cards Cards 100/133 MHz Cards 10k...

  • Page 49: Driver Impedance Selection

    3. Clocking and Reset Options The Tsi310 is expecting at most one transition on the S_CLK_STABLE input from the not stable to the stable state. The S_CLK_STABLE input may also be tied-up if the secondary clock input will always be stable prior to the de-assertion of the primary bus reset signal or the secondary bus reset bit of the bridge control register (see Section 3.6.2 on page 51).There are...

  • Page 50: Reset Functions And Operations

    3. Clocking and Reset Options There may be some applications for which these assumptions are inaccurate. For example, a conventional PCI device may be connected in a point-to-point manner. For exceptions like this, two control input signals are provided, P_DRVR_MODE for the primary interface and S_DRVR_MODE for the secondary interface.

  • Page 51: Secondary Reset

    3. Clocking and Reset Options On the de-assertion or rising edge of the P_RST# signal, the initialization pattern is received off of the bus and latched into the bridge. If the indication is that the primary bus is operating in PCI-X mode, an internal PLL sources the clock tree for the primary clock domain.

  • Page 52: Figure 4: De-Assertion Of S_Rst

    3. Clocking and Reset Options When the secondary bus is operating in PCI-X mode, an internal PLL sources the clock tree for the secondary clock domain inside the Tsi310. The appropriate range and tuning bits for the PLL are set once the initialization pattern is known, and an internal PLL reset signal is deactivated to allow the PLL to begin locking to the S_CLK input frequency.

  • Page 53: Bus Parking And Bus Width Determination

    3. Clocking and Reset Options Table 7, the terms “P_cycles” and “S_cycles” refer to clock cycles whose period is determined by the P_CLK and S_CLK input frequencies, respectively. Since the time periods listed in the table are based on counters, different clock rates will result in different effective delays, as shown.

  • Page 54: Power Management And Hot-Plug

    3. Clocking and Reset Options Power Management and Hot-Plug The Tsi310 is compliant with the minimum requirements of the PCI Bus Power Management Interface Specification (Revision 2.0), as it supports the D0 and D3 power management states and the power management capabilities registers. No other power management functions are implemented by the Tsi310.

  • Page 55: Secondary Device Masking

    3. Clocking and Reset Options Secondary Device Masking The Tsi310 supports the masking of secondary devices through configuration/power strapping of the secondary bus private device mask register. The process of converting Type 1 configuration transactions to Type 0 configuration transactions is modified by the contents of the secondary bus private device mask register.

  • Page 56: Optional Configuration Register Access From The Secondary Bus

    3. Clocking and Reset Options This 64-bit base address register and the memory space defined by it are enabled by the strapping pin, BAR_EN. When BAR_EN is pulled low, this register location returns zeros for reads and cannot be written. When BAR_EN is pulled high, the upper memory base address register and lower memory base address registers combined specify address bits 63:20 of a memory region.

  • Page 57: Short Term Caching

    3. Clocking and Reset Options 3.13 Short Term Caching Short Term Caching was developed to provide performance improvements where upstream devices are not able to stream data continuously to meet the prefetching needs of the Tsi310. As defined in the PCI-to-PCI Bridge Architecture Specification (Revision 2.0), when the master completes the transaction, the bridge is required to discard the balance of any data that was prefetched for the master.
  • Page 58 3. Clocking and Reset Options Tsi310 User Manual 80B6020_MA001_05...

  • Page 59: Transaction Ordering

    Transaction Ordering This chapter discusses the following topics: • “Overview of Transaction Ordering” on page 59 • “General Ordering Guidelines” on page 59 • “Ordering Rules” on page 60 Overview of Transaction Ordering To maintain data coherence and consistency, the Tsi310 complies with the ordering rules set forth in the PCI Local Bus Specification (Revision 2.2) for the PCI mode and the PCI-X Addendum to PCI Local Bus Specification (Revision 1.0a) for the PCI-X mode.

  • Page 60: Ordering Rules

    4. Transaction Ordering • The acceptance of posted memory or memory write transactions as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true of the bridge and must also be true of other bus agents; otherwise, a deadlock can occur.

  • Page 61: Table 9: Tsi310 Ordering Rules - Pci Mode

    4. Transaction Ordering Table 9: Tsi310 Ordering Rules — PCI Mode Can Row Pass Column? Posted Memory Delayed Read Delayed Write Delayed Read Delayed Write Bus Operation Write Request Request Completion Completion Posted Memory Write Delayed Read Request Delayed Write Request Delayed Read 1) No...
  • Page 62 4. Transaction Ordering Tsi310 User Manual 80B6020_MA001_05...

  • Page 63: Configuration Registers

    Configuration Registers This chapter describes the standard and device specific configuration registers contained within the bridge. These registers provide various control and status reporting functions. Registers are accessible from the primary interface using the configuration read and configuration write commands. This chapter discusses the following topics: •...

  • Page 64: Configuration Space

    5. Configuration Registers 5.1.2 Configuration Space The PCI and PCI-X specifications define a separate address space called the configuration space in which the configuration registers are located. It is a contiguous block of 256 bytes, subdivided into two regions: The first 64 bytes are the PCI configuration space header region, which provides for identification, configuration, and recovery capabilities.

  • Page 65: Register Map

    5. Configuration Registers Register Map The following table contains a map of Tsi310’s registers in the PCI Configuration Space. The reserved registers and bits return zeros when read. Table 11: Register Map Bits/Register Names Starting 31:24 23:16 15:08 07:00 Address Region Subregion Device ID...
  • Page 66 5. Configuration Registers Table 11: Register Map (Continued) Bits/Register Names Starting 31:24 23:16 15:08 07:00 Address Region Subregion Secondary Data Buffering Primary Data Buffering Control x‘40’ Device Control Dependent Region Reserved Miscellaneous x‘44’ (192 bytes) Control Reserved x‘48’ - x‘4C’ Reserved Arbiter Mode x‘50’...
  • Page 67 5. Configuration Registers Table 11: Register Map (Continued) Bits/Register Names Starting 31:24 23:16 15:08 07:00 Address Region Subregion Data Register Bridge Support Power Management x‘94’ Device Extensions Control/Status Dependent Region - Reserved x‘98’ - x‘AC’ Continued (192 bytes) Secondary Bus Private Device Mask x‘B0’...

  • Page 68: Register Summary

    5. Configuration Registers Register Summary The following table provides a list of Tsi310’s registers. Table 12: Register Summary Starting Register Name Address Description See Page PCI Configuration Space Header Registers Vendor ID x‘00’ Manufacturer ID, assigned by the PCI Special Interest Group Device ID x‘02’...
  • Page 69 5. Configuration Registers Table 12: Register Summary (Continued) Starting Register Name Address Description See Page Prefetchable Base Upper 32 Bits x‘28’ Base of prefetchable address range bits 63:32 Prefetchable Limit Upper 32 Bits x‘2C’ Upper limit of prefetchable address range bits 63:32 I/O Base Upper 16 Bits x‘30’...
  • Page 70 5. Configuration Registers Table 12: Register Summary (Continued) Starting Register Name Address Description See Page Opaque Memory Limit x‘76’ Specifies upper limit of opaque memory address range (bits 31:20) Opaque Memory Base Upper 32 x‘78’ Specifies base of opaque memory address range (bits Bits 63:32) Opaque Memory Limit Upper 32...

  • Page 71: Pci Configuration Space Header Registers

    Vendor ID. This read-only register contains the Vendor ID. The value assigned is x‘1014’. Note: The original manufacturer of the Tsi310 is IBM Corporation. The device was acquired by Tundra Semiconductor then Tundra was acquired by IDT. Tsi310 User Manual 80B6020_MA001_05...

  • Page 72: Device Id Register

    Device ID. This read-only register contains the Device ID. This value is x‘01A7’. Note: The original manufacturer of the Tsi310 is IBM Corporation. The device was acquired by Tundra Semiconductor then Tundra was acquired by IDT. Tsi310 User Manual 80B6020_MA001_05...

  • Page 73: Command Register

    5. Configuration Registers 5.4.3 Command Register This register provides a variety of configurable parameters defining the device’s interaction with the PCI bus. Address Offset x‘04’ Access See individual bit fields. Reset Value x‘0000’ Reserved 15 14 13 12 11 10 9 Bit(s) Access Field Name and Description...
  • Page 74 5. Configuration Registers Bit(s) Access Field Name and Description Parity Error Response 0 = Ignore detected parity errors. 1 = Respond to detected parity errors. Controls the response to address and data parity errors on the primary interface. If this bit is set, the bridge must take its normal action when a parity error is detected.

  • Page 75: Status Register

    5. Configuration Registers 5.4.4 Status Register This register records the status of PCI events. Address Offset x‘06’ Access See individual bit fields. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a ‘1’.
  • Page 76 5. Configuration Registers Bit(s) Access Field Name and Description 10:9 Device Select (DEVSEL) Timing Status 01 = Medium-speed device Data Parity Status 0 = No data parity errors encountered. 1 = Data parity errors encountered (this bit for bus masters only). Fast Back-to-Back Status 0 = Target not capable of accepting fast back-to-back transactions in PCI-X mode.

  • Page 77: Revision Id Register

    5. Configuration Registers 5.4.5 Revision ID Register This register specifies the Revision ID for the PCI-X to PCI-X Bridge. Address Offset x‘08’ Access Read only Reset Value x‘03’ Revision ID Bit(s) Access Field Name and Description x‘00’ = Revision 1.0 of the device x‘01’...

  • Page 78: Cache Line Size Register

    5. Configuration Registers 5.4.7 Cache Line Size Register This register specifies the cache line size in 32-bit DWord units (not used when the interface is in PCI-X mode). Address Offset x‘0C’ Access Read/Write Reset Value x‘00’ Restrictions Only one bit can be set at any time, if multiple bits are set or if the bits are in an invalid setting, these bits default to the 32 DWords setting.

  • Page 79: Latency Timer Register

    5. Configuration Registers 5.4.8 Latency Timer Register This register specifies, in PCI bus clock units, the value of the latency timer for this device as a bus master. Masters that can burst for more than two data phases must implement this register as Read/Write.

  • Page 80: Header Type Register

    5. Configuration Registers 5.4.9 Header Type Register This read only register specifies that a type x‘01’ header is being used for this device. Address Offset x‘0E’ Access Read only Reset Value x‘01’ Header Type Bit(s) Access Field Name and Description x‘01’...

  • Page 81: Lower Memory Base Address Register

    5. Configuration Registers 5.4.11 Lower Memory Base Address Register This register and the memory space defined by it are enabled by the strapping pin, BAR_EN. When the BAR_EN pin is pulled low, this register location returns zeros for reads and cannot be written.
  • Page 82 5. Configuration Registers Bit(s) Access Field Name and Description 31:20 Lower Memory Base Address Address bits 31:20 of the base address for an address range of prefetchable memory operations that are passed from the primary to the secondary PCI bus. 19:4 Reserved Prefetchable indicator...

  • Page 83: Upper Memory Base Address Register

    5. Configuration Registers 5.4.12 Upper Memory Base Address Register This register and the memory space defined by it are enabled by the strapping pin, BAR_EN. When the BAR_EN pin is pulled low, this register location returns zeros for reads and cannot be written.

  • Page 84: Primary Bus Number Register

    5. Configuration Registers 5.4.13 Primary Bus Number Register The Primary Bus Number register records the bus number of the PCI bus segment to which the primary interface of the bridge is connected. The configuration software programs the value in this register. The bridge uses this register to decode Type 1 configuration transactions on the secondary interface that must be converted to special cycle transactions on the primary interface.

  • Page 85: Secondary Bus Number Register

    5. Configuration Registers 5.4.14 Secondary Bus Number Register The secondary bus number register records the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. The configuration software programs the value in this register. The bridge uses this register to decode Type 1 configuration transactions on the primary interface that must be converted to Type 0 configuration transactions on the secondary interface.

  • Page 86: Subordinate Bus Number Register

    5. Configuration Registers 5.4.15 Subordinate Bus Number Register The subordinate bus number register records the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. The configuration software programs the value in this register. The bridge uses this register in conjunction with the secondary bus number register to determine when to respond to a Type 1 configuration transaction on the primary interface and pass it to the secondary interface.

  • Page 87: Secondary Latency Timer Register

    5. Configuration Registers 5.4.16 Secondary Latency Timer Register This register specifies, in PCI bus clock units, the value of the secondary latency timer for this device as a bus master. Bus masters that can burst for more than two data phases must implement this register as Read/Write.

  • Page 88: I/O Base Register

    5. Configuration Registers 5.4.17 I/O Base Register The I/O Base register specifies the base of the I/O address range bits 15:12 and is used in conjunction with the I/O limit register and I/O base upper 16 bits and I/O limit upper 16 bits registers to specify a range of 32-bit addresses supported for I/O transactions on the PCI bus.

  • Page 89: I/O Limit Register

    5. Configuration Registers 5.4.18 I/O Limit Register This register specifies the upper address of the I/O address range bits 15:12 and is used in conjunction with the I/O base register and I/O base upper 16 bits and I/O limit upper 16 bits to specify a range of 32-bit addresses supported for I/O transactions on the PCI bus.

  • Page 90: Secondary Status Register

    5. Configuration Registers 5.4.19 Secondary Status Register This register is similar in function and bit definition to the Status register. However, its bits reflect status conditions of the secondary interface. Address Offset x‘1E’ Access See individual bit fields. Writes are slightly different in that bits can be reset, but not set.
  • Page 91 5. Configuration Registers Bit(s) Access Field Name and Description Signaled Target Abort Status 0 = Target device did not terminate a transaction with target abort. 1 = Target device terminated a transaction with target abort. 10:9 Device Select (DEVSEL#) Timing Status 01 = Medium-speed device Data Parity Status 0 = No data parity errors encountered.

  • Page 92: Memory Base Register

    5. Configuration Registers 5.4.20 Memory Base Register This register specifies the base of the memory mapped I/O address range bits 31:20 and is used in conjunction with the Memory Limit register to specify a range of 32-bit addresses supported for memory mapped I/O transactions on the PCI Bus. Address bits 19:0 are assumed to be x‘0 0000’...

  • Page 93: Memory Limit Register

    5. Configuration Registers 5.4.21 Memory Limit Register This register specifies the upper address of the memory-mapped I/O address range bits 31:20 and is used in conjunction with the memory base register to specify a range of 32-bit addresses supported for memory mapped I/O transactions on the PCI bus. Address bits 19:0 are assumed to be x‘F FFFF’...

  • Page 94: Prefetchable Memory Base Register

    5. Configuration Registers 5.4.22 Prefetchable Memory Base Register This register specifies the base of the prefetchable memory address range bits 31:20 and is used in conjunction with the prefetchable memory limit register, the prefetchable base upper 32 bits register, and the prefetchable limit upper 32 bits register to specify a range of 64-bit addresses supported for prefetchable memory transactions on the PCI bus.

  • Page 95: Prefetchable Memory Limit Register

    5. Configuration Registers 5.4.23 Prefetchable Memory Limit Register This register specifies the upper address of the prefetchable memory address range bits 31:20 and is used in conjunction with the prefetchable memory base register, the prefetchable base upper 32 bits register, and the prefetchable limit upper 32 bits register to specify a range of 64-bit addresses supported for prefetchable memory transactions on the PCI bus.

  • Page 96: Prefetchable Base Upper 32 Bits Register

    5. Configuration Registers 5.4.24 Prefetchable Base Upper 32 Bits Register This register specifies the base of the prefetchable memory address range bits 63:32 and is used in conjunction with the prefetchable memory base register, the prefetchable memory limit register, and the prefetchable limit upper 32 bits register to specify a range of 64-bit addresses supported for prefetchable memory transactions on the PCI bus.

  • Page 97: Prefetchable Limit Upper 32 Bits Register

    5. Configuration Registers 5.4.25 Prefetchable Limit Upper 32 Bits Register This register specifies the upper address of the prefetchable memory address range bits 63:32 and is used in conjunction with the prefetchable memory base register, the prefetchable memory limit register, and the prefetchable base upper 32 bits register to specify a range of 64-bit addresses supported for prefetchable memory transactions on the PCI bus.

  • Page 98: I/O Base Upper 16 Bits Register

    5. Configuration Registers 5.4.26 I/O Base Upper 16 Bits Register This register specifies the base of the I/O address range bits 31:16 and is used in conjunction with the I/O base register, the I/O limit register, and I/O limit upper 16 bits register to specify a range of 32-bit addresses supported for I/O transactions on the PCI bus.

  • Page 99: I/O Limit Upper 16 Bits Register

    5. Configuration Registers 5.4.27 I/O Limit Upper 16 Bits Register This register specifies the upper address of the I/O address range bits 31:16 and is used in conjunction with the I/O base register, I/O limit register and I/O base upper 16 bits register to specify a range of 32-bit addresses supported for I/O transactions on the PCI bus.

  • Page 100: Capabilities Pointer Register

    5. Configuration Registers 5.4.28 Capabilities Pointer Register This register specifies a pointer to a capabilities list item in configuration space. Address Offset x‘34’ Access Read only Reset Value x‘80’ Capabilities Pointer Bit(s) Access Field Name and Description Capabilities Pointer Read-only pointer to a capabilities list in configuration space. 5.4.29 Reserved Registers These registers are reserved and return zeros when read.

  • Page 101: Interrupt Line Register

    5. Configuration Registers 5.4.30 Interrupt Line Register This register is a read/write register that communicates interrupt line routing information between initialization code and the device driver. If a bridge does not implement an interrupt signal pin, then the power on self test (POST) code must write x‘FF’ to this register. Address Offset x‘3C’...

  • Page 102: Bridge Control Register

    5. Configuration Registers 5.4.32 Bridge Control Register This register provides extensions to the command register that are specific to a bridge. The bridge control register provides many of the same controls for the secondary interface that are provided by the command register for the primary interface. Some bits affect the operation of both bridge interfaces.
  • Page 103 5. Configuration Registers Bit(s) Access Field Name and Description Secondary Discard Timer 0 = Secondary Discard Timer counts 2 PCI clock cycles. 1 = Secondary Discard Timer counts 2 PCI clock cycles. Ignored by the bridge if the secondary interface is in PCI-X mode. Primary Discard Timer 0 = Primary Discard Timer counts 2 PCI clock cycles.
  • Page 104 5. Configuration Registers Bit(s) Access Field Name and Description ISA Enable 0 = Forward downstream all I/O addresses in address range defined by I/O Base and I/O Limit registers. 1 = Forward upstream ISA I/O addresses in address range defined by I/O Base and I/O Limit registers in the first 64 KB of PCI I/O address space (top 768 bytes of each 1 KB block).

  • Page 105: Device-Specific Configuration Space Registers

    5. Configuration Registers Device-Specific Configuration Space Registers The following sections describe the individual registers of the device-specific configuration space region. 5.5.1 Primary Data Buffering Control Register This register provides controls for memory read transactions that are initiated on the primary interface.
  • Page 106 5. Configuration Registers Bit(s) Access Field Name and Description Reserved 14:12 Maximum Memory Read Byte Count These bits set the maximum byte count used by the bridge when generating read requests on the secondary bus in response to a memory read operation initiated on the primary bus (when the primary bus is in PCI mode).
  • Page 107 5. Configuration Registers Bit(s) Access Field Name and Description Primary Read prefetch mode bits (prefetchable range only) Controls prefetching for memory read transactions in prefetchable range that are initiated on the primary bus. 00 = One cache line prefetch. 01 = Reserved. 10 = Full prefetch.

  • Page 108: Secondary Data Buffering Control Register

    5. Configuration Registers 5.5.2 Secondary Data Buffering Control Register This register provides controls for memory read transactions that are initiated on the secondary interface. Address Offset x‘42’ Access See individual bit fields. Reset Value x‘0020’ 15 14 13 12 11 10 9 Tsi310 User Manual 80B6020_MA001_05...
  • Page 109 5. Configuration Registers Bit(s) Access Field Name and Description Reserved 14:12 Maximum Memory Read Byte Count These bits set the maximum byte count used by the bridge when generating read requests on the primary bus in response to a memory read operation initiated on the secondary bus (when the secondary bus is in PCI mode).
  • Page 110 5. Configuration Registers Bit(s) Access Field Name and Description Secondary Read prefetch mode bits Controls prefetching for memory read transactions, that are initiated on the secondary bus. 00 = One cache line prefetch. 01 = Reserved. 10 = Full prefetch. 11 = No prefetching, full handshake between initiator and target.

  • Page 111: Miscellaneous Control Register

    5. Configuration Registers 5.5.3 Miscellaneous Control Register This register provides controls for miscellaneous functions, such as handling parity errors, in the bridge. Address Offset x‘44’ Access Read/Write Reset Value x‘03’ When P_CFG_BUSY (pin C6) is tied low. For more information on strapping considerations, see Section 6.4 on page 157.
  • Page 112 5. Configuration Registers Bit(s) Access Field Name and Description Data Parity Error Recovery Enable 0Allow the bridge to pass parity errors through the bridge. 1 = Cause SERR# to be asserted whenever either Master Data Parity Error bit (bit 8 in either the Status or the Secondary Status register) is set.

  • Page 113: Arbiter Mode Register

    5. Configuration Registers 5.5.4 Arbiter Mode Register This register provides controls for the secondary bus arbitration logic on the bridge. Address Offset x‘50’ Access See bit descriptions. Reset Value x’0800’ When S_INT_ARB_EN# (pin T21) is tied low. For more information on strapping considerations, see Section 6.4 on page 157.
  • Page 114 5. Configuration Registers Bit(s) Access Field Name and Description Broken Master Timeout Enable This bit enables the internal arbiter to count 16 PCI bus cycles while waiting for FRAME# to become active when a device’s PCI Bus Grant is active and the PCI bus is idle. If the Broken Master Timeout expires the PCI Bus Grant for the device is de-asserted.

  • Page 115: Arbiter Enable Register

    5. Configuration Registers 5.5.5 Arbiter Enable Register This register enables arbitration for the requestors of the internal secondary bus arbitration logic on the bridge. Address Offset x‘54’ Access Read/Write Reset Value x‘7F’ Bit(s) Access Field Name and Description Reserved Enable Arbiter 6 0 = Disable arbitration.
  • Page 116 5. Configuration Registers Bit(s) Access Field Name and Description Enable Arbiter 2 0 = Disable arbitration. 1 = Enable arbitration. Enable Arbiter 1 0 = Disable arbitration. 1 = Enable arbitration. Enable Arbiter 0 This bit enables arbitration for the internal bridge requests. 0 = Disable arbitration.

  • Page 117: Arbiter Priority Register

    5. Configuration Registers 5.5.6 Arbiter Priority Register This register indicates whether high or low priority is assigned to the corresponding request of the internal secondary bus arbitration logic on the bridge. Address Offset x‘58’ Access Read/Write Reset Value x‘01’ Bit(s) Access Field Name and Description Reserved...
  • Page 118 5. Configuration Registers Bit(s) Access Field Name and Description Arbiter Priority 2 0 = Low priority request. 1 = High priority request. Arbiter Priority 1 0 = Low priority request. 1 = High priority request. Arbiter Priority 0 This bit indicates the priority for the internal bridge requests. 0 = Low priority request.

  • Page 119: Serr# Disable Register

    5. Configuration Registers 5.5.7 SERR# Disable Register This register controls the assertion of the SERR# signal on the primary bus due to certain errors. Address Offset x‘5C’ Access Read/Write Reset Value x‘00’ Bit(s) Access Field Name and Description Reserved PERR# on Posted Writes SERR# Disable Controls the SERR# assertion when a PERR# is detected on the destination bus on an error free posted write.
  • Page 120 5. Configuration Registers Bit(s) Access Field Name and Description Secondary Discard Timer SERR# Disable Controls the SERR# assertion when the secondary discard timer has expired. 0 = Assert SERR# and update status bit 14 in the Status register if the secondary discard timer expires, the SERR# enable bit 8 in the command register is set, and bit 11 of the bridge control register is set.

  • Page 121: Primary Retry Counter Register

    5. Configuration Registers 5.5.8 Primary Retry Counter Register This register defines the number of retries that the bridge receives on the secondary bus for a requested transaction, before its internal retry counter expires. When the counter expires, the bridge discards the request, and, if enabled, will issue SERR# on the primary bus. This mechanism prevents deadlock when the target is unable to receive the request, and allows recovery through the use of SERR#.
  • Page 122 5. Configuration Registers Bit(s) Access Field Name and Description 15:9 Reserved. This bit used to indicate 256 retries before expiration. Reserved. Tsi310 User Manual 80B6020_MA001_05...

  • Page 123: Secondary Retry Counter Register

    5. Configuration Registers 5.5.9 Secondary Retry Counter Register This register defines the number of retries that the Tsi310 will receive on the primary bus for a requested transaction, before its internal retry counter expires. When the counter expires, the bridge discards the request, and if enabled, issues SERR# on the secondary bus. This mechanism prevents deadlock when the target is unable to receive the request, and allows recovery through the use of SERR#.
  • Page 124 5. Configuration Registers Bit(s) Access Field Name and Description 15:9 Reserved. This bit used to indicate 256 retries before expiration. Reserved. Tsi310 User Manual 80B6020_MA001_05...

  • Page 125: Discard Timer Control Register

    5. Configuration Registers 5.5.10 Discard Timer Control Register This register controls the duration and enabling of the discard timers. There is a unique discard timer for every delayed transaction enqueued in the bridge. A discard timer begins counting at the receipt of a delayed transaction in the conventional PCI mode. The timer is reset each time the initiating bus master retries the transaction.
  • Page 126 5. Configuration Registers Bit(s) Access Field Name and Description Secondary Discard Timer Short Duration Controls the number of PCI clocks that the secondary discard timer allows before it expires. 0 = Use bit 9 of the bridge control register to indicate how many PCI clocks should be allowed before the secondary discard timer expires.

  • Page 127: Retry And Timer Status Register

    5. Configuration Registers 5.5.11 Retry and Timer Status Register This register indicates if a retry counter or a discard timer has expired since the register was last reset. Address Offset x‘6C’ Access See individual bit descriptions. Reads to this register behave normally.

  • Page 128: Opaque Memory Enable Register

    5. Configuration Registers 5.5.12 Opaque Memory Enable Register This register enables the opaque memory base, opaque memory limit, opaque memory base upper 32 bits, and the opaque memory limit upper 32 bits registers. These registers specify a range of 64-bit memory addresses that are used exclusively on the secondary PCI bus and are not to be accepted by the bridge on either the primary or secondary interfaces.

  • Page 129: Opaque Memory Base Register

    5. Configuration Registers 5.5.13 Opaque Memory Base Register This register specifies base address bits 31:20 of the opaque memory address range. It is used in conjunction with the opaque memory limit register, the opaque memory base upper 32 bits register, and the opaque memory limit upper 32 bits register to specify a range of 64-bit memory addresses that are used exclusively on the secondary bus.

  • Page 130: Opaque Memory Limit Register

    5. Configuration Registers 5.5.14 Opaque Memory Limit Register This register specifies upper address bits 31:20 of the opaque memory address range. It is used in conjunction with the opaque memory base register, the opaque memory base upper 32 bits register, and the opaque memory limit upper 32 bits register to specify a range of 64-bit addresses that are used exclusively on the secondary bus.

  • Page 131: Opaque Memory Base Upper 32 Bits Register

    5. Configuration Registers 5.5.15 Opaque Memory Base Upper 32 Bits Register This register specifies bits 63:32 of the base address of the opaque memory address range. It is used in conjunction with the opaque memory base register, the opaque memory limit register, and the opaque memory limit upper 32 bits register to specify a range of 64-bit addresses that are used exclusively on the secondary bus.

  • Page 132: Opaque Memory Limit Upper 32 Bits Register

    5. Configuration Registers 5.5.16 Opaque Memory Limit Upper 32 Bits Register This register specifies upper address bits 63:32 of the opaque memory address range. It is used in conjunction with the opaque memory base register, the opaque memory limit register, and the opaque memory base upper 32 bits register to specify a range of 64-bit addresses that are used exclusively on the secondary bus.

  • Page 133: Pci-X Id Register

    5. Configuration Registers 5.5.17 PCI-X ID Register This register identifies this register set in the capabilities list as a PCI-X register set. It is read-only, returning x‘07’ when read. Address Offset x‘80’ Access Read only Reset Value x‘07’ PCI-X Capability ID Bit(s) Access Field Name and Description...

  • Page 134: Next Capabilities Pointer Register

    5. Configuration Registers 5.5.18 Next Capabilities Pointer Register This register of the PCI-X register set is a read-only register returning x‘90’ when read, indicating that there are more list items in the capabilities list. Address Offset x‘81’ Access Read only Reset Value x‘90’...

  • Page 135: Pci-X Secondary Status Register

    5. Configuration Registers 5.5.19 PCI-X Secondary Status Register This register reports status information about the secondary interface. Address Offset x‘82’ Access See individual bit descriptions. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set.
  • Page 136 5. Configuration Registers Bit(s) Access Field Name and Description Split Request Delayed This bit is set any time the bridge has a request to forward a transaction to the secondary bus, but cannot because there is not enough room within the limit specified in the split transaction commitment limit field in the downstream split transaction control register.

  • Page 137: Pci-X Bridge Status Register

    5. Configuration Registers 5.5.20 PCI-X Bridge Status Register This register identifies the capabilities and current operating mode of the bridge on its primary bus. Address Offset x‘84’ Access See individual bit descriptions. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set.
  • Page 138 5. Configuration Registers Bit(s) Access Field Name and Description Unexpected Split Completion This bit is set if an unexpected split completion with a requester ID equal to the bridge’s primary bus number, device number, and function number is received on the bridge’s primary interface. 0 = No unexpected split completion has been received.
  • Page 139 5. Configuration Registers Bit(s) Access Field Name and Description Device Number These bits are read for diagnostic purposes only. They indicate the number of this device, which is the number in the device number field (AD[15:11]) of the address of a Type 0 configuration transaction that is assigned to this bridge by the connection of the system hardware.

  • Page 140: Secondary Bus Upstream Split Transaction Register

    5. Configuration Registers 5.5.21 Secondary Bus Upstream Split Transaction Register This register controls the behavior of the bridge buffers for forwarding split transactions from a secondary bus requester to a primary bus completer. When the completer bus is in PCI-X mode, the split transaction commitment limit field only affects the byte count used when issuing read requests.

  • Page 141: Primary Bus Downstream Split Transaction Register

    5. Configuration Registers 5.5.22 Primary Bus Downstream Split Transaction Register This register controls the behavior of the bridge buffers when forwarding split transactions from a primary bus requester to a secondary bus completer. When the completer bus is in PCI-X mode, the split transaction commitment limit field only affects the byte count used when issuing read requests.

  • Page 142: Power Management Id Register

    5. Configuration Registers 5.5.23 Power Management ID Register This register identifies this register set in the capabilities list as a power management register set. It is read-only, returning x‘01’ when read. Address Offset x‘90’ Access Read only Reset Value x‘01’ Power Management ID Bit(s) Access...

  • Page 143: Power Management Capabilities Register

    5. Configuration Registers 5.5.25 Power Management Capabilities Register This register reports information about the capabilities of the secondary interface with regard to power management functions. Address Offset x‘92’ Access Read only Reset Value x‘0002’ 15 14 13 12 11 10 9 Bit(s) Access Field Name and Description...

  • Page 144: Power Management Control/Status Register

    5. Configuration Registers 5.5.26 Power Management Control/Status Register This register reports status information about the secondary interface. Address Offset x‘94’ Access See bit descriptions Reset Value x‘0000’ 15 14 13 12 11 10 9 Bit(s) Access Field Name and Description PME Status Forced to b‘0’...

  • Page 145: Pci-To-Pci Bridge Support Extensions Register

    5. Configuration Registers 5.5.27 PCI-to-PCI Bridge Support Extensions Register This register is read only and indicates that the bridge will not stop the clocks on a change of power state. Address Offset x‘96’ Access Read only Reset Value x‘00’ Reserved Bit(s) Access Field Name and Description...

  • Page 146: Secondary Bus Private Device Mask Register

    5. Configuration Registers 5.5.29 Secondary Bus Private Device Mask Register This register provides a means to implement private devices on the secondary PCI bus. The process of converting Type 1 configuration transactions to Type 0 configuration transactions is modified by the contents of this register. A configuration transaction that targets a device masked by this register is rerouted to device 15.
  • Page 147 5. Configuration Registers Bit(s) Access Field Name and Description Private Device Mask 9 0 = Rerouting disabled for device 9. 1 = Block assertion of S_AD(pin 25) for configuration transactions to device 9, assert S_AD(pin 31) instead. Reserved Masking for devices 8 is not implemented. Operation of the Tsi310 is unaffected by the value of this bit.

  • Page 148: Miscellaneous Control Register 2

    5. Configuration Registers 5.5.30 Miscellaneous Control Register 2 This register provides additional control over the memory read prefetch algorithm employed by the Tsi310 when both the primary and secondary buses are in PCI mode. Address Offset x‘B8’ Access See individual fields. Reset Value b‘0000 0000 0000 00x0’...
  • Page 149 5. Configuration Registers Bit(s) Access Field Name and Description Primary Prefetch Persistence Control Affects the how the bridge reacts to target disconnect when prefetching data on the secondary bus for read transactions that are initiated on the primary bus. 0 = Discontinue prefetching when the target disconnects regardless of how much data has been buffered 1 = Continue prefetching despite target disconnects until either: the byte count specified by Primary Data Buffering Control Register has been prefetched, or the initiator disconnects.
  • Page 150 5. Configuration Registers Tsi310 User Manual 80B6020_MA001_05...

  • Page 151: Signals And Pinout

    Signals and Pinout This chapter discusses the following topics: • “Overview of Signals and Pinout” on page 151 • “Primary Interface Signals” on page 151 • “Secondary Interface Signals” on page 154 • “Strapping Pins and Other Signals” on page 157 •...
  • Page 152 6. Signals and Pinout Table 13: Primary Interface Signals (Continued) Signal Name Width Description P_DEVSEL# Device Select: Asserted by the target on the primary bus that decoded the address of the current transaction as being within one of its address ranges. P_DEVSEL# is monitored by the bridge when performing a primary bus transaction on behalf of a secondary bus master.
  • Page 153 6. Signals and Pinout Table 13: Primary Interface Signals (Continued) Signal Name Width Description P_PERR# Parity Error: Used to report data parity errors on the primary interface. P_PERR# is monitored by the bridge when performing a primary bus write transaction on behalf of a secondary bus master or when serving as the selected slave for a primary bus read transaction.

  • Page 154: Secondary Interface Signals

    6. Signals and Pinout Secondary Interface Signals Table 14: Secondary Interface Signals Signal Name Width Description S_ACK64# Acknowledge 64-Bit Transfer: Asserted by the currently addressed target on the secondary bus to indicate its willingness to transfer data using 64 bits. S_AD(63:00) Multiplexed Address and Data: These signals are the 64-bit multiplexed address and data bus, shared by other devices on the...
  • Page 155 6. Signals and Pinout Table 14: Secondary Interface Signals (Continued) Signal Name Width Description S_IRDY# Initiator Ready: This signal indicates the ability of the initiator on the secondary bus to complete the current data phase of the transaction. It is used in conjunction with S_TRDY#. S_IRDY# is driven by the bridge when performing a secondary bus transaction on behalf of a primary bus master.
  • Page 156 6. Signals and Pinout Table 14: Secondary Interface Signals (Continued) Signal Name Width Description S_RST# Secondary Bus Reset: S_RST#, driven by the bridge, is the secondary bus reset signal. Asserted when P_RST# is active or when the secondary bus reset bit in the bridge control register is set.

  • Page 157: Strapping Pins And Other Signals

    6. Signals and Pinout Strapping Pins and Other Signals Table 15: Strapping Pins and Other Signals Signal Name Width Description 64_BIT_DEVICE# Physical bus width of the PCI-X device: Used only when the Tsi310 is employed as the bus interface on a PCI-X add-in card. The PCI-X Specification requires that such devices indicate the physical width of their bus in bit 16 of the PCI-X bridge status register.
  • Page 158 6. Signals and Pinout Table 15: Strapping Pins and Other Signals (Continued) Signal Name Width Description P_CFG_BUSY Primary Configuration Busy: Controls the reset and power up value of bit 2 of the miscellaneous control register. Used to sequence initialization with regard to the primary and secondary buses for applications that require access to the bridge configuration registers from the secondary bus.
  • Page 159 6. Signals and Pinout Table 15: Strapping Pins and Other Signals (Continued) Signal Name Width Description S_INT_ARB_EN# Internal Arbiter Enable: Used to choose between the internal arbiter and external arbiter for the secondary bus. 0 = Use the internal arbiter. 1 = Disable the internal arbiter, use an external arbiter.

  • Page 160: Test Signals

    6. Signals and Pinout Test Signals Table 16: Test Signals Signal Name Width Description JTG_TCK JTAG Test Clock: Used to clock state information and test data into and out of the bridge during operation of the IEEE 1149.1 test access port (TAP).

  • Page 161: Power And Ground Connections

    A filtering circuit may be required to ensure a quiet supply at this pin (for more information, see the following section). 6.6.1 Filter Requirements for P_VDDA and S_VDDA For each Tsi310 VDDA pin, IDT recommends the use of a series ferrite bead and a 0.1µf capacitor to ground (see Figure 5).

  • Page 162: Figure 6: Inductor L1 Impedance

    6. Signals and Pinout Table 18: Inductor L1 Characteristics Parameter Value Impedance@100 MHz/20°C 70 Ohms Rated current 200 mA DC resistance 0.15 Ohms Figure 6: Inductor L1 Impedance 1000 Frequency (MHz) Tsi310 User Manual 80B6020_MA001_05...

  • Page 163: Pinout

    6. Signals and Pinout Pinout Tsi310’s pinout is displayed in the following figure. Use this diagram along with the tables in the following sections to locate pin assignments on the Tsi310: • Table 19 on page 164 lists the pinout in numerical order according to signal name. •...

  • Page 164: Pinout - Sorted By Signal Name

    6. Signals and Pinout 6.7.1 Pinout — Sorted by Signal Name The following table lists Tsi310’s pinout in alphabetical order according to signal name. Use this table along with Figure 7 on page 163 to locate Tsi310 signal names or pin assignments. Table 19: Signal Pin Listing by Signal Name Signal Name Grid Position...
  • Page 165 6. Signals and Pinout Table 19: Signal Pin Listing by Signal Name (Continued) Signal Name Grid Position Signal Name Grid Position Signal Name Grid Position P_AD(52) P_AD(16) P_AD(51) P_AD(15) P_AD(50) P_AD(14) P_AD(13) P_SERR# S_AD(31) P_AD(12) P_STOP# S_AD(30) P_AD(11) P_TRDY# S_AD(29) P_AD(10) RESERVED2 S_AD(28)
  • Page 166 6. Signals and Pinout Table 19: Signal Pin Listing by Signal Name (Continued) Signal Name Grid Position Signal Name Grid Position Signal Name Grid Position P_REQ64# S_AD(33) S_C/BE(4)# P_RST# S_AD(32) S_C/BE(3)# AA15 S_C/BE(2)# AB14 S_REQ64# AB13 VDD2 S_C/BE(1)# AB16 S_RST# VDD2 S_C/BE(0)# AB12...

  • Page 167: Pinout - Sorted By Grid Position

    6. Signals and Pinout 6.7.2 Pinout — Sorted by Grid Position The following table lists Tsi310’s pinout according to grid position. Use this table along with Figure 7 on page 163 to locate Tsi310 signal names or pin assignments. Table 20: Signal Pin Listing by Grid Position Signal Name Grid Position Signal Name...
  • Page 168 6. Signals and Pinout Table 20: Signal Pin Listing by Grid Position (Continued) Signal Name Grid Position Signal Name Grid Position Signal Name Grid Position P_C/BE(6)# P_AD(41) P_AD(00) VDD2 VDD2 P_AD(02) P_AD(51) VDD2 P_TRDY# VDD2 P_AD(16) P_AD(14) P_AD(30) VDD2 P_AD(26) P_AD(29) S_AD(18) P_AD(35)
  • Page 169 6. Signals and Pinout Table 20: Signal Pin Listing by Grid Position (Continued) Signal Name Grid Position Signal Name Grid Position Signal Name Grid Position VDD2 S_AD(23) S_AD(39) S_AD(42) S_AD(38) S_AD(53) VDD2 S_AD(52) S_AD(11) VDD2 VDD2 S_IDSEL AA22 T_DI1# S_REQ1GNT# AA23 VDD2 64_BIT_DEVICE#...
  • Page 170 6. Signals and Pinout Tsi310 User Manual 80B6020_MA001_05...

  • Page 171: Jtag Boundary Scan

    JTAG Boundary Scan This chapter discusses the following topics: • “Overview of JTAG Boundary Scan” on page 171 • “TAP Controller Initialization” on page 172 • “JTAG Design Considerations” on page 172 • “Instruction Register and Codes” on page 173 •...

  • Page 172: Tap Controller Initialization

    7. JTAG Boundary Scan TAP Controller Initialization After power-up of the Tsi310, the TAP Controller must be put into its test-logic-reset state to disable the JTAG logic and allow the Tsi310 to function normally. This may be done by driving the JTG_TMS signal high and pulsing the JTG_TCK signal five or more times, or by asserting the JTG_TRST# signal.

  • Page 173: Instruction Register And Codes

    7. JTAG Boundary Scan Instruction Register and Codes The Tsi310 implements a 4-bit Instruction register to control the operation of the JTAG logic. The defined instruction codes are shown in Table 21. Those bit combinations that are not listed are equivalent to the BYPASS (b‘1111’) instruction: Table 21: JTAG Logic Instruction Codes Instruction Code Instruction Name...

  • Page 174: Jtag Device Id Register

    7. JTAG Boundary Scan JTAG Device ID Register This register identifies the manufacturing code, a portion of the die part number, and a device revision code. 32 bits Width Read only Access x‘34940049’ Reset Value Version Part Number Manufacturer ID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bits Access...

  • Page 175: Boundary Scan Register Bit Map

    7. JTAG Boundary Scan • Output-only pins: For device outputs that are not shared with component test functions, the boundary scan cell IBM1149_BSR_BIDIOUT is used. Outputs that are shared with component test inputs use the IBM1149_BSR_OUT boundary scan cell. Those that are shared with component test outputs use the IBM1149_BSR_TESTOUT boundary scan cell.
  • Page 176 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_BIDI P_AD(9) BIDIR IBM1149_BSR_BIDI P_AD(10) BIDIR IBM1149_BSR_BIDI P_AD(11) BIDIR IBM1149_BSR_BIDI P_AD(12) BIDIR IBM1149_BSR_BIDI P_AD(13) BIDIR IBM1149_BSR_BIDI P_AD(14) BIDIR IBM1149_BSR_BIDI_SIO P_AD(15) BIDIR IBM1149_BSR_BIDI...
  • Page 177 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_BIDI P_AD(36) BIDIR IBM1149_BSR_BIDI P_AD(37) BIDIR IBM1149_BSR_BIDI P_AD(38) BIDIR IBM1149_BSR_BIDI P_AD(39) BIDIR IBM1149_BSR_BIDI P_AD(40) BIDIR IBM1149_BSR_BIDI P_AD(41) BIDIR IBM1149_BSR_BIDI P_AD(42) BIDIR IBM1149_BSR_BIDI...
  • Page 178 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_BIDI P_AD(63) BIDIR IBM1149_BSR_BIDI P_CBE(0) BIDIR IBM1149_BSR_BIDI P_CBE(1) BIDIR IBM1149_BSR_BIDI P_CBE(2) BIDIR IBM1149_BSR_BIDI P_CBE(3) BIDIR IBM1149_BSR_BIDI P_CBE(4) BIDIR IBM1149_BSR_BIDI P_CBE(5) BIDIR IBM1149_BSR_BIDI...
  • Page 179 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_BIDI S_ACK64 BIDIR IBM1149_BSR_BIDI S_AD(0) BIDIR IBM1149_BSR_BIDI S_AD(1) BIDIR IBM1149_BSR_BIDI S_AD(2) BIDIR IBM1149_BSR_BIDI S_AD(3) BIDIR IBM1149_BSR_BIDI S_AD(4) BIDIR IBM1149_BSR_BIDI S_AD(5) BIDIR IBM1149_BSR_BIDI...
  • Page 180 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_BIDI S_AD(26) BIDIR IBM1149_BSR_BIDI S_AD(27) BIDIR IBM1149_BSR_BIDI S_AD(28) BIDIR IBM1149_BSR_BIDI S_AD(29) BIDIR IBM1149_BSR_BIDI S_AD(30) BIDIR IBM1149_BSR_BIDI S_AD(31) BIDIR IBM1149_BSR_BIDI S_AD(32) BIDIR IBM1149_BSR_BIDI...
  • Page 181 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_BIDI S_AD(53) BIDIR IBM1149_BSR_BIDI S_AD(54) BIDIR IBM1149_BSR_BIDI S_AD(55) BIDIR IBM1149_BSR_BIDI S_AD(56) BIDIR IBM1149_BSR_BIDI S_AD(57) BIDIR IBM1149_BSR_BIDI S_AD(58) BIDIR IBM1149_BSR_BIDI S_AD(59) BIDIR IBM1149_BSR_BIDI...
  • Page 182 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_OUT S_GNT5 OUTPUT3 IBM1149_BSR_OUT S_GNT6 OUTPUT3 IBM1149_BSR_BIDIIN S_INT_ARB_EN INPUT IBM1149_BSR_BIDI S_IRDY BIDIR IBM1149_BSR_BIDI S_LOCK BIDIR IBM1149_BSR_IN S_DRVR_MODE INPUT IBM1149_BSR_BIDI S_PAR BIDIR IBM1149_BSR_BIDI...
  • Page 183 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_IN EN64_BIT_DEVICE INPUT IBM1149_BSR_IN IDSEL_REROUTE_EN INPUT IBM1149_BSR_IN OPAQUE_EN INPUT IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB...
  • Page 184 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL...
  • Page 185 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL...
  • Page 186 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL...
  • Page 187 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL...
  • Page 188 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL...
  • Page 189 7. JTAG Boundary Scan Table 22: Boundary Scan Register Bit Map (Continued) Tristate Control Position Cell Type Port Name Function Cell IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL IBM1149_BSR_FASTENAB CONTROL...
  • Page 190 7. JTAG Boundary Scan Tsi310 User Manual 80B6020_MA001_05...

  • Page 191: Electrical Characteristics

    Electrical Characteristics This chapter discusses the following topics: • “PCI/PCI-X Specification Conformance” on page 191 • “Absolute Maximum Ratings” on page 192 • “Recommended DC Operating Conditions” on page 193 • “AC Operating Conditions” on page 193 • “Power Dissipation” on page 194 PCI/PCI-X Specification Conformance Most of the Tsi310 interface signals are delineated by the PCI and PCI-X specifications.

  • Page 192: Absolute Maximum Ratings

    8. Electrical Characteristics Absolute Maximum Ratings Stresses greater than the absolute maximum ratings listed in the following table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside of the limits indicated in this specification is not implied.

  • Page 193: Recommended Dc Operating Conditions

    8. Electrical Characteristics Recommended DC Operating Conditions Table 24: Recommended DC Operating Conditions (T = 0 to 70C) Rating Symbol Parameter Minimum Typical Maximum Units Notes Core Logic Power Supply Voltage I/O Power Supply Voltage Input High Voltage 0.5V Input Low Voltage -0.5 0.35V Input Pin Capacitance...

  • Page 194: Power Dissipation

    8. Electrical Characteristics Power Dissipation Table 26: Tsi310 Power Dissipation (Total = I/O + Core) PCI/X Bus1 PCI/X Bus2 Clock Clock Nominal (W) Frequency Frequency PCI/X Bus1 PCI/X Bus2 Minimum Maximum (MHz) (MHz) Load (pF) Load (pF) (Total, Core, I/O) 3.2, 2.7, 0.5 3.0, 2.4, 0.6 2.8, 2.4, 0.4...
  • Page 195 8. Electrical Characteristics Table 26: Tsi310 Power Dissipation (Total = I/O + Core) (Continued) PCI/X Bus1 PCI/X Bus2 Clock Clock Nominal (W) Frequency Frequency PCI/X Bus1 PCI/X Bus2 Minimum Maximum (MHz) (MHz) Load (pF) Load (pF) (Total, Core, I/O) 2.0, 1.5, 0.5 1.9, 1.5, 0.4 1.7, 1.4, 0.3 a.
  • Page 196 8. Electrical Characteristics Tsi310 User Manual 80B6020_MA001_05...

  • Page 197: Package Information

    Package Information This chapter discusses the following topics about Tsi310’s package: • “Package Characteristics” on page 197 • “Thermal Characteristics” on page 199 Package Characteristics Tsi310’s package characteristics are summarized in the following table. Figure 8 displays Tsi310’s package diagram. Table 27: Package Characteristics Feature Description...

  • Page 198: Figure 8: Package Diagram

    9. Package Information Figure 8: Package Diagram 304X  0.75 ± 0.15 Solder Ball Bottom of Package (HPBGA Side Up) Side 12.75 Substrate 27.94 Encapsulation Stiffener 15.5 1.27 0.60 ± 0.1 1.78 max. 1.27 27.94 15.5 Note: All measurements are in millimeters Tsi310 User Manual 80B6020_MA001_05...

  • Page 199: Thermal Characteristics

    9. Package Information Thermal Characteristics The maximum ambient temperature of the Tsi310 can be calculated as follows: Ta  Tj -  Where, = Ambient temperature (°C) = Maximum Tsi310 Junction temperature (°C) = 125°C  = Ambient to Junction Thermal Impedance (°C / Watt) (see Table 28).
  • Page 200 9. Package Information Tsi310 User Manual 80B6020_MA001_05...

  • Page 201: Ordering Information

    Ordering Information This appendix discusses Tsi310’s ordering information. Ordering Information IDT “Tsi” products are designated by a product code. When ordering, please refer to the Tsi310 by its full part number as displayed in the following table. Table 29: Ordering Information...
  • Page 202 A. Ordering Information Tsi310 User Manual 80B6020_MA001_05...

  • Page 203: Index

    Index special cycle generation type 0 type 1 to type 0 translation type 1 to type 1 forwarding Numerics 64_BIT_DEVICE# signal Data Register DC operating conditions absolute maximum ratings Device ID Register AC operating conditions device masking ADB (allowable disconnect boundary) Discard Timer Control Register address decoding document conventions...
  • Page 204 Index P_SERR# signal P_STOP# signal Latency Timer Register P_TRDY# signal lead-free package P_VDDA signal Lower Memory Base Address Register package characteristics package diagram packaging information mechanical information parity error Memory Base Register parity errors Memory Limit Register PCI buffers Miscellaneous Control Register PCI transactions Miscellaneous Control Register 2 PCI-to-PCI Bridge Support Extensions Register...
  • Page 205 Index primary interface T_DI2# signal secondary interface T_MODECTL signal resets T_RI# signal Retry and Timer Status Register TAP controller Revision ID Register TEST_CE0 signal thermal characteristics transaction forwarding S_ACK64# signal transaction ordering S_AD signal transaction ordering guidelines S_C/BE signal transaction types S_CLK signal Type 0 transaction S_CLK_STABLE signal...
  • Page 206 Index Tsi310 User Manual 80B6020_MA001_05...
  • Page 207 Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.

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