Epson S1F76640 Technical Manual page 26

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08. APPLIED CIRCUIT EXAMPLES
Note 1: <Notes on load connection>
As shown in Fig.8.8, when connecting load between V
in the second stage) and V
noted: When the IC is activated or no normal output is generated at the V
off by the P
OFF
below V
in the second stage) through load. If the voltage exceeding the absolute maximum rating
SS
below V
in the second stage is generated at the V
SS
the IC. For serial connection, as shown in Fig.8.8, connect diode D1 between V
and V
, so that the voltage below V
REG
Note 2: In Fig.8.8, the first stage is assigned to triple boosting and the next-stage to quadruple boosting;
however, quadruple boosting is available for both the first and next stages unless the input voltage
V
' - V
' in the next stage exceeds the standard value (6.0V). For serial connection, each IC must be
DD
SS
designed in compliance with the standard (V
Note 3: When double boosting is provided in the first stage, the first-stage CAP1- output can be used as a
next-stage clock; however, when triple boosting is provided, it cannot be used as a next-stage clock.
Therefore, to obtain a next-stage clock, externally install R
in Table 4.2, the next-stage external clock operation by the pre-stage CAP1- output is available only for
temperature gradient CT = -0.5%/°C. If another temperature gradient is required, use an internal
oscillator like the above.
Note 4: In serial connection, the temperature gradient is provided for the V
Fig.8.9) of the IC in which the stabilizer is active.
The V
value changes according to temperature as follows:
REG
Δ | V
|
REG
Δ T
It changes at the ratio above.
20
in the second stage in serial connection, the following points should be
REG
signal, current flows into to the V
CT ( V
(25°C) - V
REG
SS
in the first stage (or other voltage below V
SS
pin from V
REG
pin, the may interfere with normal operation of
REG
in the second stage will not be applied to the V
SS
≤ 6.0V, V
- V
DD
SS
OSC
' )
EPSON
pin while V
REG
in the first stage (or other voltage
SS
in the second stage
DD
≤ 24V) (See Fig.8.9).
- V
O
SS
and use an internal oscillator. As shown
- V
voltage (V
SS
REG
S1F76640 Technical Manual (Rev.1.5)
SS
is turned
REG
pin.
REG
– V
' in
REG
SS

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