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IDT 89HPES16NT2 User Manual

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®
IDT
89HPES16NT2
™
PCI Express® Switch

User Manual

April 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.

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  • Page 1: User Manual

    ® 89HPES16NT2 ™ PCI Express® Switch User Manual April 2008 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2008 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    Content Summary Chapter 1, “PES16NT2 Device Overview,” provides a complete introduction to the performance capa- bilities of the 89HPES16NT2. Included in this chapter is a summary of features for the device as well as a system block diagram and pin description.

  • Page 4: Numeric Representations

    Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter- preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

  • Page 5: Register Terminology

    Notes bit 31 bit 0 Address of Bytes within Words: Big Endian bit 31 bit 0 Address of Bytes within Words: Little Endian Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition Register Terminology Software in the context of this register terminology refers to modifications made by PCIe root configura- tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial- ization.

  • Page 6: Use Of Hypertext

    Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.

  • Page 7: Table Of Contents

    Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Revision History ..........................4 PES16NT2 Device Overview Introduction .............................
  • Page 8 IDT Table of Contents Switch Operation Notes Introduction ............................. 4-1 Routing ............................4-3 Data Integrity ..........................4-4 Switch Time-Outs ........................... 4-5 Interrupts............................4-5 Switch Core Errors.......................... 4-6 Power Management Introduction ............................. 5-1 PME Messages ........................5-2 Link States ............................5-2 Active State Power Management ....................
  • Page 9 IDT Table of Contents Notes Physical Layer Control and Status Registers ............... 9-42 Non-Transparent Mode Operation Introduction ........................... 10-1 Transaction Routing........................10-3 Address Routing ........................10-3 ID Routing..........................10-6 Route to Root Implicit Routing....................10-6 Broadcast from Root Implicit Routing ................... 10-6 Local Terminate at Receiver Implicit Routing ...............
  • Page 10 IDT Table of Contents Notes Non-Transparent Bridge Control and Status Registers ............ 10-146 JTAG Boundary Scan Introduction ........................... 11-1 Test Access Point ......................... 11-1 Signal Definitions .......................... 11-1 Boundary Scan Chain........................11-3 Test Data Register (DR) ....................... 11-3 Boundary Scan Registers..................... 11-4 Instruction Register (IR)........................
  • Page 11 List of Tables ® Table 1.1 PES16NT2 Offset Device IDs....................1-4 Notes Table 1.2 PES16NT2 Revision IDs...................... 1-5 Table 1.3 PCI Express Interface Pins....................1-7 Table 1.4 SMBus Interface Pins ......................1-7 Table 1.5 General Purpose I/O Pins....................1-8 Table 1.6 System Pins.........................1-8 Table 1.7 Test Pins..........................
  • Page 12 IDT List of Tables Notes Table 11.3 Instructions Supported by PES16NT2’s JTAG Boundary Scan ........11-6 Table 11.4 System Controller Device Identification Register .............. 11-7 PES16NT2 User Manual April 15, 2008...
  • Page 13 List of Figures ® Figure 1.1 PES16NT2 Functional Block Diagram ................1-2 Notes Figure 1.2 PES16NT2 Architectural Block Diagram ................1-3 Figure 1.3 PES16NT2 Logic Diagram ....................1-6 Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread Spectrum Clock) ........................2-1 Figure 2.2 Non-Common Clock on Upstream;...
  • Page 14 DT List of Figures Notes PES16NT2 User Manual viii April 15, 2008...
  • Page 15 Register List ® PA_BAR0 - Base Address Register 0 (0x010) ..................9-13 Notes PA_BAR1 - Base Address Register 1 (0x014) ..................9-13 PA_BCTRL - Bridge Control (0x03E) ..................... 9-18 PA_BIST - Built-in Self Test (0x00F)...................... 9-12 PA_CAPPTR - Capabilities Pointer (0x034)................... 9-17 PA_CCODE - Class Code (0x009)......................
  • Page 16 IDT Register List Notes PA_SERDESCTL - SerDes Control (0x200) ...................9-42 PA_SLTIMER - Secondary Latency Timer (0x01B) ................9-13 PA_SMBUSCTL - SMBus Control (0x0B0) .....................9-34 PA_SMBUSSTS - SMBus Status (0x0AC)....................9-33 PA_SUBUSN - Subordinate Bus Number (0x01A) .................9-13 PA_SWCTL - Switch Control (0x0A4) .....................9-31 PA_SWSTS Switch Status (0x0A0) ......................9-30...
  • Page 17 IDT Register List Notes PC_PMLIMIT - Prefetchable Memory Limit (0x026)................10-28 PC_PMLIMITU - Prefetchable Memory Limit Upper (0x02C)..............10-29 PC_PMPC - PCI Power Management Proprietary Control (0x078) ............10-39 PC_PVCCAP1- Port VC Capability 1 (0x104)..................10-48 PC_RID - Revision Identification (0x008)....................10-23 PC_SBUSN - Secondary Bus Number (0x019) ..................10-25 PC_SECSTS - Secondary Status (0x01E)....................10-26...
  • Page 18 IDT Register List Notes PCEE_INTSTS - Interrupt Status (0x0E8) ..................10-138 PCEE_MAXLAT - Maximum Latency (0x03F) ..................10-116 PCEE_MINGNT - Minimum Grant (0x03E) ..................10-115 PCEE_MLTIMER - Master Latency Timer (0x00D)................10-110 PCEE_MSIADDR - Message Signaled Interrupt Address (0x068) .............10-121 PCEE_MSICAP - Message Signaled Interrupt Capability and Control (0x064) ........10-120 PCEE_MSIMDATA - Message Signaled Interrupt Message Data (0x070) .........10-121...
  • Page 19 IDT Register List Notes PCIE_BARTLIMIT2 - BAR 2 Translated Limit Address (0x220)............10-103 PCIE_BARTLIMIT3 - BAR 3 Translated Limit Address (0x224)............10-103 PCIE_BIST - Built-on Self Test (0x00F) ....................10-63 PCIE_CAPPTR - Capabilities Pointer (0x034) ..................10-67 PCIE_CCODE - Class Code (0x009) ....................10-62 PCIE_CLS - Cache Line Size (0x00C)....................10-62 PCIE_DID - Device Identification (0x002) .....................10-59...
  • Page 20 IDT Register List Notes PES16NT2 User Manual April 15, 2008...

  • Page 21: Pes16Nt2 Device Overview

    (NTB) functions between a PCIe® upstream port and an NTB downstream port. The PES16NT2 is a part of the IDT PCIe System Interconnect Products and is intended to be used with IDT PCIe System Interconnect Switches. Together, the chipset targets multi-host and intelligent I/O applications such as communications, storage, and blade servers where inter-domain communication is required.
  • Page 22 IDT PES16NT2 Device Overview Notes Port A (Upstream Port) Type 1 Configuration Header PCI-PCI Transparent Bridge Virtual PCI Bus Type 1 Configuration Header PCI-PCI Transparent Bridge Internal Type 0 Configuration Header Non-Transparent Bridge External Type 0 Configuration Header Port C (Non-Transparent Port) Figure 1.1 PES16NT2 Functional Block Diagram...

  • Page 23: List Of Features

    IDT PES16NT2 Device Overview Notes 2-Port Switch Core Egress Egress GPIO Port Arbiter Port Arbiter Scheduler Scheduler Controller Input Frame Buffer Input Frame Buffer Route Route Table Table Master SMBus Interface Slave SMBus Transaction Transaction Interface Layer Layer Data Link...

  • Page 24: System Identification

    IDT PES16NT2 Device Overview Notes • Two shared scratchpad registers – Allows up to sixteen masters to communicate through the non-transparent port – No limit on the number of supported outstanding transactions through the non-transparent bridge – Completely symmetric non-transparent bridge operation allows similar/same configuration soft- ware to be run –...

  • Page 25: Revision Id

    IDT PES16NT2 Device Overview Revision ID Notes All revision IDs in the PES16NT2 are set to the same value. The value of the revision ID is determined in one place and is easily modified during a metal mask change. The revision ID shall be incremented with each all layer or metal mask change.

  • Page 26: Figure 1.3 Pes16Nt2 Logic Diagram

    IDT PES16NT2 Device Overview Logic Diagram Notes PEREFCLKP Reference PEREFCLKN Clocks REFCLKM PEALREV PEARP[0] PEATP[0] PEARN[0] PEATN[0] PCI Express PCI Express Switch PEATP[1] PEARP[1] Switch SerDes Input PEARN[1] PEATN[1] SerDes Output Port A Port A PEARP[7] PEATP[7] PEARN[7] PEATN[7] PECLREV...

  • Page 27: Pin Description

    IDT PES16NT2 Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES16NT2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...

  • Page 28: Table 1.5 General Purpose I/O Pins

    IDT PES16NT2 Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PECRSTN...

  • Page 29: Table 1.7 Test Pins

    IDT PES16NT2 Device Overview Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside the PES16NT2 and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES16NT2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.

  • Page 30: Pin Characteristics

    IDT PES16NT2 Device Overview Notes Signal Type Name/Description PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. PCI Express Termination Power. Ground. Table 1.8 Power and Ground Pins Pin Characteristics Note: Some input pads of the PES16NT2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
  • Page 31 IDT PES16NT2 Device Overview Notes Internal Function Pin Name Type Buffer I/O Type Notes Resistor System Pins CCLKDS LVTTL Input pull-up CCLKUS pull-up MSMBSMODE pull-down PENTBRSTN PERSTN RSTHALT pull-down SWMODE[3:0] pull-up JTAG JTAG_TCK LVTTL pull-up JTAG_TDI pull-up JTAG_TDO Low Drive...
  • Page 32 IDT PES16NT2 Device Overview Notes PES16NT2 User Manual 1 - 12 April 15, 2008...

  • Page 33: Clocking, Reset, And Initialization

    Chapter 2 Clocking, Reset, and Initialization ® Introduction Notes The PES16NT2 has two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both reference clock input pairs be driven from a common clock source.

  • Page 34: Figure 2.2 Non-Common Clock On Upstream; Common Clock On Downstream (Must Disable Spread Spectrum Clock)

    IDT Clocking, Reset, and Initialization Clock Operation Notes PES16NT2 Port A Root Complex Port C CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum Clock) PES16NT2 Port A...

  • Page 35: Table 2.2 Boot Configuration Vector Signals

    IDT Clocking, Reset, and Initialization Clock Operation Notes PES16NT2 Port A Root Complex Port C CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Clock Generator Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES16NT2 during a fundamental reset when PERSTN is negated.

  • Page 36: Table 2.3 System Pins

    IDT Clocking, Reset, and Initialization Clock Operation Notes May Be Signal Description Overridden PEALREV PCI Express Port A Lane Reverse. When this pin is asserted, the lanes of PCI Express Port A are reversed. This value may be overridden by modifying the value of the PALREV bit in the PA_SWCTL register.

  • Page 37: Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes Signal Type Name/Description PERSTN Fundamental Reset. Assertion of this signal resets all logic inside the PES16NT2 and initiates a PCI Express fundamental reset. RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES16NT2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.
  • Page 38 IDT Clocking, Reset, and Initialization Clock Operation Notes Global Global Ext. Ext. Local Fund. Reset to Reset to Reset Downstr Fund. Entire Reset Reset Reset Device Ports Port A Transaction Layer Port A Data Link Layer Port A Phy Layer...

  • Page 39: Fundamental Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes An External Fundamental reset in non-transparent mode with the PEFR bit set in either NTBCTL register is the same as a fundamental reset. See that column for its behavior. All registers except those in the NTB configuration capability structure.

  • Page 40: Hot Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes Device ready for Boot vector sampled normal operation REFCLK Tpvperl PERSTN < 100 ms RSTHALT 1.01 ms up to 12 µs SerDes PLL Reset and Lock Link Training CDR Reset & Lock...

  • Page 41: Non-Transparent Mode Reset

    IDT Clocking, Reset, and Initialization Clock Operation Notes Globally Initiated Hot Reset To Downstream Ports A hot reset is initiated globally to downstream ports when the following condition occurs: – A one is written to the Secondary Bus Reset (SRESET) bit in the upstream port’s (port A) Bridge Control Register (BCTRL).
  • Page 42 IDT Clocking, Reset, and Initialization Clock Operation Notes mental reset of the entire device and behaves in the same manner as an internal side fundamental reset (see section Fundamental Reset on page 2-7). Otherwise, an external side fundament reset results in the following.
  • Page 43 IDT Clocking, Reset, and Initialization Clock Operation Notes Reception of TS1 ordered-sets on the external side on the non-transparent bridge port indicating a hot reset. The handling of an external side hot reset mirrors that of an external side fundament reset.
  • Page 44 IDT Clocking, Reset, and Initialization Clock Operation Notes PES16NT2 User Manual 2 - 12 April 15, 2008...

  • Page 45: Link Operation

    Chapter 3 Link Operation ® Introduction Notes The PES16NT2 contains two ports. The default link width of each port is x8 and the SerDes lanes are statically assigned to a port. Polarity Inversion Each port of the PES16NT2 supports automatic polarity inversion as required by the PCIe® specifica- tion.

  • Page 46: Figure 3.1 Lane Reversal For Maximum Link Width Of X8

    IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES16NT2 PES16NT2 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5]...

  • Page 47: Figure 3.2 Lane Reversal For Maximum Link Width Of X4

    IDT Link Operation Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 PES16NT2 PES16NT2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x4 Port with PExLREV asserted...

  • Page 48: Link Retraining

    IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES16NT2 PES16NT2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with PExLREV asserted (a) x2 Port with PExLREV negated...

  • Page 49: Crosslink

    IDT Link Operation Crosslink Notes Port A is an upstream port and only supports link training with a downstream port. Port C is an upstream port that supports crosslink operation. This allows port C to link train and operate with any standard PCIe upstream or downstream port.
  • Page 50 IDT Link Operation Notes PES16NT2 User Manual 3 - 6 April 15, 2008...

  • Page 51: Notes

    Chapter 4 Switch Operation ® Introduction Notes The PES16NT2 utilizes an input buffered cut-through switch to forward PCIe® TLPs between switch ports. At a high level the switch may be viewed as consisting of three PCIe stacks and a switch core. The PCIe stacks are each responsible for performing the per port Phy, data link and transaction layer functions defined in the PCIe specification.

  • Page 52: Table 4.2 Pes16Nt2 Advertised Flow Control Credits

    IDT Switch Operation Notes A flow control mechanism exists between the switch buffers and the transaction layer in the ingress stack to prevent overflows. This flow control mechanism forms the basis of the PCIe flow control credits advertised by the stack to the ingress port’s link partner. When a TLP is sent to the switch core from an ingress stack, its header is looked-up in a routing map table and the TLP is queued in a buffer that corre- sponds to the TLP type (i.e., posted, non-posted or completion).

  • Page 53: Routing

    IDT Switch Operation Notes Default Flow Control Advertised Notes Category Credits Non-Posted Data 30 credits Each credit represents 16 bytes (i.e., 4 doublewords) for a max- imum of 480 bytes (note that non-posted data is assumed to consists of only one doubleword per header)

  • Page 54: Data Integrity

    IDT Switch Operation Notes Routing Method TLP Type Using Routing Method Implicit Routing - Broadcast from Root Msg, MsgD Implicit Routing - Local Msg, MsgD Implicit Routing - Gathered and Routed to Only supported for PME_TO_Ack messages in response to a Root root initiated PME_Turn_Off message.

  • Page 55: Switch Time-Outs

    IDT Switch Operation Notes To prevent error flooding, error messages are not sent to the root once the EEPERRC field saturates. Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent End-to-End Parity Checking bit (SEEPC) bit in the SWSICTL register is provided to disable generation of error messages and setting of the Detected Parity Error bit when internal corruption is detected.

  • Page 56: Switch Core Errors

    IDT Switch Operation Notes Table 4.4 exhibits the interrupt sources that are aggregated by the switch. PCI Compatible Interrupt Sources INTx INTA - External downstream port C (in transparent mode) - Non-transparent bridge internal endpoint INTB - External downstream port C (in transparent mode)
  • Page 57 IDT Switch Operation Notes Port arbitration should never be configured to starve a port. If a port arbitration table configuration results in port starvation, then TLPs generated by the port may be dropped (e.g., error messages, inter- rupts, configuration completions, etc.).
  • Page 58 IDT Switch Operation Notes – Reception of a TLP that matches a VGA region in a downstream port when the downstream port’s VGA Enable (VGAEN) bit is set in its Bridge Control (BCTRL) register. – Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared in PCICMD register) or the upstream port when the Bus Master Enable (BME) bit is not set in the PCICMD register.

  • Page 59: Power Management

    Chapter 5 Power Management ® Introduction Notes A power management capability structure is located in the configuration space of each PCI-PCI bridge in the PES16NT2. The structure associated with a PCI-PCI bridge of a downstream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.

  • Page 60: Pme Messages

    IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.

  • Page 61: Active State Power Management

    IDT Power Management Notes L2/L3 Ready Figure 5.2 PES16NT2 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is orthogonal to power management. Once enabled by the ASPM field in the PCI Express® Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.
  • Page 62 IDT Power Management Notes PES16NT2 User Manual 5 - 4 April 15, 2008...

  • Page 63: Smbus Interfaces

    Chapter 6 SMBus Interfaces ® Introduction Notes The PES16NT2 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES16NT2, allowing every register in the device to be read or written by an external SMBus master.

  • Page 64: Smbus Registers

    IDT SMBus Interfaces Notes In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is not required. SMBus Registers Field Default Type Description Field Name Value Reserved Reserved field. SSMBADDR HWINIT Slave SMBus Address. This field contains the SMBus address assigned to the slave SMBus interface.

  • Page 65: Table 6.2 Smbusctl - Smbus Control

    IDT SMBus Interfaces Notes Field Default Type Description Field Name Value 15:0 MSMBCP HWINIT Master SMBus Clock Prescalar. This field contains a clock prescalar value used during master SMBus transac- tions. The prescalar clock period is equal to 32 ns multi- plied by the value in this field.

  • Page 66: Master Smbus Interface

    IDT SMBus Interfaces Master SMBus Interface Notes The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM. Initialization Master SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page 2-7).

  • Page 67: Table 6.4 Base Addresses For Pci Configuration Spaces In The Pes16Nt2

    IDT SMBus Interfaces Notes Base Address Value PCI Configuration Space used to form CSR System Address Upstream Port A 0x0000 Downstream Port C 0x2000 Internal Non-Transparent Bridge Endpoint 0x3000 External Non-Transparent Bridge Endpoint 0x3800 Table 6.4 Base Addresses for PCI Configuration Spaces in the PES16NT2...

  • Page 68: Figure 6.2 Single Double Word Initialization Sequence Format

    IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 DATA[7:0] Byte 3 DATA[15:8] Byte 4 DATA[23:16] Byte 5 DATA[31:24] Figure 6.2 Single Double Word Initialization Sequence Format The second type of configuration block is the sequential double word initialization sequence. It is similar to a single double word initialization sequence except that it contains a double word count that allows multiple sequential double words to be initialized in one configuration block.

  • Page 69: Figure 6.4 Configuration Done Sequence Format

    IDT SMBus Interfaces Notes The final type of configuration block is the configuration done sequence which is used to signify the end of a serial EEPROM initialization sequence. If during serial EEPROM initialization, an attempt is made to initialize a register that is not defined in a configuration space (i.e., does not appear in Table 9.5 in trans- parent mode or in Tables 10.6, 10.7, 10.7 in non-transparent mode), then the Unmapped Register Initializa-...

  • Page 70: Slave Smbus Interface

    IDT SMBus Interfaces Notes Error Action Taken Configuration Done Sequence checksum - Set RSTHALT bit in PA_SWCTL register mismatch with that computed by the - ICSERR bit is set in the PA_SMBUSSTS register PES16NT2 - Abort initialization, set DONE bit in the PA_SMBUSSTS register...

  • Page 71: Initialization

    IDT SMBus Interfaces Initialization Notes Slave SMBus initialization occurs during a fundamental reset (see section Fundamental Reset on page 2-7). During the fundamental reset initialization sequence, the address is specified by the SSMBADDR[5,3:1] signals as shown in Table 6.7. Address...

  • Page 72: Table 6.8 Slave Smbus Command Code Fields

    IDT SMBus Interfaces Notes Name Description Field End of transaction indicator. Setting both START and END signifies a single transaction sequence 0 - Current transaction is not the last read or write sequence. 1 - Current transaction is the last read or write sequence.

  • Page 73: Table 6.9 Csr Register Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Byte Field Position Name Description CCODE Command Code. Slave Command Code field described in Table 6.8. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses do not contain this field.

  • Page 74: Table 6.11 Serial Eeprom Read Or Write Operation Byte Sequence

    IDT SMBus Interfaces Notes Name Type Description Field Read/Write CSR Operation. This field encodes the CSR operation to be per- formed. 0 - CSR write 1 - CSR read Reserved. Must be zero RERR Read-Only Read Error. This bit is set if the last CSR read SMBus transaction was and Clear not claimed by a device.

  • Page 75: Table 6.12 Serial Eeprom Read Or Write Cmd Field Description

    IDT SMBus Interfaces Notes Name Type Description Field Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address. When this bit is set the serial EEPROM SMBus address specified in the EEADDR is used instead of that specified in the MSMBADDR field in the SMBUSSTS register.

  • Page 76: Figure 6.9 Serial Eeprom Read Using Smbus Block Write/Read Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES16NT2 Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU PES16NT2 Slave CCODE (PES16NT2 not ready with data) SMBus Address START,END PES16NT2 Slave CCODE PES16NT2 Slave BYTCNT=5 CMD (status) EEADDR SMBus Address START,END SMBus Address...

  • Page 77: Figure 6.13 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled

    IDT SMBus Interfaces Notes PES16NT2 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES16NT2 Slave CCODE ADDRU SMBus Address END, Byte PES16NT2 Slave CCODE (PES16NT2 not ready with data) SMBus Address START,Word PES16NT2 Slave CCODE SMBus Address START,Word PES16NT2 Slave...
  • Page 78 IDT SMBus Interfaces Notes PES16NT2 User Manual 6 - 16 April 15, 2008...

  • Page 79: Ntb Upstream Port Failover

    Chapter 7 NTB Upstream Port Failover ® Introduction Notes The PES16NT2 supports an NTB upstream port failover mechanism that enables the construction of fault tolerant systems. The NTB upstream port failover usage model is illustrated in Figure 7.1. In this usage there is a primary root and a secondary root.

  • Page 80: Failover

    IDT NTB Upstream Port Failover Notes Port A Port C PES16NT2 SerDes Switch Internal Port A Internal Port C (Upstream Port) (NTB Port) External Type 0 Configuration Header PES16NT2 Switch Non-Transparent Logic Bridge Internal Type 0 Configuration Header Type 1...

  • Page 81: Static Upstream Port Failover

    IDT NTB Upstream Port Failover Notes When a dynamic failover occurs, upstream and NTB port data queued in the switch, data being trans- mitted, and data in the replay buffers may be lost. Thus, some interruption of PCIe traffic should be expected with a failover.
  • Page 82 IDT NTB Upstream Port Failover Notes The following sections describe the manner in which a dynamic upstream port failover may be initiated. Software Initiated Failover A failover may be initiated by modifying the state of the NTB Upstream Port Failover Mode Select (FOVRMSEL) field in the Failover Control (FOVRCTL) register.
  • Page 83 IDT NTB Upstream Port Failover Notes PES16NT2 User Manual 7 - 5 April 15, 2008...
  • Page 84 IDT NTB Upstream Port Failover Notes PES16NT2 User Manual 7 - 6 April 15, 2008...

  • Page 85: General Purpose I/O

    Chapter 8 General Purpose I/O ® Introduction Notes The PES16NT2 has eight General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Control and Status (GPIOCS) register located in upstream port A’s PCI configuration space (see Table 8.1).

  • Page 86: Gpio Configuration

    IDT General Purpose I/O Notes Alternate Alternate GPIO Function Alternate Function Description Function Pin Name Pin Type PECRSTN Reset output for downstream port C Output PALINKUPN Port A link up status output Output PCLINKUPN Port C link up status output...

  • Page 87: Transparent Mode Operation

    Chapter 9 Transparent Mode Operation ® Introduction Notes This chapter discusses the operation of Port A. The following chapter, Chapter 11, discusses Port C which is configured as a non-transparent port. When the PES16NT2 is configured during a fundamental reset to operate in transparent mode or transparent mode with serial EEPROM initialization, the device functionally operates as illustrated in Figure 9.1.

  • Page 88: Interrupts

    IDT Transparent Mode Operation End-to-End CRC Notes PCIe® defines an optional end-to-end CRC associated with TLPs. The PES16NT2 fully supports ECRC for all TLPs that pass through the switch except for transactions utilizing gathered and routed to root complex implicit routing. For transactions received with this routing type, the ECRC is discarded and not checked and the resulting gathered message is generated without an ECRC.

  • Page 89: Table 9.3 Transaction Layer Errors

    IDT Transparent Mode Operation Notes PCIe Base 1.0a Error Condition Action Taken Specification Section Replay time-out 3.5.2.1 Correctable error processing REPLAY NUM rollover 3.5.2.1 Correctable error processing Violation of flow control initialization pro- 3.3.1 Uncorrectable error processing tocol Sequence number specified by 3.5.2.1...

  • Page 90: Table 9.4 Malformed Tlp Error Checks

    IDT Transparent Mode Operation Notes TLP Type Error Check LENGTH < Max_Payload_Size (i.e., MPS field in PCIEDCTL register) I/O read request LENGTH = 1 (doubleword) TC = 0, ATTR = 0 The actual packet length is correct (4 doublewords when CRC is present, 3doublewords otherwise)

  • Page 91: Configuration Requests

    IDT Transparent Mode Operation Notes TLP Type Error Check Completion with data The packet length is correct. - Number of doublewords received equals LENGTH + 3 when a packet does not contain ECRC - Number of doublewords received equals LENGTH + 4 when ECRC is present...

  • Page 92: Pci Express Capability Structure

    IDT Transparent Mode Operation Notes 0x000 Type 1 Configuration Header 0x040 PCI Express Capability Structure 0x070 PCI Power Management Capability Structure Configuration Space (64 DWords) 0x0A0 Switch Control & Status Registers *** Port A Only *** 0x0F4 Extended Cfg. Access &...

  • Page 93: Table 9.5 Upstream Port A Configuration Space Registers

    IDT Transparent Mode Operation Upstream Port A Configuration Space Registers Notes All configuration space locations not listed in Table 9.5 return a value of zero when read. Writes to these locations are ignored and have no side-effects. Port A configuration space registers may be read and written via the slave SMBus interface and initialized from the serial EEPROM using the CSR system address formed by adding the base address 0x0000 to the PCI configuration space offset address.
  • Page 94 IDT Transparent Mode Operation Notes Cfg. Register Size Register Definition Offset Mnemonic 0x032 Word PA_IOLIMITU PA_IOLIMITU - I/O Limit Upper (0x032) on page 9-17 0x034 Byte PA_CAPPTR PA_CAPPTR - Capabilities Pointer (0x034) on page 9-17 0x038 DWord PA_EROMBASE PA_EROMBASE - Expansion ROM Base Address (0x038) on...
  • Page 95 Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit ven- dor ID value assigned to IDT. See section Vendor ID on page 1-4. PA_DID - Device Identification (0x002) Field Default Type Description Field Name...
  • Page 96 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value Bus Master Enable. When this bit is cleared, the bridge does not issue requests (e.g., memory, I/O and MSIs since they are in-band writes) on behalf of subordinate devices and responds to non-posted transactions with a Unsup- ported Request (UR) completion.
  • Page 97 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value CAPL Capabilities List. This bit is hardwired to one to indicate that the bridge implements an extended capability list item. C66MHZ 66 MHz Capable. Not applicable. Reserved Reserved field.
  • Page 98 IDT Transparent Mode Operation Notes PA_CCODE - Class Code (0x009) Field Default Type Description Field Name Value INTF 0x00 Interface. This value indicates that the device is a PCI- PCI bridge that does not support subtractive decode. 15:8 0x04 Sub Class Code. This value indicates that the device is a PCI-PCI bridge.
  • Page 99 IDT Transparent Mode Operation Notes PA_BAR0 - Base Address Register 0 (0x010) Field Default Type Description Field Name Value 31:0 Base Address Register. Not applicable. PA_BAR1 - Base Address Register 1 (0x014) Field Default Type Description Field Name Value 31:0 Base Address Register.
  • Page 100 IDT Transparent Mode Operation Notes PA_IOBASE - I/O Base (0x01C) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32- bit I/O addressing. 0x0 - (io16) 16-bit I/O addressing. 0x1 - (io32) 32-bit I/O addressing.
  • Page 101 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value RW1C Signalled System Error. This bit is controlled by the SERR enable bit in the Bridge Control (BCTRL) register. If the SERRE bit is cleared in BCTRL, then this bit is never set.
  • Page 102 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value Reserved Reserved field. 15:4 PMBASE 0xFFF Prefetchable Memory Address Base. The PMBASE, PMBASEU, PMLIMIT and PMLIMITU registers are used to control the forwarding of prefetchable transactions between the primary and secondary interfaces of the bridge.
  • Page 103 IDT Transparent Mode Operation Notes PA_IOBASEU - I/O Base Upper (0x030) Field Default Type Description Field Name Value 15:0 IOBASEU 0xFFFF I/O Address Base Upper. This field specifies the upper 16-bits of IOBASE. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 104 IDT Transparent Mode Operation Notes PA_INTRPIN - Interrupt PIN (0x03D) Field Default Type Description Field Name Value INTRPIN Interrupt Pin. Interrupt pin or legacy interrupt messages are not used by the bridge. This field should only be configured with values of 0x0 through 0x4.
  • Page 105 IDT Transparent Mode Operation PCI Express Capability Structure Notes PA_PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure. 15:8...
  • Page 106 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value Attention Indicator Present. When set, this bit indicates that an Attention Indicator is implemented on the card/mod- ule. This bit should not be set on downstream ports. Power Indicator Present. When set, this bit indicates that a Power Indicator is implemented on the card/module.
  • Page 107 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value Max Payload Size. This field sets maximum TLP payload size for the device. 0x0 - (s128) 128 bytes max payload size 0x1 - (s256) 256 bytes max payload size...
  • Page 108 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value AUXPD Aux Power Detected. Devices that require AUX power, set this bit when AUX power is detected.This device does not require AUX power, hence the value is hardwired to zero.
  • Page 109 IDT Transparent Mode Operation Notes PA_PCIELCTL - PCI Express Link Control (0x050) Field Default Type Description Field Name Value ASPM Active State Power Management (ASPM) Control. This field controls the level of ASPM supported by the link. The initial value corresponds to disabled. The value contained...
  • Page 110 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value SCLK HWINIT Slot Clock Configuration. When set, this bit indicates that the component uses the same physical reference clock that the platform provides. The initial value of this field is the state of the CCLKUS signal for port A and the CCLKDS signal for downstream port C.
  • Page 111 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:19 PSLOTNUM Physical Slot Number. This field indicates the physical slot number attached to this port. For devices intercon- nected on the system board, this field should be initialized to zero.

  • Page 112: Power Management Capability Structure

    IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value Electromechanical Interlock Status. Hot-plug is not sup- ported. 15:8 Reserved Reserved field. Power Management Capability Structure PA_PMCAP - PCI Power Management Capabilities (0x070) Field Default Type Description Field...
  • Page 113 IDT Transparent Mode Operation Notes PA_PMCSR - PCI Power Management Control and Status (0x074) Field Default Type Description Field Name Value PSTATE Power State. This field is used to determine the current power state and to set a new power state.
  • Page 114 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value 27:16 L0ET 0x6D6 L0s Entry Timer. This field specifies the L0s entry time value for the related port transmitter. If all L0s entry condi- tions are met for the specified amount of time, then the transmitter port enters L0s.
  • Page 115 IDT Transparent Mode Operation Notes Mode2 Field Default Type Description Field Name Value PMCS 0x3F Values for PM current state. This field denotes the cur- rent value of the internal PM State Machine. Note that the SMBus is generally used to read this field rather than Con- figuration Reads.

  • Page 116: Switch Control And Status Registers

    IDT Transparent Mode Operation Switch Control and Status Registers Notes PA_SWSTS Switch Status (0x0A0) Field Default Type Description Field Name Value SWMODE HWINIT Switch Mode. The value of this field encodes the switch mode sampled on the Switch Mode (SWMODE[3:0]) sig- nals when exiting reset.
  • Page 117 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value INTB INTB Aggregated State. Aggregated switch state for INTB. 0x0 - (negated) INTB negated 0x1 - (asserted) INTB asserted INTC INTC Aggregated State. Aggregated switch state for INTC.
  • Page 118 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value PALREV HWINIT Port A Lane Reversal. When this bit is set, the lanes asso- ciated with port A are reversed. The initial value of this reg- ister corresponds to the state of the PALREV pin. However, this value may be overridden by the serial EEPROM, SMBus, or PCIe configuration write.
  • Page 119 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value 23:16 GPIOD HWINIT GPIO Data. Each bit in this field controls the corresponding Sticky GPIO pin. Reading this field returns the current value of each GPIO pin regardless of GPIO pin mode (i.e., alternate function or GPIO pin).
  • Page 120 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:30 Reserved Reserved field. PA_SMBUSCTL - SMBus Control (0x0B0) Field Default Type Description Field Name Value 15:0 MSMBCP HWINIT Master SMBus Clock Prescalar. This field contains a clock prescalar value used during master SMBus transac- tions.
  • Page 121 IDT Transparent Mode Operation Notes The MSMBCLK low minimum pulse width is equal to half the period programmed in this field. The value of 0x53, which corre- sponds to~373 KHz, allows the min low pulse width to be satisfied. In systems where this timing parameter is not critical, the op- erating frequency may be increased.

  • Page 122: Extended Configuration Space Access And Intx Status Registers

    IDT Transparent Mode Operation Extended Configuration Space Access and INTx Status Registers Notes PA_INTSTS - Interrupt Status (0x0F4) Field Default Type Description Field Name Value INTA INTA Aggregated State. Aggregated port state for INTA. 0x0 - (negated) INTA negated 0x1 - (asserted) INTA asserted INTB INTB Aggregated State.

  • Page 123: Pci Express Virtual Channel Capability

    IDT Transparent Mode Operation Notes PA_ECFGDATA - Extended Configuration Space Access Data (0x0FC) Field Default Type Description Field Name Value 31:0 DATA Configuration Data. A read from this field will return the configuration space register value pointed to by the ECF- GADDR register.
  • Page 124 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:12 Reserved Reserved field. PA_VCR0CAP- VC Resource 0 Capability (0x110) Field Default Type Description Field Name Value PARBC Port Arbitration Capability. This field indicates the type of port arbitration supported by the VC. Each bit corresponds to a Port Arbitration capability.
  • Page 125 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value LPAT Load Port Arbitration Table. This bit, when set, updates the Port Arbitration logic from the Port Arbitration Table for the VC resource. In addition, this field is only valid when...
  • Page 126 IDT Transparent Mode Operation Notes PA_VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120) Field Default Type Description Field Name Value PHASE0 Phase 0. This field contains the port ID for the correspond- ing port arbitration period. Selecting an invalid port ID results in the entry being skipped without delay.
  • Page 127 IDT Transparent Mode Operation Notes PA_VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124) Field Default Type Description Field Name Value PHASE16 Phase 16. This field contains the port ID for the corre- sponding port arbitration period. Selecting an invalid port ID results in the entry being skipped without delay.
  • Page 128 IDT Transparent Mode Operation Physical Layer Control and Status Registers Notes PA_SERDESCTL - SerDes Control (0x200) Field Default Type Description Field Name Value TXEQL Transmit Driver Equalization Level. This field controls the SerDes transmit driver equalization. 0x0 - (de000) de-emphasis of 0.00 dB 0x1 - (de035) de-emphasis of -0.35 dB...
  • Page 129 IDT Transparent Mode Operation Notes Field Default Type Description Field Name Value 13:12 RXTERM Receiver Termination Adjustment. This field controls the SerDes receiver termination value. 0x0 - (nom) nominal transmit termination value of 50 ohms 0x1 -(m17) termination value of nominal - 17%...
  • Page 130 IDT Transparent Mode Operation Notes PES16NT2 User Manual 9 - 44 April 15, 2008...

  • Page 131: Non-Transparent Mode Operation

    Chapter 10 Non-Transparent Mode Operation ® Introduction Notes The PCIe® architectural model is one in which a root, typically the main CPU, is responsible for config- uring a tree of endpoints (i.e., a hierarchy of virtual PCI buses). Once configured, any endpoint or root may “initiate transactions.

  • Page 132: Figure 10.1 Pes16Nt2 Functional Block Diagram In Non-Transparent Mode

    IDT Non-Transparent Mode Operation Notes Port A (Upstream Port) Type 1 Configuration Header PCI-PCI Transparent Bridge Virtual PCI Bus Type 1 Configuration Header PCI-PCI Transparent PCI Express Link Bridge Capabilities, Control, Status & Virtual PCI Express Slot PCIe Link Capabilities, Control, Status...

  • Page 133: Transaction Routing

    IDT Non-Transparent Mode Operation Notes Following configuration of the non-transparent bridge complex, the non-transparent bridge will appear as a PCI-PCI bridge followed by an endpoint on the internal side and an endpoint on the external side. Therefore, once configured the operation of the non-transparent bridge should be transparent to system software and drivers.

  • Page 134: Table 10.1 Non-Transparent Bridge Mapping Table Fields

    IDT Non-Transparent Mode Operation Notes Description Field Name When set, this field indicates if the table entry is valid. 18:16 FUNC This field contains the mapping table entry function number. 23:19 This field contains the mapping table entry device number.

  • Page 135: Figure 10.3 Ntb Base And Limit Address Translation

    IDT Non-Transparent Mode Operation Notes Transaction Address Base Address Offset Address Translated Base Address BARTBASEx Unsupported Translated Limit Address > Request BARTLIMITx Translated Transaction Address (Offset Address + BARTBASEx) > BARTLIMITx Figure 10.3 NTB Base and Limit Address Translation A base and limit address translation mechanism is employed to translate the address of transactions that flow through the NTB.

  • Page 136: Id Routing

    IDT Non-Transparent Mode Operation Notes Treating a transaction as an unsupported request means setting the appropriate status bits and, if enabled, generating an error message. If the transaction was a non-posted, this also means generating a completion with status UR. See the PCIe base specification for details.

  • Page 137: Gather And Route To Root Implicit Routing

    IDT Non-Transparent Mode Operation Gather and Route to Root Implicit Routing Notes Gather and route to root implicit routing is not supported through the non-transparent bridge and are discarded. Non-Transparent Bridge Interprocessor Communica- tions The Non-Transparent Bridge Communications Capability Structure has a number of facilities to aid in interprocessor communications between processors on opposite sides of the NTB.

  • Page 138: Doorbell Registers

    IDT Non-Transparent Mode Operation Doorbell Registers Notes The internal and external endpoints each have an Inbound Doorbell (INDBELL) and Outbound Doorbell (OUTDBELL) register. The OUTDBELL register may be read and written while INDBELL register is read and cleared. The doorbell registers provide 32 doorbells in each direction through the non-transparent bridge.

  • Page 139: Non-Transparent Bridge Tlp Processing

    IDT Non-Transparent Mode Operation Notes transparent bridge endpoint generates a single MSI message for all interrupt sources and this message is only generated when a falling edge would have occurred on a legacy PCI INTx# pin that corresponds to the MSI request value.

  • Page 140: Configuration Space

    IDT Non-Transparent Mode Operation Configuration Space Notes Associated with the internal and external NTB endpoints is a 4 KB PCIe configuration space containing a Type 0 header. The organization of these configuration spaces is described in section NTB Endpoint Configuration Space Organization on page 10-55. The NTB configuration spaces are symmetric, meaning that the same fields are located in the locations on both sides of the NTB.

  • Page 141: Memory Mapped Configuration Space

    IDT Non-Transparent Mode Operation Memory Mapped Configuration Space Notes In PCIe only the root may perform configuration space read and write operations. Since the interpro- cessor communication facilities are mapped into configuration space, it is desirable to provide a means for any PCIe master to access configuration space.

  • Page 142: End-To-End Crc

    IDT Non-Transparent Mode Operation Notes Configuration accesses to different entities within the PES16NT2 may complete out-of-order and may limit the utility of multiple outstanding PCIe configuration accesses. For example, a configuration access that modifies a secondary or subordinate bus number which is immediately followed by a Type 1 configura- tion access that relies on the modified value for routing may result in an error when issued concurrently, but execute properly when issued in sequence.

  • Page 143: Table 10.3 Data Link Layer Errors

    IDT Non-Transparent Mode Operation Notes PCIe Base 1.0a Error Condition Action Taken Specification Section TLP ending in ENDB with LCRC that does not 3.5.3.1 TLP discarded match inverted calculated LCRC TLP received with incorrect LCRC 3.5.3.1 Correctable error processing TLP received with sequence number not 3.5.3.1...

  • Page 144: Table 10.5 Malformed Tlp Error Checks

    IDT Non-Transparent Mode Operation Notes Table 10.5 lists the error checks performed by the transaction layer for malformed TLPs. TLP error checks are only performed when a TLP is received by the switch (i.e., by the stack associated with the port on which the switch receives the TLP). No checks are made for malformed TLPs inside the switch.

  • Page 145: Power Management

    IDT Non-Transparent Mode Operation Notes TLP Type Error Check Memory write request (32- and 64-bit address The packet length is correct. mode) 32-bit address mode: - Number of doublewords received equals LENGTH + 4 when ECRC is present - Number of doublewords received equals...

  • Page 146: Initializing The Non-Transparent Bridge

    IDT Non-Transparent Mode Operation Notes When an NTB endpoint’s PSTATE field is set to D3 , the endpoint does not initiate bus transactions (i.e., transactions destined to that side of the NTB are dropped) and does not respond to transactions other than PCIe configuration transactions.
  • Page 147 IDT Non-Transparent Mode Operation Notes For I/O transactions to be routed from the external port C link to the internal virtual PCI bus of the switch the following configuration should be performed. – The I/O Access Enable (IOAE) bit should be set in the PCEE_PCICMD register to enable the external endpoint of the non-transparent bridge to forward I/O transactions into the switch.

  • Page 148: Non-Transparent Port C Configuration Space Organization

    IDT Non-Transparent Mode Operation Non-Transparent Port C Configuration Space Organiza- Notes tion The organization of port C configuration space is shown in Figure 10.6. 0x000 Type 1 Configuration Header 0x040 PCI Express Capability Structure 0x070 PCI Power Management Capability Structure...

  • Page 149: Table 10.6 Downstream Port C Configuration Space Registers In Non-Transparent Mode

    IDT Non-Transparent Mode Operation Non-Transparent Mode Downstream Port C Configura- Notes tion Space Organization Registers All configuration space locations not listed in Table 10.6 return a value of zero when read. Writes to these locations are ignored and have no side-effects.Port C configuration space registers may be read and written via the slave SMBus interface and initialized from the serial EEPROM using the CSR system address formed by adding the base address 0x1000 to the PCI configuration space offset address.
  • Page 150 IDT Non-Transparent Mode Operation Notes Cfg. Register Size Register Definition Offset Mnemonic 0x032 Word PC_IOLIMITU PC_IOLIMITU - I/O Limit Upper (0x032) on page 10-29 0x034 Byte PC_CAPPTR PC_CAPPTR - Capabilities Pointer (0x034) on page 10-29 0x038 DWord PC_EROMBASE PC_EROMBASE - Expansion ROM Base Address (0x038) on page...

  • Page 151: Port C Registers

    Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit ven- dor ID value assigned to IDT. See section Vendor ID on page 1-4. PC_DID - Device Identification (0x002) Field Default Type Description Field Name...
  • Page 152 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value Bus Master Enable. When this bit is cleared, the bridge does not issue requests (e.g., memory, I/O and MSIs since they are in-band writes) on behalf of subordinate devices and responds to non-posted transactions with a Unsup- ported Request (UR) completion.
  • Page 153 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value CAPL Capabilities List. This bit is hardwired to one to indicate that the bridge implements an extended capability list item. C66MHZ 66 MHz Capable. Not applicable. Reserved Reserved field.
  • Page 154 IDT Non-Transparent Mode Operation Notes PC_CCODE - Class Code (0x009) Field Default Type Description Field Name Value INTF 0x00 Interface. This value indicates that the device is a PCI- PCI bridge that does not support subtractive decode. 15:8 0x04 Sub Class Code. This value indicates that the device is a PCI-PCI bridge.
  • Page 155 IDT Non-Transparent Mode Operation Notes PC_BAR0 - Base Address Register 0 (0x010) Field Default Type Description Field Name Value 31:0 Base Address Register. Not applicable. PC_BAR1 - Base Address Register 1 (0x014) Field Default Type Description Field Name Value 31:0 Base Address Register.
  • Page 156 IDT Non-Transparent Mode Operation Notes PC_IOBASE - I/O Base (0x01C) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32- bit I/O addressing. 0x0 -(io16) 16-bit I/O addressing. 0x1 - (io32) 32-bit I/O addressing.
  • Page 157 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value RW1C Signalled System Error. This bit is controlled by the SERR enable bit in the Bridge Control (BCTRL) register. If the SERRE bit is cleared in BCTRL, then this bit is never set.
  • Page 158 IDT Non-Transparent Mode Operation Notes PC_PMBASE - Prefetchable Memory Base (0x024) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. 0x0 -(prefmem32) 32-bit prefetchable memory addressing. 0x1 - (prefmem64) 64-bit prefetchable memory addressing.
  • Page 159 IDT Non-Transparent Mode Operation Notes PC_PMLIMITU - Prefetchable Memory Limit Upper (0x02C) Field Default Type Description Field Name Value 31:0 PMLIMITU Prefetchable Memory Address Limit Upper. This field specifies the upper 32-bits of PMLIMIT. When the PMCAP field in the PMBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 160 IDT Non-Transparent Mode Operation Notes PC_INTRLINE - Interrupt Line (0x03C) Field Default Type Description Field Name Value INTRLINE Interrupt Line. This register communicates interrupt line routing information. Values in this register are programmed by system software and are system architecture specific.

  • Page 161: Pci Express Capability Structure

    IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SRESET Secondary Bus Reset. Setting this bit triggers a hot reset down the secondary interface of the bridge. 15:7 Reserved Reserved field. PCI Express Capability Structure PC_PCIECAP - PCI Express Capability (0x040)
  • Page 162 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value E0AL Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to transition from the L0s state to the L0 state. The value is hardwired to 0x0 as this field does not apply to a switch.
  • Page 163 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value URREN Unsupported Request Reporting Enable. This bit con- trols reporting of unsupported requests. Enable Relaxed Ordering. When set, this bit enables relaxed ordering. The switch never sets the relaxed order- ing bit in transactions it initiates as a requester.
  • Page 164 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value RW1C Fatal Error Detected. This bit indicates the status of Fatal errors. Errors are logged in this registers regardless of whether error reporting is enabled or not. RW1C Unsupported Request Detected.
  • Page 165 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 17:15 L1EL see text L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express link. This field is affected by the deep L1 and D3 disable bits (i.e., DEEPD3DIS and DEEPL1DIS).
  • Page 166 IDT Non-Transparent Mode Operation Notes PC_PCIELSTS - Port C NTB Mode PCI Express Link Status (0x052) Field Default Type Description Field Name Value Link Speed. This field is hardwired to 2.5 Gbps. HWINIT Link Width. This field indicates the negotiated width of the link.
  • Page 167 IDT Non-Transparent Mode Operation Notes PC_PCIESCTL - Port C NTB Mode PCI Express Slot Control (0x058) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable. Hot-plug is not sup- ported. PFDE Power Fault Detected Enable. Hot-plug is not supported.

  • Page 168: Power Management Capability Structure

    IDT Non-Transparent Mode Operation Power Management Capability Structure Notes PC_PMCAP - PCI Power Management Capabilities (0x070) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0x1 identifies this capability as a PCI power management capability structure.
  • Page 169 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 12:9 DSEL Data Select. The optional data register is not implemented. 14:13 DSCALE Data Scale. The optional data register is not implemented. PMES RW1C PME Status. This bit is set if a PME is generated by the Sticky port even if the PMEE bit is cleared.
  • Page 170 IDT Non-Transparent Mode Operation Notes Mode2 Field Default Type Description Field Name Value PMCS 0x3F Values for PM current state. This field denotes the cur- rent value of the internal PM State Machine. Note that the SMBus is generally used to read this field rather than Con- figuration Reads.

  • Page 171: Switch Control And Status Registers

    IDT Non-Transparent Mode Operation Switch Control and Status Registers Notes PC_SWSTS Switch Status (0x0A0) Field Default Type Description Field Name Value SWMODE HWINIT Switch Mode. The value of this field encodes the switch mode sampled on the Switch Mode (SWMODE[3:0]) sig- nals when exiting reset.
  • Page 172 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value INTB INTB Aggregated State. Aggregated switch state for INTB. 0x0 - (negated) INTB negated 0x1 - (asserted) INTB asserted INTC INTC Aggregated State. Aggregated switch state for INTC.
  • Page 173 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value PALREV HWINIT Port A Lane Reversal. When this bit is set, the lanes asso- ciated with port A are reversed. The initial value of this reg- ister corresponds to the state of the PALREV pin. However, this value may be overridden by the serial EEPROM, SMBus, or PCIe configuration write.
  • Page 174 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 23:16 GPIOD HWINIT GPIO Data. Each bit in this field controls the corresponding Sticky GPIO pin. Reading this field returns the current value of each GPIO pin regardless of GPIO pin mode (i.e., alternate function or GPIO pin).
  • Page 175 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value URIA RW1C Unmapped Register Initialization Attempt. This bit is set if an attempt is made to initialize via serial EEPROM a reg- ister that is not defined in the corresponding PCI configura- tion space.
  • Page 176 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 21:20 MSMBMODE Master SMBus Mode. The master SMBus contains inter- nal glitch counters on the MSMBCLK and MSMBDAT sig- nals that wait approximately 1 µS before sampling or driving these signals.

  • Page 177: Extended Configuration Space Access And Intx Status Registers

    IDT Non-Transparent Mode Operation Extended Configuration Space Access and INTx Status Registers Notes PC_INTSTS - Interrupt Status (0x0F4) Field Default Type Description Field Name Value INTA INTA Aggregated State. Aggregated port state for INTA. 0x0 - (negated) INTA negated 0x1 - (asserted) INTA asserted INTB INTB Aggregated State.

  • Page 178: Pci Express Virtual Channel Capability

    IDT Non-Transparent Mode Operation Notes PC_ECFGDATA - Extended Configuration Space Access Data (0x0FC) Field Default Type Description Field Name Value 31:0 DATA Configuration Data. A read from this field will return the configuration space register value pointed to by the ECF- GADDR register.
  • Page 179 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:12 Reserved Reserved field. PC_VCR0CAP- VC Resource 0 Capability (0x110) Field Default Type Description Field Name Value PARBC Port Arbitration Capability. This field indicates the type of port arbitration supported by the VC. Each bit corresponds to a Port Arbitration capability.
  • Page 180 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value LPAT Load Port Arbitration Table. This bit, when set, updates the Port Arbitration logic from the Port Arbitration Table for the VC resource. In addition, this field is only valid when...
  • Page 181 IDT Non-Transparent Mode Operation Notes PC_VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120) Field Default Type Description Field Name Value PHASE0 Phase 0. This field contains the port ID for the correspond- ing port arbitration period. Selecting an invalid port ID results in the entry being skipped without delay.
  • Page 182 IDT Non-Transparent Mode Operation Notes PC_VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124) Field Default Type Description Field Name Value PHASE16 Phase 16. This field contains the port ID for the corre- sponding port arbitration period. Selecting an invalid port ID results in the entry being skipped without delay.

  • Page 183: Physical Layer Control And Status Registers

    IDT Non-Transparent Mode Operation Physical Layer Control and Status Registers Notes PC_SERDESCTL - SerDes Control (0x200) Field Default Type Description Field Name Value TXEQL Transmit Driver Equalization Level. This field controls the SerDes transmit driver equalization. 0x0 - (de000) de-emphasis of 0.00 dB 0x1 - (de035) de-emphasis of -0.35 dB...
  • Page 184 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 13:12 RXTERM Receiver Termination Adjustment. This field controls the SerDes receiver termination value. 0x0 - (nom) nominal transmit termination value of 50 ohms 0x1 -(m17) termination value of nominal - 17%...

  • Page 185: Ntb Endpoint Configuration Space Organization

    IDT Non-Transparent Mode Operation NTB Endpoint Configuration Space Organization Notes 0x000 Type 0 Configuration Header 0x040 PCI Express Capability Structure 0x064 MSI Capability Structure 0x074 Configuration Space (64 DWords) Non-Transparent Bridge Configuration Capability Structure 0x0B4 Some Non-Transparent Bridge Non-Transparent Bridge...

  • Page 186: Table 10.7 Non-Transparent Bridge Internal Endpoint Configuration Space Registers

    IDT Non-Transparent Mode Operation NTB Internal Endpoint Configuration Space Registers Notes All configuration space locations not listed in Table 10.7 return a value of zero when read. Writes to these locations are ignored and have no side-effects. Non-transparent bridge internal endpoint configura- tion space registers may be read and written via the slave SMBus interface using the base address 0x3000 added to the PCI configuration space offset address of the register to be accessed.
  • Page 187 IDT Non-Transparent Mode Operation Notes Cfg. Register Size Register Definition Offset Mnemonic 0x04A Word PCIE_PCIEDSTS PCIE_PCIEDSTS - PCI Express Device Status (0x04A) on page 10-70 0x04C DWord PCIE_PCIELCAP PCIE_PCIELCAP - PCI Express Link Capabilities (0x04C) on page 10-71 0x050 Word...
  • Page 188 IDT Non-Transparent Mode Operation Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0AC DWord PCIE_MTADDR PCIE_MTADDR - Mapping Table Address (0x0AC) on page 10- 0x0B0 DWord PCIE_MTDATA PCIE_MTDATA - Mapping Table DATA (0x0B0) on page 10-88 0x0B4 DWord PCIE_NTBCOMC PCIE_NTBCOMC - Non-Transparent Bridge Communications...

  • Page 189: Non-Transparent Bridge Internal Endpoint Registers

    Type Description Field Name Value 15:0 — Device Identification. This field contains the 16-bit device ID assigned by IDT to this non-transparent bridge. See section Device ID on page 1-4. PCIE_PCICMD - PCI Command (0x004) Field Default Type Description Field...
  • Page 190 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value Memory Access Enable. When this bit is cleared, the non- transparent bridge does not respond to memory space access. 0x0 -(disable) Disable memory space. 0x1 - (enable) Enable memory space.
  • Page 191 IDT Non-Transparent Mode Operation Notes PCIE_PCISTS - PCI Status (0x006) Field Default Type Description Field Name Value Reserved Reserved field. INTS INTx Status. This bit is set when an INTx interrupt is pend- ing from the device. INTx emulation interrupts forwarded by switch ports from devices downstream of the bridge are not reflected in this bit.
  • Page 192 IDT Non-Transparent Mode Operation Notes PCIE_RID - Revision Identification (0x008) Field Default Type Description Field Name Value — Revision ID. This field contains the revision identification number for the device. See 17.4 “Revision ID” on page 17-2. PCIE_CCODE - Class Code (0x009)
  • Page 193 IDT Non-Transparent Mode Operation Notes PCIE_BIST - Built-on Self Test (0x00F) Field Default Type Description Field Name Value BIST BIST. This value indicates that the non-transparent bridge does not implement BIST. PCIE_BAR0 - Base Address Register 0 (0x010) Field Default...
  • Page 194 IDT Non-Transparent Mode Operation Notes PCIE_BAR1 - Base Address Register 1 (0x014) When the MEMSI field in BARSETUP0 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR1 takes on the function of the upper 32-bits of the BADDR field in BAR0. Otherwise, the BAR format below is used.
  • Page 195 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value TYPE — Address Type. When the MEMSI field indicates memory space, this field specifies if a 32-bit or 64-bit address for- mat is used. The value of this field is determined by the TYPE field in the BARSETUP2 register.
  • Page 196 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value TYPE — Address Type. When the MEMSI field indicates memory space, this field specifies if a 32-bit or 64-bit address for- mat is used. Since this is an odd-numbered BAR, it can only be config- ured for a 32-bit address format.
  • Page 197 IDT Non-Transparent Mode Operation Notes PCIE_SUBVID - Subsystem Vendor ID Pointer (0x02C) Field Default Type Description Field Name Value 15:0 SUBVID Subsystem Vendor ID. This field identifies the vendor of the subsystem. PCIE_SUBID - Subsystem ID Pointer (0x02E) Field Default...

  • Page 198: Pci Express Capability Structure

    IDT Non-Transparent Mode Operation Notes PCIE_MAXLAT - Maximum Latency (0x03F) Field Default Type Description Field Name Value MAXLAT Maximum Latency. Not applicable. PCI Express Capability Structure PCIE_PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID.
  • Page 199 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value E0AL Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to transition from the L0s state to the L0 state. The value is hardwired to 0x3 to indicate more than 4 us.
  • Page 200 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value Max Payload Size. This field sets maximum TLP payload size for the device. 0x0 - (s128) 128 bytes max payload size 0x1 - (s256) 256 bytes max payload size...
  • Page 201 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value RW1C Unsupported Request Detected. This bit indicates the device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not.

  • Page 202: Message Signaled Interrupt Capability Structure

    IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value CCLK Common Clock Configuration. Not applicable for “virtual” links. ESYNC Extended Sync. Not applicable for “virtual” links. 15:8 Reserved Reserved field. PCIE_PCIELSTS - PCI Express Link Status (0x052)

  • Page 203: Non-Transparent Bridge Configuration Capability Structure

    IDT Non-Transparent Mode Operation Notes PCIE_MSIADDR - Message Signaled Interrupt Address (0x068) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction.
  • Page 204 Writes should never be performed to this field during nor- mal operation. 31:24 IDTCAP IDT Capability. This field defines an IDT proprietary PCI, PCI-X or PCI Express capability. The value of 0x1 identifies this as a non-transparent bridge configuration capability structure.
  • Page 205 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value OSCFGPROT Opposite Side Configuration Protection.When this bit is set, all configuration and BAR4 writes from the opposite side of the non-transparent bridge to the internal or exter- nal non-transparent bridge configuration capability struc- ture are ignored (i.e., they are completed normally but do...
  • Page 206 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value OSHRD RW1C Opposite Side Hot Reset Detected. This bit is set when a hot reset is detected on the opposite side of the non-trans- parent bridge. OSRIP Opposite Side Reset in Progress. This bit is set when a hot or fundamental reset is in progress on the opposite side of the non-transparent bridge.
  • Page 207 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 15:8 Bus Number. This field contains the bus number value of the last configuration write transaction to this configuration space of the non-transparent bridge. PCIE_BARSETUP0 - BAR 0 Setup (0x07C)
  • Page 208 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 209 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR0 of the non-transparent bridge. When 64-bit addressing is selected, the translated base...
  • Page 210 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 211 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR1 of the non-transparent bridge. Not reset by external fundamental reset or internal/external hot reset...
  • Page 212 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 213 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR2 of the non-transparent bridge. When 64-bit addressing is selected, the translated base...
  • Page 214 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 215 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR3 of the non-transparent bridge. When a transaction address is translated, the PCI address bits from bit 31 through the bit specified by the SIZE field are replaced by the corresponding bits in this field.
  • Page 216 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 14:12 FUNC Function Number. This field selects the function number as defined by Section 7.2.2 of the PCI Express Base Spec- ification, Rev. 1.0a 19:15 Device Number. This field selects the device number as defined by Section 7.2.2 of the PCI Express Base Specifi-...
  • Page 217 IDT Non-Transparent Mode Operation Notes PCIE_PTCSTS - Punch Through Configuration Status (0x0A8) Field Default Type Description Field Name Value BUSY Punch Through Configuration Interface Busy. This bit is set when a punch through configuration transaction is in progress. 0x0 - (idle) configuration transaction interface is idle...
  • Page 218 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value ADDR Mapping Table Address. This field contains the DWord address of a mapping table entry. 31:6 Reserved Reserved field. Not reset by external fundamental reset or internal/external hot reset...

  • Page 219: Non-Transparent Bridge Communications Capability Structure

    Capability Length. This field defines the length in bytes of the capability. It includes the VSID and NXTPTR fields. 31:24 IDTCAP IDT Capability. This field defines an IDT proprietary PCI, PCI-X or PCI Express capability. The value of 0x2 identifies this as a non-transparent bridge communications capability structure...
  • Page 220 IDT Non-Transparent Mode Operation Notes PCIE_SCRATCHPAD[0..1] - Scratchpad [0..1] (0x0D8-ODC) Field Default Type Description Field Name Value 31:0 SCRATCHPAD Scratchpad Value. This scratchpad register may be read and written from both sides of the non-transparent bridge. Scratchpad registers may not be accessed using the Extended Configuration Space Data (ECFGDATA) regis- ter.
  • Page 221 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value INMSG2 RW1C Inbound Message 2. This bit is set whenever a value is written to the OUTMSG2 register located in PCI configura- tion space on the opposite side of the non-transparent bridge.
  • Page 222 IDT Non-Transparent Mode Operation Notes PCIE_INTCTL0 - Interrupt Control 0 (0x0EC) Field Default Type Description Field Name Value INMSG0 Inbound Message 0 Configuration. This field encodes the action taken when the INMSG0 bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 223 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value INMSG2 Inbound Message 2 Configuration. This field encodes the action taken when the INMSG2 bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 224 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 14:12 INDBELL Inbound Doorbell Configuration. This field encodes the action taken when the INMSG1 bit in the INTSTS register is set, or cleared when INTx interrupt signalling is enabled.

  • Page 225: Power Management Capability Structure

    IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 20:18 OSPSTATEM Opposite Side Power State Modification Configuration. This field encodes the action taken when the OSPSTATEM bit in the INTSTS register is set, or cleared when INTx interrupt signalling is enabled.
  • Page 226 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value DEVSP Device Specific Initialization. The value of zero indicates that no device specific initialization is required. 24:22 AUXI AUX Current. not used D1 Support. This field indicates that the PES16NT2 does not support D1.

  • Page 227: Extended Configuration Space Access Registers

    IDT Non-Transparent Mode Operation Extended Configuration Space Access Registers Notes PCIE_ECFGADDR - Extended Configuration Space Access Address (0x0F8) Field Default Type Description Field Name Value Reserved Reserved field. Register Number. This field selects the configuration reg- ister number as defined by Section 7.2.2 of the PCI Express Base Specification, Rev.

  • Page 228: Non-Transparent Bridge Control And Status Registers

    IDT Non-Transparent Mode Operation Non-Transparent Bridge Control and Status Registers Notes PCIE_NTBCFG - Non-Transparent Bridge Configuration (0x200) Field Default Type Description Field Name Value 31:0 Reserved Reserved field. PCIE_INTCTL1 - Interrupt Control 1 (0x210) Field Default Type Description Field Name...
  • Page 229 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value PALINKDN Port A Link Down Configuration. This field encodes the action taken when the PALINKDN bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 230 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 11:9 PBLINKDN Port B Link Down Configuration. This field encodes the action taken when the PBLINKDN bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 231 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 17:15 PCLINKDN Port C Link Down Configuration. This field encodes the action taken when the PCLINKDN bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 232 IDT Non-Transparent Mode Operation Notes PCIE_TLPPCTL - TLP Processing Control (0x214) Field Default Type Description Field Name Value Force Relaxed Ordering. When this bit is set, all TLPs in Sticky which the relaxed attribute is applicable are modified as dictated by the Relaxed Ordering Modification (ROM) field in this register for TLPs flowing through the NTB from this side to the opposite side.
  • Page 233 IDT Non-Transparent Mode Operation Notes PCIE_BARTLIMIT1 - BAR 1 Translated Limit Address (0x21C) When the MEMSI field in BARSETUP0 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BARTLIMIT1 takes on the function of the upper 32-bits of the TLADDR field in BARTLIMIT0.

  • Page 234: Table 10.8 Non-Transparent Bridge External Endpoint Configuration Space Registers

    IDT Non-Transparent Mode Operation NTB External Endpoint Configuration Space Registers Notes All configuration space locations not listed in Table 10.8 return a value of zero when read. Writes to these locations are ignored and have no side-effects. Non-transparent bridge external endpoint configuration space registers may be read and written via the slave SMBus interface and initialized from the serial EEPROM using the CSR system address formed by adding the base address 0x3000 to the PCI configuration space offset address.
  • Page 235 IDT Non-Transparent Mode Operation Notes Cfg. Register Size Register Definition Offset Mnemonic 0x040 DWord PCEE_PCIECAP PCEE_PCIECAP - PCI Express Capability (0x040) on page 10- 0x044 DWord PCEE_PCIEDCAP PCEE_PCIEDCAP - PCI Express Device Capabilities (0x044) on page 10-116 0x048 Word PCEE_PCIEDCTL...
  • Page 236 IDT Non-Transparent Mode Operation Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0A0 DWord PCEE_PTCCFG PCEE_PTCCFG - Punch Through Configuration Control (0x0A0) on page 10-133 0x0A4 DWord PCEE_PTCDATA PCEE_PTCDATA - Punch Through Configuration Data (0x0A4) on page 10-134 0x0A8 DWord...

  • Page 237: Non-Transparent Bridge External Endpoint Registers

    Default Type Description Field Name Value 15:0 — Device Identification. This field contains the 16-bit device ID assigned by IDT to this non-transparent bridge. See section Device ID on page 1-4. PES16NT2 User Manual 10 - 107 April 15, 2008...
  • Page 238 IDT Non-Transparent Mode Operation Notes PCEE_PCICMD - PCI Command (0x004) Field Default Type Description Field Name Value IOAE I/O Access Enable. When this bit is cleared, the non- transparent bridge does not respond to I/O access. 0x0 -(disable) Disable I/O space.
  • Page 239 IDT Non-Transparent Mode Operation Notes PCEE_PCISTS - PCI Status (0x006) Field Default Type Description Field Name Value Reserved Reserved field. INTS INTx Status. This bit is set when an INTx interrupt is pend- ing from the device. INTx emulation interrupts forwarded by switch ports from devices downstream of the bridge are not reflected in this bit.
  • Page 240 IDT Non-Transparent Mode Operation Notes PCEE_RID - Revision Identification (0x008) Field Default Type Description Field Name Value — Revision ID. This field contains the revision identification number for the device. See 17.4 “Revision ID” on page 17-2. PCEE_CCODE - Class Code (0x009)
  • Page 241 IDT Non-Transparent Mode Operation Notes PCEE_BIST - Built-on Self Test (0x00F) Field Default Type Description Field Name Value BIST BIST. This value indicates that the non-transparent bridge does not implement BIST. PCEE_BAR0 - Base Address Register 0 (0x010) Field Default...
  • Page 242 IDT Non-Transparent Mode Operation Notes PCEE_BAR1 - Base Address Register 1 (0x014) When the MEMSI field in BARSETUP0 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BAR1 takes on the function of the upper 32-bits of the BADDR field in BAR0. Otherwise, the BAR format below is used.
  • Page 243 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value TYPE — Address Type. When the MEMSI field indicates memory space, this field specifies if a 32-bit or 64-bit address for- mat is used. The value of this field is determined by the TYPE field in the BARSETUP2 register.
  • Page 244 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value TYPE — Address Type. When the MEMSI field indicates memory space, this field specifies if a 32-bit or 64-bit address for- mat is used. Since this is an odd-numbered BAR, it can only be config- ured for a 32-bit address format.
  • Page 245 IDT Non-Transparent Mode Operation Notes PCEE_SUBVID - Subsystem Vendor ID Pointer (0x02C) Field Default Type Description Field Name Value 15:0 SUBVID Subsystem Vendor ID. This field identifies the vendor of the subsystem. PCEE_SUBID - Subsystem ID Pointer (0x02E) Field Default...

  • Page 246: Pci Express Capability Structure

    IDT Non-Transparent Mode Operation Notes PCEE_MAXLAT - Maximum Latency (0x03F) Field Default Type Description Field Name Value MAXLAT Maximum Latency. Not applicable. PCI Express Capability Structure PCEE_PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID.
  • Page 247 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value E0AL Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to transition from the L0s state to the L0 state. The value is hardwired to 0x3 to indicate more than 4 us.
  • Page 248 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value Max Payload Size. This field sets maximum TLP payload size for the device. 0x0 - (s128) 128 bytes max payload size 0x1 - (s256) 256 bytes max payload size...
  • Page 249 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value RW1C Unsupported Request Detected. This bit indicates the device received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not.

  • Page 250: Message Signaled Interrupt Capability Structure

    IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value CCLK Common Clock Configuration. Not applicable for “virtual” links. ESYNC Extended Sync. Not applicable for “virtual” links. 15:8 Reserved Reserved field. PCEE_PCIELSTS - PCI Express Link Status (0x052)

  • Page 251: Non-Transparent Bridge Configuration Capability Structure

    IDT Non-Transparent Mode Operation Notes PCEE_MSIADDR - Message Signaled Interrupt Address (0x068) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction.
  • Page 252 Writes should never be performed to this field during nor- mal operation. 31:24 IDTCAP IDT Capability. This field defines an IDT proprietary PCI, PCI-X or PCI Express capability. The value of 0x1 identifies this as a non-transparent bridge configuration capability structure.
  • Page 253 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value OSCFGPROT Opposite Side Configuration Protection.When this bit is set, all configuration and BAR4 writes from the opposite side of the non-transparent bridge to the internal or exter- nal non-transparent bridge configuration capability struc- ture are ignored (i.e., they are completed normally but do...

  • Page 254: Table 1.1 Table

    IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value OSHRD RW1C Opposite Side Hot Reset Detected. This bit is set when a hot reset is detected on the opposite side of the non-trans- parent bridge. OSRIP Opposite Side Reset in Progress. This bit is set when a hot or fundamental reset is in progress on the opposite side of the non-transparent bridge.
  • Page 255 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 15:8 Bus Number. This field contains the bus number value of the last configuration write transaction to this configuration space of the non-transparent bridge. PCEE_BARSETUP0 - BAR 0 Setup (0x07C)
  • Page 256 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 257 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR0 of the non-transparent bridge. When 64-bit addressing is selected, the translated base...
  • Page 258 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 259 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR1 of the non-transparent bridge. Not reset by external fundamental reset or internal/external hot reset...
  • Page 260 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 261 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR2 of the non-transparent bridge. When 64-bit addressing is selected, the translated base...
  • Page 262 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value SIZE Address Space Size. This field selects the size, in address bits, of the address space for the corresponding BAR or BAR pair when 64-bit addressing is selected.
  • Page 263 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 31:4 TBADDR Translated Base Address. This field specifies the trans- lated base address for transactions that map through BAR3 of the non-transparent bridge. When a transaction address is translated, the PCI address bits from bit 31 through the bit specified by the SIZE field are replaced by the corresponding bits in this field.
  • Page 264 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 14:12 FUNC Function Number. This field selects the function number as defined by Section 7.2.2 of the PCI Express Base Spec- ification, Rev. 1.0a 19:15 Device Number. This field selects the device number as defined by Section 7.2.2 of the PCI Express Base Specifi-...
  • Page 265 IDT Non-Transparent Mode Operation Notes PCEE_PTCSTS - Punch Through Configuration Status (0x0A8) Field Default Type Description Field Name Value BUSY Punch Through Configuration Interface Busy. This bit is set when a punch through configuration transaction is in progress. 0x0 - (idle) configuration transaction interface is idle...
  • Page 266 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value ADDR Mapping Table Address. This field contains the DWord address of a mapping table entry. 31:6 Reserved Reserved field. Not reset by external fundamental reset or internal/external hot reset...

  • Page 267: Non-Transparent Bridge Communications Capability Structure

    Capability Length. This field defines the length in bytes of the capability. It includes the VSID and NXTPTR fields. 31:24 IDTCAP IDT Capability. This field defines an IDT proprietary PCI, PCI-X or PCI Express capability. The value of 0x2 identifies this as a non-transparent bridge communications capability structure...
  • Page 268 IDT Non-Transparent Mode Operation Notes PCEE_SCRATCHPAD[0..1] - Scratchpad [0..1] (0x0D8-ODC) Field Default Type Description Field Name Value 31:0 SCRATCHPAD Scratchpad Value. This scratchpad register may be read and written from both sides of the non-transparent bridge. Scratchpad registers may not be accessed using the Extended Configuration Space Data (ECFGDATA) regis- ter.
  • Page 269 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value INMSG2 RW1C Inbound Message 2. This bit is set whenever a value is written to the OUTMSG2 register located in PCI configura- tion space on the opposite side of the non-transparent bridge.
  • Page 270 IDT Non-Transparent Mode Operation Notes PCEE_INTCTL0 - Interrupt Control 0 (0x0EC) Field Default Type Description Field Name Value INMSG0 Inbound Message 0 Configuration. This field encodes the action taken when the INMSG0 bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 271 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value INMSG2 Inbound Message 2 Configuration. This field encodes the action taken when the INMSG2 bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 272 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 14:12 INDBELL Inbound Doorbell Configuration. This field encodes the action taken when the INMSG1 bit in the INTSTS register is set, or cleared when INTx interrupt signalling is enabled.

  • Page 273: Power Management Capability Structure

    IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 20:18 OSPSTATEM Opposite Side Power State Modification Configuration. This field encodes the action taken when the OSPSTATEM bit in the INTSTS register is set, or cleared when INTx interrupt signalling is enabled.
  • Page 274 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value DEVSP Device Specific Initialization. The value of zero indicates that no device specific initialization is required. 24:22 AUXI AUX Current. not used D1 Support. This field indicates that the PES16NT2 does not support D1.

  • Page 275: Extended Configuration Space Access Registers

    IDT Non-Transparent Mode Operation Extended Configuration Space Access Registers Notes PCEE_ECFGADDR - Extended Configuration Space Access Address (0x0F8) Field Default Type Description Field Name Value Reserved Reserved field. Register Number. This field selects the configuration reg- ister number as defined by Section 7.2.2 of the PCI Express Base Specification, Rev.

  • Page 276: Non-Transparent Bridge Control And Status Registers

    IDT Non-Transparent Mode Operation Non-Transparent Bridge Control and Status Registers Notes PCEE_NTBCFG - Non-Transparent Bridge Configuration (0x200) Field Default Type Description Field Name Value 31:0 Reserved Reserved field. PCEE_INTCTL1 - Interrupt Control 1 (0x210) Field Default Type Description Field Name...
  • Page 277 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value PALINKDN Port A Link Down Configuration. This field encodes the action taken when the PALINKDN bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 278 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 11:9 PBLINKDN Port B Link Down Configuration. This field encodes the action taken when the PBLINKDN bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 279 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value 17:15 PCLINKDN Port C Link Down Configuration. This field encodes the action taken when the PCLINKDN bit in the INTSTS regis- ter is set, or cleared when INTx interrupt signalling is enabled.
  • Page 280 IDT Non-Transparent Mode Operation Notes PCEE_TLPPCTL - TLP Processing Control (0x214) Field Default Type Description Field Name Value Force Relaxed Ordering. When this bit is set, all TLPs in Sticky which the relaxed attribute is applicable are modified as dictated by the Relaxed Ordering Modification (ROM) field in this register for TLPs flowing through the NTB from this side to the opposite side.
  • Page 281 IDT Non-Transparent Mode Operation Notes PCEE_BARTLIMIT1 - BAR 1 Translated Limit Address (0x21C) When the MEMSI field in BARSETUP0 is set to memory space (i.e., zero) and the TYPE field is set to 64-bit addressing, BARTLIMIT1 takes on the function of the upper 32-bits of the TLADDR field in BARTLIMIT0.
  • Page 282 IDT Non-Transparent Mode Operation Notes PCEE_FOVRSTS - Failover Status (0x228) Field Default Type Description Field Name Value CFMODE HWINIT Current Failover Mode. This field indicates the current NTB upstream port failover mode. 0x0 -(normal) external port A associated with internal port A and external port C associated with internal port C.
  • Page 283 IDT Non-Transparent Mode Operation Notes Field Default Type Description Field Name Value DFHRST Disable Failover Hot Reset. When this bit is set, hot Sticky resets due to the data link layer of the upstream or NTB ports transitioning to the DL_Down caused by a failover are disabled.
  • Page 284 IDT Non-Transparent Mode Operation Notes PES16NT2 User Manual 10 - 154 April 15, 2008...

  • Page 285: Jtag Boundary Scan

    Chapter 11 Chapter 11 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES16NT2: AC-coupled and DC-coupled (also called AC and DC pins).

  • Page 286: Table 11.1 Jtag Pin Descriptions

    IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge.

  • Page 287: Boundary Scan Chain

    IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Inter- PEALREV face PEARN[7:0] PEARP[7:0] PEATN[7:0] PEATP[7:0] PECLREV PECRN[7:0] PECRP[7:0] PECTN[7:0] PECTP[7:0] PEREFCLKN[1:0] PEREFCLKP[1:0] REFCLKM SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT General Purpose I/O...

  • Page 288: Boundary Scan Registers

    IDT JTAG Boundary Scan Notes These registers are connected in parallel between a common serial input and a common serial data output and are described in the following sections. For more detailed descriptions, refer to IEEE Standard Test Access Port (IEEE Std. 1149.1).

  • Page 289: Instruction Register (Ir)

    IDT JTAG Boundary Scan Notes shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 11.5 Diagram of Bidirectional Cell The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register.

  • Page 290: Extest

    IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.

  • Page 291: Clamp

    Bit(s) Mnemonic Description Reset Reserved Reserved 11:1 Manuf_ID Manufacturer Identity (11 bits) 0x33 This field identifies the manufacturer as IDT. 27:12 Part_number Part Number (16 bits) 0x804C This field identifies the silicon as PES16NT2. 31:28 Version Version (4 bits) silicon- This field identifies the silicon revision of the PES16NT2.
  • Page 292 IDT JTAG Boundary Scan Notes the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test- Logic-Reset controller state by continuously holding JTAG_TRST_N low and/or JTAG_TMS high when the chip is in normal operation. If JTAG will not be used, externally pull-down JTAG_TRST_N low to disable it.

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