Sony KDX-46Q005 Service Manual page 59

3-2. BLOCK DIAGRAMS
3-2-1. DISPLAY UNIT (XDM-F4600Q)
(1) DE6, H1D and H2D Boards
CN5901
R0 +/-
2
R2 +/-
2
IC5906
TO
BUS LINE BUFF C
MEDIA
RECEIVER DSCL 7
T1MJ BOARD
CN9008
DSDA 2
DISPLAY SIGNAL IN
(WHITE)
HDMI-HPD
T1MJ BOARD
DISPLAY SIGNAL IN
D1002 D1003
CN1001
1 STBY5V
Q1008
3 MUTE_LED
Q1007
4 TIMER_LED
Q1003
5 POWER_LED
Q1006
6 STBY_LED
Q1001
7 STBY_LO
Q1004
Q1002
Q1005
R G
H1D
D1001
CN1101
IC1101
1 STBY5V
VCC OUT
SIRCS 2 SIRCS
4 3.3V
5 BL_IN
IC1102
1 ILLUMINANCE 5
SENSOR
H2D
IC5907 IC5910
D5917
EQULIZER PANEL LINK RECEIVER
D5919
30,31 20,21 ER0 +/- 60,61
ADJ 0N/0P RX0 +/- QO0-7
R1 +/- 33,34 17,18 ER1 +/- 2 64,65
ADJ 1N/1P RX1 +/-
2 LIMIT. 39,40 13,14 ER2 +/- 2 68,69
ADJ 2N/2P RX2 +/- QO8-15
RC +/- 27,28 23,24 ERC +/- 2 56,57
AC KN/KP RXC +/-
2 2
QO16-23
25 HDMI_RST 99
Q5905
CE RESET
6
2 1
OE0-7
46
DSCL
3 47
DSDA OE8-15
OE16-23
3.3V_HP
94
XTALOUT ODCK
X5901
VSYNC
27MHz
95
XTALIN HSYNC
CSDA
CSCL
IC5901 Q5912
BUFF INV.
5
7
6
STBY_5V
2
1
3
Q5901
Q5102
BUS LINE BUFFER
CN5902
SCL A1
SDA A3
SET ON A4
IC5911
POWER ON B5
5
TO VBUS B6 3
6
MEDIA
JIG A7
RECEIVER
CABLE DET B7 IC5905
IC5913
D5921
CN9005 A8 3,4 5 1
SIRCS +/- . LIMITTER 4
A10 2
D5920
(BLACK)
A11
SPDIF +/- . LIMITTER
A13
UDM B8
UDP B9
IC5902
XRESET B11
IC5911
DE_REBOOT A6
1
DE_BUSY B12 7
2
STBY5V B13 STBY5V
TO
K BOARD IC5912
CN2600 LINE RECEIVER
CN5903 1 SPDIF-
7
A
SPDIF- 3 2 SPDIF+
CN5103
STBY5V 1 STBY5V
MUTE 3
TIMER 4
POWER 5
STBY 6
1
STBY_LO 7 7
2
SIRCS 9
IC5103
Q5911
BL_IN 12
IC5104
STBY5V 8 STBY5V
EXA SDA 2 1
3.3V 11 3.3V
EXA SCL 5 6
7 3
CN5106
LED VBUS 1
LED UDM 2
LED UPD 3
EXT_SCL
SCL 5
EXT_SDA
SDA 6
PROTO 7
RSTX 8
MODE_SEL 9
1
7
2
CN5105
IC5110
STBY_5V 3.4 STBY5V 6
3
SUB_6.5V 7-10 SUB6.5V 5
PANEL_ON 13
PS_PROT 14
THERMO_1 15
THERMO_2 16
B
FAN_DRIVE 17
FAN_ERR 18
TO
G2L BOARD POWER_ON 19
CN6204
AC_OFF_DET 20
G_PROT 21
P_VCC 25-28
IC5105
3.3V REG STBY3.3V
IC8208
+1.5V
1.5V REG
Q8202,8203
IC5302
DISPLAY ENGINE
IFQ(IFQ0_2-9) ONRED(OVRED1_0-9)
IFQO OVRED1
8 10
IFQ(IFQ0_12-19) OVRED(OVRED2_0-9)
IFQO OVRED2
8 10
IFQ(IFQ0_22-29) OVGRN(OVGRN1_0-9)
IFQO OVGRN1
8 10
IFQ(IFQE_2-9) OVGRN(OVGRN2_0-9)
IFQE OVGRN2
8 10
IFQ(IFQE_12-19) OVBLU(OVBLU1_0-9)
IFQE OVBLU1
8 10
IFQ(IFQE_22-29) OVBLU(OVBLU2_0-9)
IFQE OVBLU2
8 10
CLK
IFVSYNC
IFHSYNC
IFDE
DE
45 OVVS
IC5301
46 DRAM OVHS
BDDQ0-15 OVBLKDE
DQ BDDQ
OBA0-11 16 OVCLK2
A ODA
12 DCC0
9 DCC1
CLX
ICFREE
BCSDA
IC5101
ICSCL
RESET
S5799
IC5102
DISPLAY ENGINE MINRO CONTROLLER
50
D_DEV_RST
61
IC FREE
58
HDMI_RESET
24
CABLE_DET
90
RESET
STBY3.3V
IC5904
Q5904 IC5908
7 6 1 2 27
SCL0
2 3 6 5 28
SDA0
5
3 3 7 23
6 SET_ON
IC5902
48
Q5908 BUS_SW1
IC5903
1
5
3
2
4
12
2 1
14
13
15 NON_PANEL_MODE
7
11
B A
9 10
Q8204
70
FPGA_BINT
68
DE_BUSY
117
PICTURE_LED
118
TIMER_LED
119
POWER_LED
120
STBY_LED
98
MAIN SW
62
STBY_LO_INT
42
BL_IN
Q5103 AUDIO RESET 100
LIMITTER
74
USB_DVP
73
AUDIO RESET
USB_DVM
STBY3.3V
80
HCONX
Q5205 63
INV_FAIL
1
LED_RST
91
BUS_SW0
IC5107
2 1 64
SCL1
5 6 65
SDA1
3 7 2
LED_INT
49
BUS_SW2
95
ERR2
39
TEMP1
40
TEMP2
69
FAN
92
FAN ERR
94
ERR1
93
PANELON
97
POWER
96
ERR3
Q5101
IC8209
OVRED(OFR1_2-9)
8
OVRED(OFR2_2-9)
8
OVGRN(OFG1_2-9)
8
OVGRN(OFG2_2-9)
8
OVBLU(OFG1_2-9)
8
OVBLU(OFG2_2-9)
8
OFHSYNC
OFVSYNC
OFDE
OFCLK
DCLK
nCOFFIG
nCE
DATAO
nCSO
R15
ASDO
P17
R14
57 R13
NVM_ERR
60
CMP_STOP
25
INT_V
55
PANEL_PD
4
CONF_DONE
11
SIN0
12
SDT0
17
SCK0
SCL2
SDA2
104
BINT
21
P60
22
P61
89
MD0
87
MD2
45
IC5106 IC8207
66 6 6 FPGA_SCL
SCL2 SCL2A SCL
67 5 5 FPGA_SDA
SDA2 SDA2A SDA
99 7 7
NVM_WP1 WP WP
82
CH_M/S_SW
81
CH_IIC_SW
102
SP PROT
8
OF_FLAG
6
K3.3V_SW
46
CH_NVM_WP
51
CH_RST
PRO 9
SCLATCH
103
AMP
10
SCLATCH2
19
SDT1
20
SCK1
AUDIO 101
MUTE
52
TMDS_ON
59
OVP_DET Q5107
PS5101
IC5109
SWITCHING REG
1 11
SEL1 OUT1
8 16
INV1
INV2
19 5
STB OUT2
Q5108
LVDS TRANSMITTER,
DE6
MICRO CONTROLLER
IC5408
LVDS TRANSMITTER
CN5407
R10 88,49 1
TA1 +/- . TX00 +/-
R17 2
R20 46,47 3
TB1 +/- . TX01 +/-
R27 4
G10 43,44 5
TC1 +/- . TX02 +/-
G17 6
G20 39,40 9
TD1 +/- . TX03 +/-
G27 10
B10 41,42 7
TCLK +/- . TX0CLK +/-
B17 8
B20 36,37 11
TA2 +/- . TXE0 +/-
TO
B27 12
PDP
7 34,35 13
UNIT
HSYNC TB2 +/- . TXE1 +/-
8 14
VSYNC
9 31,32 15
DE TC2 +/- . TXE2 +/-
10 16
CLKIN
27,28 19
TD2 +/- . TXE3 +/-
19 20
/PDWN
29,30 17
TCLK2 +/- . TXECLK +/-
18
26 DCC
25 GND(DCC-SEL1)
27
VCC
30
CN8200
1 DCLK
3 CONF_DONE
5 /CONFIG
6 /CE
IC8202
7 DATAO
CONFIGURATION
8 /CSO
ROM
5 9 ASD
DCLK
2 3.3V 4 VCC
DATAO
1
NCS
7
ASDIO
CN5104
STBY3.3V
STBY3.3V 1 STBY3.3V
3 SIN
4 SDT
5 SCK
6 RESET
SCL_JIG
7 SCL
SDA_JIG
8 SDA
9 BINT
Q5106
10 P60
11 P61
12 MD0
13 MD2
14 NON_PANEL_MODE
3.3V
15 NVM_WP1
5V_FPGL_SCL
21 FPGA_SCL
5V_FPGL_SDA
22 FPGA_SDA
23 FPGA_BINT
+3.3V 16 3.3V
1.8V_HP 17 1.8V-HP
+1.8V 18 1.8V
+1.5V 19 1.5V
CN5101
EXA SDA 3 DAT_D
EXA SCL 4 CLK_D
5 CH_M/S_SW
6 CH_IIC_SW
7 SP_PROT
8 A_MUTE
9 OF_FLAG
10 3.3V_SW
C
11 CH_WP
12 CH_RST TO
K BOARD
13 M_RST
CN2603
14 SCLATCH
15 AMP_RST
16 SCLATCH2
17 SCDT
18 SCSHIFT
IC5103
5
3
6
Q5104
+1.8V
Q5902
Q5903
D5109
3.3V_HP
IC5909
1.8V REG 1.8V_HP
+3.3V
D5110
KDX-46Q005 (UC) 3-2