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Related Manuals for Tews Technologies TAMC900
Summary of Contents for Tews Technologies TAMC900
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Page 1: User Manual
TAMC900 AMC with 8 high Speed ADCs 105MSps, 14Bit Version 2.0 User Manual Issue 2.0.1 April 2010 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com... - Page 2 However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
- Page 3 New User Manual Issue Notation January 2009 Correction of “MMC JTAG Connector Pin Assignment” 2.0.0 Update to TAMC900 V2.0 November 2009 Added FPGA code description 2.0.1 Firmware Upgrade to Version 2 April 2010 TAMC900 User Manual Issue 2.0.1 Page 3 of 71...
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Page 4: Table Of Contents
Channel Pre-Trigger Data Size ....................35 6.10 Channel Data 0–7 ..........................36 6.11 General DMA Status........................37 6.12 Channel DMA Status 0-7 ......................38 6.13 Channel DMA Buffer Fill-Level 0-7 ....................39 6.14 Revision Control Register......................39 TAMC900 User Manual Issue 2.0.1 Page 4 of 71... - Page 5 14.3 Board and Component Height .....................61 15 MODULE MANAGEMENT CONTROLLER (MMC) ............ 62 15.1 Indicators ............................62 15.1.1 Front Panel LEDs........................62 15.2 Temperature and Voltage Sensors....................63 15.3 Connectivity...........................63 15.4 Interfaces to Payload ........................64 TAMC900 User Manual Issue 2.0.1 Page 5 of 71...
- Page 6 16.1 DONE LED............................65 16.2 Power Good LEDs.........................65 17 PIN ASSIGNMENT...................... 66 17.1 Overview ............................66 17.2 I/O Connector ..........................67 17.3 MMC JTAG Connector (Factory Use Only).................69 17.4 Payload JTAG Connector......................69 17.5 AMC Connector ..........................69 TAMC900 User Manual Issue 2.0.1 Page 6 of 71...
- Page 7 TABLE 4-2 : ADC DATA FORMAT WITH SIGN EXTENSION ...............15 TABLE 4-3 : DMA DESCRIPTOR STRUCTURE ....................19 TABLE 5-1 : TAMC900 PCI DEVICE INFORMATION..................24 TABLE 5-2 : TAMC900 LOCAL SPACE CONFIGURATION ................24 TABLE 5-3 : TLP TYPE SUMMARY .......................25 TABLE 5-4 : REGISTER MAP.........................27 TABLE 5-5 : DMA DESCRIPTOR SPACE ......................27...
- Page 8 TABLE 15-1: FRONT PANEL LEDS .......................62 TABLE 17-1: PIN ASSIGNMENT I/O CONNECTOR..................68 TABLE 17-2: PIN ASSIGNMENT MMC JTAG CONNECTOR (FACTORY USE ONLY)........69 TABLE 17-3: PIN ASSIGNMENT PAYLOAD JTAG CONNECTOR ...............69 TABLE 17-4: PIN ASSIGNMENT AMC CONNECTOR...................71 TAMC900 User Manual Issue 2.0.1 Page 8 of 71...
- Page 9 List of Figures FIGURE 1-1 : BLOCK DIAGRAM TAMC900 WITH SIGNAL CONDITIONING ADAPTER ......10 FIGURE 4-1: TAMC900 FPGA SYSTEM STRUCTURE ................14 FIGURE 9-1 : SHIELDING COVER DIMENSIONS ..................46 FIGURE 10-1: QDR-II SRAM INTERFACE.....................47 FIGURE 11-1: CLOCK DISTRIBUTION BLOCK DIAGRAM................48 FIGURE 13-1: TIMING OF FPGA-CPLD INTERFACE...................51 FIGURE 14-1: TAMC900 CONNECTOR AND STANDOFF POSITIONS ............60...
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Page 10: Product Description
The up to x8 PCIe link of the TAMC900 is used to transmit the ADC data to the CPU. To adapt the TAMC900 to different customer requirements, the TAMC900 is equipped with a Signal Conditioning Adapter (SiCA) which holds the connector for the analog inputs, the connectors for the clock and trigger inputs, and the analog signal conditioning. -
Page 11: Technical Specification
Physical Data Power Requirements 2A typical, 4A max. @ +12V DC (Payload Power) 50 mA typical @ +3.3V DC (Management Power) The exact Power requirement of the TAMC900 depends on Signal Cond. Adapter used and FPGA utilization. Temperature Range Operating 0 °C to +55 °C... -
Page 12: Handling And Operating Instructions
The TAMC900 will be damaged if higher voltage levels are applied. 3.1 ESD Protection The TAMC900 is sensitive to static electricity. Packing, unpacking and all other handling of the TAMC900 has to be done in an ESD/EOS protected area. 3.2 Thermal Considerations The TAMC900 requires forced air cooling during operation. -
Page 13: Amc Module Insertion & Hot-Swap
Request Hot-Swap Pulled out 1/2 Short Blink Hot-Swap Negotiation Pulled out 1/2 Module is ready to be extracted Open (Full extracted) Extract Module from slot Table 3-2 : AMC Module Extraction TAMC900 User Manual Issue 2.0.1 Page 13 of 71... -
Page 14: Functional Procedures
The following diagram illustrates the structure of the ADC data acquisition system implemented on the TAMC900. The structure is abstract in order to show the different functional units and the data flow. All physical connections are termed in a bold style. The remaining ones are internal connections. -
Page 15: Channel Logic
0x1FFE +0.000122V 0x8001 0x0001 0.000000V 0x8000 0x0000 -0.000122V 0x1FFF 0xFFFF -0.000244V 0x1FFE 0xFFFE -0.999878V 0x0001 0xE001 -1.000000V 0x0000 0xE000 <-1.000000V 0x0000 0xE000 Table 4-2 : ADC Data Format with Sign Extension TAMC900 User Manual Issue 2.0.1 Page 15 of 71... -
Page 16: Tracking Buffer
It is used to stop providing new data to the DMA Engines if one engine signalizes that its dedicated channel FIFO is running full. One stalled channel may cause that all channels of the group get into error state due to buffer overflow. TAMC900 User Manual Issue 2.0.1 Page 16 of 71... -
Page 17: Operation Modes (Om)
All trigger inputs are handled in the same manner. There is no difference. Additionally the Post Trigger Data gathering can be used in conjunction with the software trigger to realize a free-running operation mode if necessary. TAMC900 User Manual Issue 2.0.1 Page 17 of 71... -
Page 18: Dma Engine
For this a descriptor contains on the one hand flags required for its processing and on the other hand information to build a Linked List (LL). TAMC900 User Manual Issue 2.0.1 Page 18 of 71... -
Page 19: Table 4-3 : Dma Descriptor Structure
The Subsequent Linked List Pointer is an address inside the module’s descriptor address range (see above). Due to the 36 kbit Block RAM size the address length is 10 bit. Setting the Linked List Pointer to 0x0 selects the first DMA descriptor memory address. TAMC900 User Manual Issue 2.0.1 Page 19 of 71... -
Page 20: Sample Rate Logic
CPLD has been reset 4.6.2 Pre-Initialization (Setup) Check Before any operation on the TAMC900 can be performed it has to be checked that • the GSTAT bit inside the Module Status and DCM 0/1 Status register indicates that the module is operational, •... -
Page 21: Channel Setup
Shutdown steering input. Valid ADC samples can only be obtained if the sample frequency is set correctly and this bit is set. Stopping a channel should not be done with this steering bit since the DMA operation will not stop. TAMC900 User Manual Issue 2.0.1 Page 21 of 71... -
Page 22: Descriptor Change
Manipulating the content of a DMA (Base) Descriptor Addresses register while the accompany DMA Engine is active is not allowed. Moreover changing a Descriptor in memory during its processing is also not allowed. TAMC900 User Manual Issue 2.0.1 Page 22 of 71... -
Page 23: Channel Start/Stop
For all channels at least 256 k samples can be obtained independently of the transmission rate caused by the integration of the QDR-II memory in the transmission path (refer chapter “Tracking Buffer”). The amount of data can be composed over all channels. TAMC900 User Manual Issue 2.0.1 Page 23 of 71... -
Page 24: Address Map
5 Address Map 5.1 PCI Express Configuration The TAMC900 module will be present in the PCI Device Tree with the subsequent information. PCI Information Hex Value Description Vendor 0x1498 TEWS TECHNOLOGIES GmbH Device ID 0x8384 TAMC900 Class Code 0x118000 Signal Processing Controller... -
Page 25: Table 5-3 : Tlp Type Summary
Read Locked, 64 Bit Addressing Prohibit, Error Message Configuration Read, 0/1 Permitted Configuration Write, 0/1 Permitted Messages Dumped Completion Prohibit, Error Message Completion, Locked Prohibit, Error Message Table 5-3 : TLP Type Summary TAMC900 User Manual Issue 2.0.1 Page 25 of 71... -
Page 26: Register Space
0x0064 Channel Pre-Trigger Data Size 0 0x0068 Channel Pre-Trigger Data Size 1 0x006C Channel Pre-Trigger Data Size 2 0x0070 Channel Pre-Trigger Data Size 3 The read value will always be zero. TAMC900 User Manual Issue 2.0.1 Page 26 of 71... -
Page 27: Dma Descriptor Space
Table 5-4 : Register Map 5.3 DMA Descriptor Space Offset to PCI Register Name Access Size Base Address 1 (Bit) 0x0 : 0x1FFF Channel DMA Descriptor Memory Table 5-5 : DMA Descriptor Space TAMC900 User Manual Issue 2.0.1 Page 27 of 71... -
Page 28: Register Description
1 = Module is operating 0 = Module is not operating Table 6-1 : Module Status Register (Address 0x0) The module should not be used for DMA transmissions if the GSTAT bit is not asserted. TAMC900 User Manual Issue 2.0.1 Page 28 of 71... -
Page 29: Dcm Multiply/Divide 0/1
The legal value range reflect the Virtex-5 DCM specification. Do not use values other than the allowed ones. The minimum frequency that can be set is 32 MHz. The reset value adjusts a sample frequency of 50 MHz. TAMC900 User Manual Issue 2.0.1 Page 29 of 71... -
Page 30: Global Channel Configuration
Activation of a channel via the register above should be done after the channel has been configured correctly. Internal processing holds the corresponding channel processing logic in reset state if the channel enable bit (CHENx) is not set. TAMC900 User Manual Issue 2.0.1 Page 30 of 71... -
Page 31: Global Reset And Software Trigger Input
Writing a value 0x1 at this bit position causes a single-cycle trigger input. Table 6-4 : Global Reset and Software Trigger Input Register (Address 0x10) The software generated trigger inputs are equivalent to external trigger signals. Read Value is always zero TAMC900 User Manual Issue 2.0.1 Page 31 of 71... -
Page 32: Sample Clock Configuration 0/1
Reserved Reserved SCEN Channel Group Sample Clock Enable Table 6-5 : Sample Clock Configuration Register (Address 0x14+ 0x4*Channel Group) The ‘x’ inside the embedded table represents a do not care condition. TAMC900 User Manual Issue 2.0.1 Page 32 of 71... -
Page 33: Trigger Configuration 0/1
0100 Rising Trigger input 1 (TRIG_1) 0101 Falling 0110 Rising Trigger input 2 (TRIG_2) 0111 Falling 1000 Software Trigger Others Reserved Table 6-6 : Trigger Configuration Register (Address 0x1C+ 0x4*Channel Group) TAMC900 User Manual Issue 2.0.1 Page 33 of 71... -
Page 34: Channel Configuration 0-7
0 = disable channel 1 = enable channel Table 6-7 : Channel Configuration Register (Address 0x24+ 0x4*Channel) If a channel is not enabled (CHEN), the corresponding Channel Data register will always be zero (0x0). TAMC900 User Manual Issue 2.0.1 Page 34 of 71... -
Page 35: Channel Dma (Base) Descriptor Addresses 0-7
Table 6-9 : Channel Pre-Trigger Data Register (Address 0x64+ 0x4*Channel) Setting a value different then one requires that the number of samples has already been acquired by the module. If this condition is violated, the obtained data will be invalid. TAMC900 User Manual Issue 2.0.1 Page 35 of 71... -
Page 36: Channel Data 0-7
Table 6-10: Channel Data Register (Address 0x84+ 0x4*Channel) The value read from such a register cannot be the last that has been sampled due to the AD Converter 5-stage internal pipeline. TAMC900 User Manual Issue 2.0.1 Page 36 of 71... -
Page 37: General Dma Status
ECH2 ECH1 ECH0 Table 6-11: Global DMA Status Register (Address 0xA4) The channel event information is obtained from the single channel DMA status registers. Thus it must not be cleared here. TAMC900 User Manual Issue 2.0.1 Page 37 of 71... -
Page 38: Channel Dma Status 0-7
The status flags have to be cleared for acknowledgement. The errors marked with an asterisk (*) require a channel reset to get into a defined state. All flags are cleared automatically after processing start (valid trigger input). TAMC900 User Manual Issue 2.0.1 Page 38 of 71... -
Page 39: Channel Dma Buffer Fill-Level 0-7
31:0 CREV Code Revision of the FPGA Firmware Table 6-14: Revision Control Register (Address 0xE8) The version of the Firmware is not fixed and depends besides others on the hardware version. TAMC900 User Manual Issue 2.0.1 Page 39 of 71... -
Page 40: Interrupts
Consequently interrupts have to be acknowledged after their occurrence. The use of Message Signaled Interrupts may introduce spurious interrupts as described in the PCI Specification. TAMC900 User Manual Issue 2.0.1 Page 40 of 71... -
Page 41: Fpga
Interface Description FUNC_LED2 This signal can be used to flash the USER LED in the front panel of the TAMC900. A rising or falling edge of FUNC_LED2 triggers the MMC to turn the USER LED off for app. 100ms. EKEY[4:1] These signals can be used to transmit connectivity data from the MMC to the FPGA. -
Page 42: Amc Interface
RX2- TX3+ TX3- RX3+ RX3- TX4+ TX4- RX4+ RX4- TX5+ TX5- RX5+ RX5- TX6+ TX6- RX6+ RX6- TX7+ TX7- RX7+ RX7- Table 8-2 : AMC Fabric Interface connections to the FPGA TAMC900 User Manual Issue 2.0.1 Page 42 of 71... -
Page 43: Ram Interface
MMC. Otherwise, proper operation of the TAMC900 is not possible. 8.4 RAM Interface The RAM interface to access the QDR-II SRAM of the TAMC900 has to be implemented in the FPGA. TEWS recommends using the Xilinx Memory Interface Generator (MIG) to build the RAM interface logic. -
Page 44: Adcs
The LTC2254 differential inputs are routed to the Signal Conditioning Adapter (SiCA) connector. For the pin assignment, please refer to chapter “I/O Connector”. Any signal conditioning of the analog inputs is not done on the TAMC900. This is done by the SiCA. The SiCA also carries the I/O connectors accessible through the face plate. -
Page 45: Clock Duty Cycle Stabilizer
For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle. TAMC900 User Manual Issue 2.0.1 Page 45 of 71... -
Page 46: Shielding
9.3 Shielding The TAMC900 allows adding a cover to shield its ADCs. See picture below for cover mounting area dimensions. The cover must ensure a minimum free height of 3 mm and sufficient cooling of the ADCs. 37,50 mm 34,30 mm... -
Page 47: Memory
10 Memory The TAMC900 provides 4 MByte QDR-II SRAM. 2 RAM devices with 18 bit wide data bus each are used to implement the 4 MByte RAM of the TAMC900. The two RAMs have fully independent interfaces to the FPGA:... -
Page 48: Clock Distribution
11 Clock Distribution The TAMC900 has several Clock sources: • 3 Clock Inputs from the SiCA • 1 Clock Input from AMC interface connector • 2 local Clocks • 2 Clock outputs of the FPGA The Clocks are distributed to the ADCs and the FPGA. Configuration of the Clock Distribution is done via the on board CPLD. -
Page 49: Table 11-1: Fpga Local Clock (Lclk_250) Inputs
4 – 7 V5_CLKOUT 1- Table 11-2: FPGA Clock Outputs The TAMC900 provide two feedback clocks (MUX0_FB and MUX1_FB) that return the ADC clocks back to the FPGA. The following table provides the pin assignment of the feedback clock inputs: Signal Name... -
Page 50: Lvds Link
12 LVDS Link The TAMC900 provides a differential interface from the FPGA to the SiCA connector. 10 differential pairs out of one FPGA I/O bank are routed to the SiCA connector. For the Virtex-5 and SiCA connector pin assignment, see table below. -
Page 51: On Board Cpld
13 On Board CPLD The On Board CPLD of the TAMC900 is used for static board configuration and provides the following functions: • QDR-II SRAM DLL enable / disable • ADC Shutdown • ADC Output Enable • ADC Mode selection (all 4 modes available) •... -
Page 52: Cpld Register Description
13.2 CPLD Register Description The following registers are implemented in the on board CPLD of the TAMC900. They are used for static board configuration. For user access, the CPLD provides an interface to the FPGA. CPLD- Register Description Value after Reset... -
Page 53: Adc X Control Register (Address 0X00 To 0X07)
I_SiCA13 I_SiCA12 Displays the value of the corresponding SiCA general purpose pin. Value after reset depends on the SiCA. I_SiCA11 I_SiCA10 I_SiCA9 I_SiCA8 Table 13-3: SiCA Input Register 1 (Address 0x08) TAMC900 User Manual Issue 2.0.1 Page 53 of 71... -
Page 54: Sica Input Register 2 (Address 0X09)
SiCA on the corresponding SiCA general purpose pins if the pin is defined as output in the corresponding SiCA O_SiCA3 Output Enable Register. O_SiCA2 O_SiCA1 O_SiCA0 Table 13-6: SiCA Output Register 2 (Address 0x0B) TAMC900 User Manual Issue 2.0.1 Page 54 of 71... -
Page 55: Sica Output Enable Register 1 (Address 0X0C)
Sets the corresponding SiCA general purpose pins as EN_SiCA4 input or output. 0 = CPLD input EN_SiCA3 1 = CPLD output EN_SiCA2 EN_SiCA1 EN_SiCA0 Table 13-8: SiCA Output Enable Register 2 (Address 0x0D) TAMC900 User Manual Issue 2.0.1 Page 55 of 71... -
Page 56: Crosspoint Switch Control Register (Address 0X10)
01 = Clock input 1 : EXT_CLK2 OUT0_ 10 = Clock input 2 : EXT_CLK1 SEL0 11 = Clock input 3 : EXT_CLK0 Table 13-9: Crosspoint Switch Control Register (Address 0x10) TAMC900 User Manual Issue 2.0.1 Page 56 of 71... -
Page 57: Clock Mux Control Register (Address 0X11)
1 = route Clock from FPGA to ADCs EN_03 Enable Clock outputs to ADC 0 to 3. 0 = disable 1 = enable Table 13-10: Clock Mux Control Register (Address 0x11) TAMC900 User Manual Issue 2.0.1 Page 57 of 71... -
Page 58: Jitter Attenuator Control Register (Address 0X12)
1 = disable Output disable for the QA0 and QA1 clocks 0 = enable 1 = disable Table 13-11: Jitter Attenuator Control Register (Address 0x12) Do not change the frequency of QA0/QA1. TAMC900 User Manual Issue 2.0.1 Page 58 of 71... -
Page 59: General Board Control Register (Address 0X18)
LOC_CLK Disable local 250 MHz clock 0 = enable 1 = disable Table 13-12: General Board Control Register (Address 0x18) TAMC900 User Manual Issue 2.0.1 Page 59 of 71... -
Page 60: Signal Conditioning Adapter (Sica)
TAMC900. Depending on customer needs, the form and function of the SiCA can vary. For more information please refer to the corresponding SiCA User Manual. The SiCA is powered from the TAMC900 with +6 Volts from a switched power supply. Any other voltages needed must be generated on the SiCA. -
Page 61: Mating Connector
Mating Connector The mating connector connects the SiCA with the TAMC900. The Samtec QSE/QTE Series is used, and the height of the connector mounted on the SiCA dictates the stacking height of the SiCA above the TAMC900. Possible connectors are (e.g):... -
Page 62: Module Management Controller (Mmc)
15.1 Indicators For a quick visual inspection the TAMC900 offers 3 LEDs in the front panel and seven on board LEDs. For a detailed description of the on board LEDs, please refer to chapter “On Board Indicators”. 15.1.1 Front Panel LEDs... -
Page 63: Temperature And Voltage Sensors
15.3 Connectivity The on board FPGA of the TAMC900 is connected to AMC Port 4 to 11. AMC FCLKA (CLK3) is connected to the FPGA via a Jitter-Attenuator that scales the clock from 100 MHz up to 250 MHz and reduces the Clock Jitter. -
Page 64: Interfaces To Payload
These signals can be used to implement a serial communication between FPGA and MMC. By default, this is used as debug-output of the MMC. Any other implementation in MMC and FPGA has to be done by the customer. TAMC900 User Manual Issue 2.0.1 Page 64 of 71... -
Page 65: On Board Indicators
16.2 Power Good LEDs There are six green “Power Good” LEDs on the bottom side of the TAMC900. If one of the LEDs is off, this indicates a power failure of the corresponding power supply. TAMC900 User Manual Issue 2.0.1... -
Page 66: Pin Assignment
I/O Connector (X3) Figure 17-1: Connector Overview The TAMC900 interfaces to a Signal Conditioning Adapter that carries the I/O connectors accessible through the front panel. The TAMC900 has a 120 pin connector (Samtec QSE-060-01-L-D-A) that interfaces to the Signal Conditioning Adapter. See the figure below for pin locating of this connector. -
Page 67: I/O Connector
The I/O interface of the TAMC900 is the connector between SiCA and the TAMC900. The Samtec QTE / QSE Series are used as I/O connection between TAMC900 and the SiCA. The TAMC900 carries a QSE connector, and the mating QTE connector is populated on the SiCA. The stacking height is defined by the QTE connector on the SiCA. -
Page 68: Table 17-1: Pin Assignment I/O Connector
LVDS GP_IO_12 2.5 Volt CMOS logic Ground GP_IO_13 2.5 Volt CMOS CLKIN_2+ LVDS GP_IO_14 2.5 Volt CMOS CLKIN_2- LVDS GP_IO_15 2.5 Volt CMOS logic Ground Table 17-1: Pin Assignment I/O Connector TAMC900 User Manual Issue 2.0.1 Page 68 of 71... -
Page 69: Mmc Jtag Connector (Factory Use Only)
Logic Ground Do Not Connect - Logic Ground Do Not Connect - Table 17-3: Pin Assignment Payload JTAG Connector 17.5 AMC Connector Signals written in Italic are not connected on the TAMC900 Signal Function Signal Function Logic Ground Logic Ground... - Page 70 +12V Payload Power Rx15- Differential Signaling ENABLE# AMC Enable Input Rx15+ Logic Ground Logic Ground Rx3- Tx15- Differential Signaling Differential Signaling Rx3+ Tx15+ Logic Ground Logic Ground Tx3- Differential Signaling TCLKC- Differential Signaling TAMC900 User Manual Issue 2.0.1 Page 70 of 71...
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Page 71: Table 17-4: Pin Assignment Amc Connector
Geogr. Address Input JTAG TMS Input +3.3V TRST# JTAG Reset Input PS1# Present detect JTAG TDO Output +12V Payload Power JTAG TDI Input Logic Ground Logic Ground Table 17-4: Pin Assignment AMC Connector TAMC900 User Manual Issue 2.0.1 Page 71 of 71...
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