Philips MC-D370/21M Service Manual page 48

8M bit MULTI-PURPOSE FLASH
SST39VF080
F B D
UNCTIONAL LOCK IAGRAM
X-Decoder
Memory
Address Buffer & Latches
Address
CE#
Control Logic
OE#
WE#
A16 1
A15 2
A14 3
A13 4
A12 5
A11 6
A9 7
A8 8
Standard Pinout
WE# 9
NC 10
NC 11
NC 12
A18 13
A7 14
A6 15
A5 16
A4 17
A3 18
A2 19
A1 20
P A 40- TSOP
IN SSIGNMENTS FOR PIN
P D
IN ESCRIPTION
Symbol Pin Name Functions
A -A Address Inputs To provide memory addresses. During Sector-Erase A
MS 0
lines will select the sector. During Block-Erase A
will select the block.
DQ -DQ Data Input/output To output data during Read cycles and receive input data during Write
7 0
cycles. Data is internally latched during a Write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF080/016
DD
Vss Ground
NC No Connection Unconnected pins.
Note: A = Most significant address
MS
A = A for SST39LF/VF080 and A for SST39LF/VF016.
MS 19 20
9-2
EEPROM
Cell Array
Y-Decoder
I/O Buffers and Data Latches
DQ 7 - DQ 0
396 ILL B1.1
40 A17
39 V SS
38 NC
37 A19
36 A10
35 DQ7
34 DQ6
33 DQ5
32 DQ4
31 V DD
Top View
30 V DD
29 NC
Die Up
28 DQ3
27 DQ2
26 DQ1
25 DQ0
24 OE#
23 V SS
22 CE#
21 A0
396 ILL F01.2
-A address
MS 12
-A address lines
MS 16
2.7-3.6V for SST39VF080/016
SYNCHRONOUS DRAM
4MX16Y3VTW
PIN ASSIGNME NT (Top Vi ew )
54- Pin TSOP
x4 x8 x16
- -
V DD 1
NC DQ0
DQ0 2
- -
V Q 3
DD
NC NC DQ1 4
DQ0 DQ1 DQ2 5
- -
VssQ 6
NC NC DQ3 7
NC DQ2 DQ4 8
- -
V DD Q 9
NC NC DQ5 10
DQ1 DQ3 DQ6 11
- -
VssQ 12
NC NC DQ7 13
- - V 14
DD
NC NC DQML 15
- - WE# 16
- -
CAS# 17
- -
RAS# 18
- - CS# 19
- - BA0 20
- - BA1 21
- - A10 22
- - A0 23
- -
A1 24
- - A2 25
- - A3 26
- - V 27
DD
CKE
CLK
CS# CONTROL
LOGIC
WE#
CAS#
RAS#
REFRESH
COUNTER
MODE REGISTER
12
12
1
A0-A11, ADDRESS
14
BA0, BA1 REGISTER
2
3
4
5
396 PGM T2.2
6
9-2
x16 x8 x4
- -
54 Vss
DQ7 NC
53 DQ15
- -
52 VssQ
NC NC
51 DQ14
50 DQ13 DQ6 DQ3
- -
49 V Q
DD
Note : The # symbol indicates signal is active LOW. A dash (– )
48 DQ12 NC NC
indicates x8 and x4 pin function is same as x16 pin function.
47 DQ11 DQ5 NC
- -
46 VssQ
NC NC
45 DQ10 16 Meg x 48
44 DQ9 DQ4 DQ2
Configuration 4 Meg x 4 x 4 banks
- -
43 V Q
DD
42 DQ8 NC NC Refresh Count 4K
- -
41 Vss
Row Addressing 4K (A0-A11)
40 NC - -
Bank Addressing 4 (BA0, BA1)
39 DQMH DQM DQM
- -
38 CLK
Column Addressing 1K (A0-A9)
- -
37 CKE
- -
36 NC
35 A11 - -
34 A9 - -
33 A8 - -
32 A7 - -
- -
31 A6
- -
30 A5
29 A4 - -
28 Vss - -
FUNCTIONAL BLOCK DI AGRAM
4 Meg x 16 SDRAM
BANK3
BANK2
BANK1
12
ROW- BANK0
12
ROW-
ADDRESS BANK0
ADDRESS
MUX MEMORY
2
4096
LATCH
ARRAY
&
(4,096 x 256 x 16)
DECODER
SENSE AMPLIFIERS DATA
OUTPUT
16
REGISTER
4096
I/O GATING
2
DQM MASK LOGIC
BANK READ DATA LATCH
CONTROL WRITE DRIVERS
DATA
LOGIC
2 INPUT
16
REGISTER
256
(x16)
COLUMN
DECODER
COLUMN-
ADDRESS
8
8 COUNTER/
LATCH
Meg x 84 Meg x 16
2 Meg x 8 x 4 banks 1 Meg x 16 x 4 banks
4K 4K
4K (A0-A11) 4K (A0-A11)
4 (BA0, BA1) 4 (BA0, BA1)
512 (A0-A8) 256 (A0-A7)
2
DQML,
DQMH
DQ0-DQ15
16