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Memec Virtex-4 User Manual

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Virtex-4™ MB Development Board
User's Guide
Version 3.0
December 2005

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  • Page 1 Virtex-4™ MB Development Board User’s Guide Version 3.0 December 2005...

  • Page 2: Table Of Contents

    Table of Contents OVERVIEW ........................1 THE VIRTEX-4 MB SYSTEM BOARD ................1 FUNCTIONAL DESCRIPTION ..................2 LVDS I .......................3 NTERFACE 3.1.1 SPI-4.2 Interface....................4 3.1.2 SPI-4.2 Pin Assignments..................4 3.1.3 LVDS Connector....................6 DDR SDRAM ......................7 ........................8 LASH ......................9 LOCK OURCES 3.4.1 Programmable LVDS Clock Source ..............11 3.4.2...
  • Page 3 Figures 1 - V -4 MB D ..........3 IGURE IRTEX EVELOPMENT LATFORM LOCK IAGRAM 2- SPI-4.2 I ....................4 IGURE NTERFACE 3 – SAMTEC QSE T SPI-4.2 I ........7 IGURE ONNECTOR FOR THE NTERFACE 4 – DDR SDRAM I ..................7 IGURE NTERFACE 5 –...

  • Page 4: Overview

    Overview The Memec Virtex-4™ MB Development Kit provides a complete development platform for designing and verifying applications based on the Xilinx Virtex-4 FPGA family. This kit enables designers to implement DSP and embedded processor based applications with extreme flexibility using IP cores and customized modules. The Virtex-4 FPGA along with Xilinx MicroBlaze soft...

  • Page 5: Functional Description

    Functional Description A high-level block diagram of the Virtex-4™ MB development platform is shown below followed by a brief description of each sub-section. A list of features for this board is shown below: • Xilinx XC4VLX25/LX60/SX35-10FF668 FPGA • 64MB of DDR SDRAM •...

  • Page 6: Lvds Interface

    In addition to the SPI-4.2 interface, the LVDS interface is designed to support XSBI 16-bit LVDS @644Mbps to support a 10GbE interface on the Virtex-4 MB development platform. The following sections provide a brief description of the LVDS interface on this development board.

  • Page 7: Spi-4.2 Interface

    3.1.1 SPI-4.2 Interface The Virtex-4 MB development board provides a SPI-4.2 via a 16-bit parallel LVDS electrical interface. The following figure shows the SPI-4.2 interface on the board. The transmit and receive interface of the SPI-4.2 are implemented using LVDS signals while the status flow control signals are implemented using single-ended LVTTL signals.
  • Page 8 TDat_N(2) TDat_P(3) TDat_P(2) TDat_N(1) TDat_N(0) TDat_P(1) TDat_P(0) TCtl_N TDCLK_N TCtl_P TDCLK_P Table 2 – SPI-4.2 Receive Pin Assignments Virtex-4 Pin # LVDS Signal J5 Connector Pin # LVDS Signal Virtex-4 Pin # Name LVDS RX Name 5.0V 5.0V 5.0V 5.0V 3.3V...

  • Page 9: Lvds Connector

    RSTAT1 RDat_N(15) RDat_N(14) RDat_P(15) RDat_P(14) RDat_N(13) RDat_N(12) RDat_P(13) RDat_P(12) RDat_N(11) RDat_N(10) TDat_P(11) RDat_P(10) RDat_N(9) RDat_N(8) RDat_P(9) RDat_P(8) RDat_N(7) RDat_N(6) RDat_P(7) RDat_P(6) RDat_N(5) RDat_N(4) RDat_P(5) RDat_P(4) RDat_N(3) RDat_N(2) RDat_P(3) RDat_P(2) RDat_N(1) RDat_N(0) AA10 RDat_P(1) RDat_P(0) RCtl_N RDCLK_N AF10 RCtl_P RDCLK_P AF11 3.1.3 LVDS Connector The design of the SPI-4.2 interface requires use of a high-speed and high quality connector.

  • Page 10: Ddr Sdram

    Figure 3 – SAMTEC QSE Type Connector for the SPI-4.2 Interface 3.2 DDR SDRAM The Virtex-4™ MB development board provides 64MB of DDR SDRAM memory (x16). A high- level block diagram of the DDR SDRAM interface is shown below followed by a table describing the SDRAM memory interface signals.

  • Page 11: Flash

    Clock ddr_clke Clock Enable 3.3 Flash The Virtex-4™ MB development board provides 4MB of flash memory (x16). A high-level block diagram of the flash interface is shown below followed by a table describing the flash memory interface signals. Address[0:20] Data[0:15]...

  • Page 12: Clock Sources

    Reset 3.4 Clock Sources The Clock Generation section of the Virtex-4 MB board provides all the necessary clocks for a MicroBlaze processor, the I/O devices located on the board, as well as the DDR SDRAM memory. In general, the clock sources on the board are grouped into two categories; differential and single-ended clock sources.

  • Page 13: Figure 6 - Clock Sources On The

    LVTTL clock input to the FPGA via an 8 or 4-pin oscillator. The following figure shows the clock resources on the Virtex-4 MB development board. Connectors LVTTL P240 P240 Programmable @100 Single-ended Feedback Differential...

  • Page 14: Programmable Lvds Clock Source

    The following table provides a brief description of each clock input to the Virtex-4 FPGA. Table 5 - Clock Inputs Signal Name FPGA Pin # Description CLK_PROG_P, A10, Positive and Negative Differential System Clock Inputs – CLK_PROG_N These clock inputs are connected to the output of an LVDS clock synthesizer.
  • Page 15 The following figure shows a high-level block diagram of the ICS8442 programmable LVDS clock synthesizer. M[0:8] N[0:1] nP_LOAD S_DATA S_CLOCK S_LOAD FOUT0 nFOUT0 VCO_SEL ICS8442 XTAL_SEL FOUT1 TEST_CLK nFOUT1 TEST XTAL1 XTAL2 Figure 7 – ICS8442 Clock Synthesizer Table 6 – ICS8442 Clock Synthesizer Pin Description Signal Name Direction Pull up/Pull down...

  • Page 16: Ics8442 Clock Generation

    XTAL_SEL Input Pull up This signal is used to select between the crystal and the TEST_CLK input to the device. When this high, crystal is selected. VCO_SEL Input Pull up This signal is used to place the internal PLL in the bypass mode.

  • Page 17: Ics8442 Programming Modes

    3.4.5 ICS8442 M and N Settings The following figure shows how the ICS8442 programmable LVDS clock synthesizer is used on the Virtex-4 MB board. DIP Switches are provided on the board for manual setting of the M and N values.
  • Page 18 LVDS interface on the Virtex-4 MB development board, while the other clock output can be used to trigger a scope during testing. The second output could also be used to provide a low jitter, LVDS clock source to a user board, such as the P240 module.

  • Page 19: Figure 10 - Mandn Dip S

    CLK_PROG_P CLK_PROG_N CONTROL Virtex-4 ICS8442 FPGA 25Mhz Figure 9 – ICS8442 Clock Synthesizer M and N DIP Switches The following tables show the DIP Switch settings for M and N selections. Please refer to Table 6 for the information on pull-up and pull-down resistors provided internal to the ICS8442 device for the M and N input signals.
  • Page 20 Table 10 – DIP Switch Setting for M[8:0] Switch Position SW1, SW10, and SW2 M[8:0] DIP1 DIP2 DIP3 DIP4 Note (1) DIP5 DIP6 DIP7 DIP8 DIP9 DIP10 Unused Note(1) – The polarity of M5 (DIP4) is the opposite of all other DIP switch positions. Table 11 –...

  • Page 21: 10/100 Ethernet Phy

    This output signal is used as the test clock output. 3.5 10/100 Ethernet PHY The Virtex-4 MB development board provides a 10/100 Ethernet port for network connection. A high-level block diagram of the 10/100 Ethernet interface is shown in the following figure followed by FPGA pin assignments for this interface.
  • Page 22 20Mhz ETH_RESETn LEDs ETH_MDIO Figure 11 – 10/100 Ethernet Interface The following table shows the FPGA pin assignments for the Ethernet interface. Table 14 – Ethernet Pin Assignments Signal Name Virtex-4 Pin # ETH_TXC ETH_RXC ETH_CRS ETH_RXDV ETH_RXD[0] ETH_RXD[1] ETH_RXD[2]...

  • Page 23: Lcd Panel

    3.6 LCD Panel The Virtex-4 MB development board provides an 8-bit interface to a 2x16 LCD panel (MYTECH MOC-16216B-B). The following table shows the LCD interface signals. Table 15 – LCD Interface Signals Signal Name Description Virtex-4 Pin # LCD Data Bit 0...

  • Page 24: Figure 12 - Usb 2.0 To Rs232 S

    CP2101/2 virtual COM port device drivers, refer to Appendix A. 3.8 RS232 The Virtex-4 MB development board provides an RS232 interface with RX and TX signals and jumpers for connecting the RTS and CTS signals. The following figure shows the RS232 interface to the Virtex-4 LX25/LX60/SX35 FPGA.

  • Page 25: User Dip And Pb Switches

    A Jumper must be installed on JP22, if RTS and CTS signal connections are needed. 3.9 User DIP and PB Switches The Virtex-4 MB development board provides four user push button switches as described in the following table. An active low signal is generated when a given switch is pressed.

  • Page 26: User Leds

    User Switch Input 8 3.10 User LEDs The Virtex-4 MB development board provides four user LEDs that can be turned “ON” by driving the LEDx signal to logic “0”. The following table shows the user LEDs and their associated Virtex- 4 FPGA pin assignments.

  • Page 27: System Ace Module Connector

    The Virtex-4 MB development board provides the SAM 50-pin connector on the board for using the Memec System ACE Module (SAM). The SAM can be used to configure the FPGA or to provide bulk flash memory to the MicroBlaze processor.

  • Page 28: Figure 15 - Systemace Module

    Figure 15 – SystemACE Module 3.12.2.1 System ACE Controller Signal Description The following table shows the System ACE Module signal assignments to the FPGA I/O pins. Table 23 - SAM Interface Signals Virtex-4 Pin System ACE SAM Connector Pin # System ACE Virtex-4 Pin...

  • Page 29: Serial Data Flash

    This section describes the procedure for programming the Atmel serial data flash on the Memec Virtex-4 MB development board. This serial flash along with a CPLD is used to configure the Virtex-4 FPGA located on the development board on power up. The following figure shows a high-level block diagram of the serial flash interface to the Virtex -4 FPGA.
  • Page 30 3.12.3.1 JTAG Chain on the Virtex-4 MB Development Board The following figure shows the JTAG chain on the Virtex-4 MB development board. As mentioned in the above section, the CPLD is used for interfacing to the configuration flash and does not provide any user logic.

  • Page 31: Figure 17 - Virtex -4 Mb D

    (PC4) Figure 17 – Virtex-4 MB Development Board JTAG Chain The following table shows jumper settings for the JTAG chain on the Virtex-4 MB development board. Since CPLD is already programmed by Memec prior to shipment, the board is shipped with jumpers installed on pins 1-2 and 4-5 (FPGA only, in the JTAG chain).

  • Page 32: Figure 18 - Serial Flashc

    Figure 18 – Serial Flash Configuration Interface 3.12.3.3 Procedure for Programming the Serial Flash 1. The Memec Virtex-4 MB development board is shipped with a self-extracting zip file called Serial_Flash_Programming. Double-click on this self-extracting zip file to unzip it. After unzipping this file, a folder called C:\Flash_Utilities is created.
  • Page 33 MCS file, select a single platform flash device that will hold the entire design configuration bits. The following table shows the platform flash devices that must be used when generating the MCS file in iMPACT for the Virtex-4 MB board: Table 27 – Platform Flash Selection...

  • Page 34: Jtag Port (Pc4)

    16. Power up the board and FPGA will configure. 3.12.4 JTAG Port (PC4) The Virtex-4 MB development board provides a JTAG port (PC4 type) connector for configuration of the FPGA. The following figure shows the pin assignments for the PC4 header on this development board.

  • Page 35: Voltage Regulators

    The following table shows the power provided on the development board for the on-board voltage sources. A 32.5W power adapter (5V @ 6.5A) is used to provide power to the on-board regulators. The following table shows typical power usage on the Virtex-4 MB development board.

  • Page 36: Bank I/O Voltage

    3.14 Bank I/O Voltage The following table shows the Virtex-4 bank I/O voltages on the Virtex-4 MB development board. Table 30 – I/O Bank Voltages Bank # I/O Voltage 2.5V...
  • Page 37 3.3V 3.3V LIO_SE_30 LIO_SE_31 LIO_SE_28 LIO_SE_29 LIO_SE_26 LIO_SE_27 LIO_SE_24 LIO_SE_25 LIO_SE_22 LIO_SE_23 LIO_SE_20 LIO_SE_21 LIO_SE_18 LIO_SE_19 LIO_SE_16 LIO_SE_17 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V LIO_SE_14 LIO_SE_15 LIO_SE_12 LIO_SE_13 LIO_SE_10 LIO_SE_11 LIO_SE_8 LIO_SE_9 LIO_SE_6 LIO_SE_7 LIO_SE_4 LIO_SE_5 LIO_SE_2 LIO_SE_3 LIO_SE_0 LIO_SE_1 LIO_LVDS_P14...
  • Page 38 Table 32– P240 Connector Pin Assignments Virtex-4 FPGA Pin # I/O Connector I/O Connector Virtex-4 FPGA Pin # Signal Name JX2 Pin # Signal Name 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V RIO_SE_42 RIO_SE_43 RIO_SE_40 RIO_SE_41 RIO_SE_38 RIO_SE_39 RIO_SE_36...

  • Page 39: Revisions

    AF24 RIO_LVDS_P8 RIO_LVDS_P9 AB20 AE24 RIO_LVDS_N8 RIO_LVDS_N9 AC20 AF23 RIO_LVDS_P6 RIO_LVDS_P7 AD22 AE23 RIO_LVDS_N6 RIO_LVDS_N7 AD23 AF21 RIO_LVDS_P4 RIO_LVDS_P5 AE21 AF22 RIO_LVDS_N4 RIO_LVDS_N5 AD21 AF19 RIO_LVDS_P2 RIO_LVDS_P3 AC18 AF20 RIO_LVDS_N2 RIO_LVDS_N3 AB18 AF18 RIO_LVDS_P0 RIO_LVDS_P1 AE18 RIO_LVDS_N0 RIO_LVDS_N1 RIO_CLKOUT_P RIO_CLKOUT_1 AA17 RIO_CLKOUT_N RIO_CLKOUT_0...

  • Page 40: Appendix A

    Appendix A 1. Double-click CP2101_Drivers.exe. Launching CP2101 Driver Installation 2. Click Next. 3. Read the license agreement and then click Yes. Cygnal License Agreement December 20, 2005...
  • Page 41 4. Browse to an acceptable installation directory, and then click Next. CP2101 Destination Location 5. The drivers are extracted to the selected directory. Click Finish once the extraction completes. CP2101 Installation Successful 6. To finish the installation, plug the USB cable into the board and a USB port on the PC. December 20, 2005...
  • Page 42 7. Turn the board power switch to the ON position. 8. The Found New Hardware Wizard launches. Click the radio button to Install the software automatically (Recommended) and then click Next. Found New Hardware Wizard 9. The driver installation begins. If installing on WindowsXP, a warning is received stating that Windows Logo testing has not passed, as shown below.
  • Page 43 10. The driver installation completes at this point. Click Finish in the Found New Hardware Wizard. CP2101 Driver Installation Complete 11. Open the Device Manager (Control Panel à System à Hardware tab à Device Manager). 12. Under the Ports heading, a new device shows up, called CP2101 USB to UART Bridge Controller.
  • Page 44 COM Port Properties 15. Change to the Port Settings tab and select Advanced. Port Settings – Advanced 16. Select COM10 in the COM Port Number field, and then click OK twice. December 20, 2005...
  • Page 45 Changing the COM Port Number 17. Close the Device Manager, and then re-open it. Under Ports, the CP2101 USB to UART Bridge Controller is now assigned to COM10, as shown below. CP2101 Assigned to COM10 December 20, 2005...

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