Agilent Technologies 6622A Service Manual page 18

The voltage readback buffer (U319C) provides unity gain for
the V READBACK signal and isolates the multiplexes circuit
from the CV control circuit (see Figure 2-5). The current
readback amplifier (U345) provides a gain of approximately
36 for the I-MON signal (0 to 0.25 V approximately) which
comes from the current sense resistor (see Figure 2-5). The
amplified signal is an input (+ IMON) to the analog
multiplexes and to the current readback inverter (P/O
U319D). The inverter slightly attenuates the signal and
provides the correct polarity to the analog multiplexes so
that the current can be monitored (- IMON) when the
output is sinking current (- current).
2-31 Readback DAC and Signal Comparator. The readback
DAC(U321), amplifier (U315D), readback signal comparator
(U324), and analog multiplexes (U323) along with the
microcomputer (U312) form an analog-to-digital converter
(ADC) which monitors the output board signals sent to the
analog multiplexes.
The readback 12-bit DAC (U321) and amplifier (U315D)
convert the digital input signal from the microcomputer to
an analog signal in the range of 0 to -10 V. The 12-bit DAC
internally formulates the 12-bit DAC data from the 8-bit
(D0-D7) data bus (same as the CV DAC described above).
The output of the DAC and the output of the analog
multiplexes are applied to the signal comparator. The
readback DAC, under the control of the microcomputer,
successively approximates the value of the multiplexer's
output to a 12-bit resolution. Starting from the most
significant bit, each bit is successively compared to the
multiplexer's output and is kept or discarded depending on
whether its value is less than or greater than the
multiplexer's output.
approximation) is evaluated by the microcomputer via its
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INT input. The microcomputer maintains a running total of
the approximations which, when complete, represents the
value of the analog multiplexer's output.
2-32 Signal Processor. This special purpose IC (U327)
processes both analog and digital signals to interface the
microcomputer with the power mesh and control circuits.
The circuits can be functionally divided into status monitor,
overvoltage detector and driver, and power-on/start-up
circuits.
Status Monitor - This circuit consists of comparators to
monitor the control loops, logic to decode these input lines,
and flip-flops to catch and hold changes. The inputs to the
status comparators are the CV LOOP, +CL LOOP, and –CL
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LOOP signals from the power control circuits (see Figure 2-
5). The outputs of the comparators are combined in logic
circuits which then go into the set inputs of flip-flops which
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hold the status of CVO, + CLO, - CLO ,and UNREG outputs.
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UNREG is decoded if the output is not regulated by a CV or
CL control loop.
The flip-flops are set by any transition into a decoded state.
This generates a record of whether any of the conditions
(CV, + CL, - CL, UNREG) existed since the last time the flip-
Each comparison (successive
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flops were reset. The STATUS RESET input line from the
microcomputer resets the flip-flops.
The status monitor circuit also receives OV SENSE and
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THERM inputs. The THERM signal is received from the
power module(s) in the power mesh (see Figure 2-5) and
indicates when an overtemperature condition exists. Note
that when the microcomputer senses the overtemperature
(OT) condition via data bus line D4, it shuts down the
output. This circuit resets automatically and restores the
output approximately 30 seconds after the temperature
drops sufficiently for safe operation.
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The OV SENSE input signal indicates when the output's
overvoltage detector circuit has been tripped and the output
has been shut-down (see overvoltage detector description
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below). The THERM and OV SENSE inputs control the OT
and OV outputs of the status monitor. Note that the OT and
OV status are not held in flip-flops. All of status monitor's
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outputs (CVO, + CLO, - CLO , OV, OT, and UNREG) are
returned to the microcomputer via data bus lines D0-D5
when chip select CSO is decoded.
Overvoltage Detector - This circuit generates the OV DRIVE
signal which shorts the output by firing the SCR crowbar
(within the power module) on the output if any of the
following conditions are present:
1. The output at the + V terminal exceeds the programmed
OV trip point (OV REF). Note that the +I READBACK
signal provides an offset to compensate for the voltage
drop across the current monitor resistor. The POV
DISABLE signal inhibits the programmable OV function
from affecting the OV DRIVE signal.
2. The voltage from the +V output terminal to the +S
terminal or from the -S terminal to the -V output terminal
exceeds 1.5 V (applies to remote sensing only).
3. A trip signal is received on the output's OV terminals.
4. The output's fixed overvoltage circuit is activated.
Power-On/Start-Up - At power-on, the output of the turn-on
comparator circuit( BIAS TRIP input signal to U327) is
initially low which holds the PCLR and ON/OFF signals
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low. With PCLR low, the microcomputer is held in the reset
state. With ON/ OFF low, the power control circuits are
held off preventing any power from reaching the output
terminals.
The turn-on comparator circuit (part of U325) monitors the
unregulated bias supply to determine if it is high enough to
guarantee regulation by the three-pin regulators. The
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medium rail voltage is also monitored to ensure that it is
above the minimum level required for proper operation of
the power module. When these two conditions are met, the
BIAS TRIP line is allowed to go high (approximately 0.7 V).
Then, after a delay of approximately 0.3 seconds (provided
by an external delay capacitor, C346), the PCLR signal goes
high allowing the microcomputer to complete its itialization
routine and set the OUTPUT ENABLE line low.This allows
ON/OFF signal to go high (+2V) enabling the control circuit
and current sources which allow power to reach the output
terminals. Note that whenever the OUTPUT ENABLE signal
2-8
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