Akai PDP4273M Service Manual page 40

a
Preliminary Datasheet
FEATURES
Analog/HDMI Dual Interface
Supports High-Bandwidth Digital Content Protection
RGB to YCbCr two-way color conversion
Automated clamping level adjustment
1.8/3.3V Power Supply
100-pin LQFP Pb-Free Package
RGB and YCbCr Output Formats
Analog Interface
8-bit Triple Analog to Digital Converters
150 MSPS Maximum Conversion Rate
Macrovision Detection
2:1 Input Mux
Full Sync Processing
Sync Detect for "Hot Plugging"
Mid-Scale Clamping
Digital Video Interface
HDMI 1.0, DVI 1.0
150 MHz HDMI Receiver
Supports High-Bandwidth Digital Content Protection
(HDCP 1.1)
Digital Audio Interface
HDMI 1.0 compatible audio interface
S/PDIF (IEC90658 compatible) digital audio output
Multi-channel I S audio output (up to 8 channels)
2
APPLICATIONS
Advanced TV
HDTV
Projectors
LCD Monitor
GENERAL DESCRIPTION
The AD9880 offers designers the flexibility of an analog interface
and High-Definition Multimedia Interface (HDMI) receiver
integrated on a single chip. Also included is support for High
bandwidth Digital Content Protection (HDCP).
Analog Interface
The AD9880 is a complete 8-bit 150 MSPS monolithic analog
interface optimized for capturing Component Video (YPbPr) and
RGB graphics signals. Its 150 MSPS encode rate capability and
full power analog bandwidth of 300 MHz supports all HDTV
formats (up to 1080p) and FPD resolutions up to SXGA (1280 x
1024 at 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8V and 3.3V power supply, analog input, and Hsync.
Three-state CMOS outputs may be powered from 1.8V to 3.3V.
The AD9880's on-chip PLL generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 150 MHz.
AD9880 Preliminary Technical Information
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Analog/HDMI Dual Display Interface
3/26/2004
FUNCTIONAL BLOCK DIAGRAM
Analog Interface
R/G/B or YPbPr
2:1
IN0
Clamp A/D
MUX
R/G/B or YPbPr
IN1
2:1
HSYNC 0
HSYNC 1 MUX
HSYNC 0 2:1
HSYNC 1 MUX
Sync
2:1
SOGIN 0
Processing and
SOGIN 1 MUX
Clock
COAST Generation
REFOUT
CLAMP
CKINV
CKEXT
FILT
SCL
SDA Serial Register and
Power Management
Digital Interface
RX0+
RX0-
RX1+
RX1-
RX2+
HDMI Receiver
RX2-
RXC+
RXC-
R
TERM
MCL
MDA
HDCP
DDCSCL
DDCSDA
PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The
AD9880 also offers full sync processing for composite sync and
Sync-on-Green (SOG) applications.
Digital Interface
The AD9880 contains a HDMI 1.0 compatible receiver and
supports all HDTV formats (up to 1080p) and display resolutions
up to SXGA (1280 x 1024 at 75 Hz). The receiver features an
intra-pair skew tolerance of up to one full clock cycle. With the
inclusion of HDCP, displays may now receive encrypted video
content. The AD9880 allows for authentication of a video receiver,
decryption of encoded data at the receiver, and renewability of that
authentication during transmission as specified by the HDCP 1.1
protocol.
Fabricated in an advanced CMOS process, the AD9880 is provided
in a space-saving 100-lead LQFP surface-mount plastic package
and is specified over the 0 ºC to 70 ºC temperature range.
One Technology Way, P.O Box 9106, Norwood, MA 02062–9106, USA
Tel: 617/329–4700
38／72
AD9880
R/G/B 8X3
or YCbCr
2
DATACK
HSOUT
VSOUT
SOGOUT
R/G/B 8X3
Ref
REFIN YCbCr (4:2:2
or 4:4:4)
2
DATACK
HSOUT
VSOUT /A0
SOGOUT
DE
R/G/B 8X3
or YCbCr
2
DATACK
DE
Hsync
Vsync
SPDIF OUT
8 Channel
I S OUT
2
MCLK
LRCLK
AD9880
 Analog Devices, Inc., 2004
Fax: 617–326–8703