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2-10 Digital AFT
The tuning system of this chassis also utilises a digital AFT system.
In this operation,
the tuner is automatically
adjusted
to the required
tuning
point of the
broadcast
signal by increasing
and decreasing
the tuning voltage within the synchronisation
range, whilst checking the 2 signals from the lF/Video decoder IC, ICI 01 cTDA8361/8362z.
The signals which are outputted from pins 4 and 44 of ICI 01 are fed to pins 15 and 33 of the
CPU via the impedance
and voltage converter circuit.
The CPU checks the voltage level of the Ident signal at pin 15 and the AFT-S signal at pin
33, and controls the tuning voltage which is supplied to the tuner.
The CPU determines
that the correct tuning point is achieved when the Ident signal is Hi(5V)
and the AFT-S signal is 2.OV to 3.OV.
When the Ident signal is Hi(5V) and AFT-S signal is greater than 3.OV, the CPU judges that
the tuning point is incorrect and increases the tuning voltage output from pin 14 of CPU to
correct the tuning point.
When the Ident signal is Hi(5V) and AFT-S signal is less than 2.OV, the CPU again judges
that the tuning point is incorrect and decreases the tuning voltage output from pin 14 of CPU
_
to correct the tuning point.
This function only operates during the channel changing and the presetting modes.
-16-
A7:A
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