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Dimtel iGp-5120F Technical User's Manual

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iGp-5120F Signal Processor
Technical User Manual
Author:
Revision:
Dmitry Teytelman
1.6
September 19, 2008

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Summary of Contents for Dimtel iGp-5120F

  • Page 1 Signal Processor Technical User Manual Author: Revision: Dmitry Teytelman September 19, 2008...
  • Page 2 Information in this document is subject to change without notice. Copyright © Dimtel, Inc., 2007. All rights reserved. Dimtel, Inc. 2059 Camden Avenue, Suite 136 San Jose, CA 95124 Phone: +1 650 862 8147 Fax: +1 603 907 0210...

  • Page 3: Table Of Contents

    CONTENTS Contents 1 Regulatory Compliance Information 2 Introduction 2.1 Delivery Checklist ......2.2 System Overview ......
  • Page 4 CONTENTS 8 Warranty and Support 8.1 Warranty ......40 8.2 Support ......40 9 Appendix A: Address Map 9.1 Registers .

  • Page 5: Regulatory Compliance Information

    The exposed metal parts of the unit are connected to the power ground to protect against electrical shock. Always use an outlet with properly con- nected protective ground. iGp-5120F was designed and tested to operate safely under the following environmental conditions: ˆ indoor use;...

  • Page 6: Introduction

    8. CE declaration of conformity. System Overview Ethernet Linux IOC USB driver EPICS IOC computer Triggers Temperature and Fiducial interface supply monitoring RF clock Input Output FPGA Slow analog Acquisition and digital I/O memory Figure 1: iGp-5120F block diagram 4 of 58...
  • Page 7 (DAC). A block diagram of the iGp-5120F system is shown in Figure 1. The main signal processing chain consists of a high-speed analog-to-digital converter (ADC), a field programmable gate array (FPGA), and a high-speed DAC and is driven by the radio frequency (RF) clock.

  • Page 8: Front Panel Features

    Front Panel Features Figure 2: Front panel features 1) Power switch This momentary-on lighted switch turns iGp-5120F on and off. From the off condition, the unit will take 25–30 seconds to fully boot. Shutdown time after power switch actuation is 5–10 seconds.
  • Page 9 2.3 Front Panel Features STATUS FPGA Local bus activity is indicated in green. SATURATION FIR filter operation status. Green indicates normal operation, red — output saturation. CLOCK MISSING Red indication when the input RF clock is not detected.

  • Page 10: Rear Panel Features

    5) Monitor output Connect a monitor for the initial setup of the iGp- 5120F. 6) Network This RJ-45 connector is used to connect the iGp-5120F to the control network. All control and data acquisition communications with the unit are performed via this network connection.

  • Page 11: Getting Started

    (Fig. 3, item 1) is in the correct position (115 or 230 V). 1. Configure voltage selection switch (Fig. 3, item 1). Mains supply re- quirements for the iGp-5120F are listed in Table 8; 2. Connect RF clock at 3 dBm nominal level (Fig. 2, item 5);...

  • Page 12: Ioc Setup

    (when, for example, a keyboard or a monitor is not available), such configuration can be performed using a dedicated network. Set up a network consisting of the iGp-5120F, a network hub or a switch, and a remote computer. The iGp-5120F is delivered with the following network configuration:...
  • Page 13 IOC Setup (a) Welcome screen (b) Timezone (c) Date (d) Time (e) Network (f) Password (g) Device name Figure 4: Setup screens b) Timezone In this panel, select the appropriate timezone. c) Date Set the correct date using the calendar.

  • Page 14: Utilities And Selftest

    Device name This device name is the second part of the EPICS process variable (PV). All PV names start with IGPF:X:, where X is the device name. As delivered the iGp-5120F defaults to device name TEST pro- ducing PVs of the form IGPF:TEST:DELAY. If multiple iGp-5120F units are to be deployed they must be assigned differing device names.

  • Page 15: Selftest

    4.2 Selftest Write a single location. usbw <addr> <val> Read a block of memory. The data is send to usbrblk <addr> <len> stdout and can be redirected into a file. Write a block of memory. This utility expects the usbwblk <addr>...
  • Page 16 4.2 Selftest 1 Terminating t h e IOC 3 System i n f o r m a t i o n : Function : f e e d b a c k Harmonic number : 64 D e m u l t i p l e x i n g : R e v i s i o n : 1 .
  • Page 17 4.2 Selftest 46 FID c l o c k d e l a y t e m p e r a t u r e r i s e ( deg C ) : 5 . 8 47 DAC c l o c k d e l a y t e m p e r a t u r e r i s e ( deg C ) : 6 .

  • Page 18: User Interface

    User Interface User Interface User interface functionality for the iGp-5120F is implemented using extensi- ble display manager (EDM). Software installation CD is designed for seamless installation on a client computer, configured with Fedora 8 version of Linux operating system.

  • Page 19: Starting The Edm

    5.2 Starting the EDM Starting the EDM Once the software has been installed and the IOCs added via IOC add you are ready to start the EDM. iGp-5120F display panels are opened by the following command: [iGp@host ~]$ iGp_display [device name] Note that the device name is optional.

  • Page 20: Control Panel

    5.3 Display Panels 5.3.2 Control Panel Figure 6: Control panel This window integrates most important controls for the iGp-5120F. COEFFICIENT SET Feedback coefficient set selector. SHIFT GAIN Output gain adjustment, each step doubles the feedback gain. DOWNSAMPLING Processing channel downsampling factor.
  • Page 21 5.3 Display Panels GROW/DAMP ENABLE Enables coefficient set switching during data acquisition. REC. DOWNSAMPLE Acquisition channel downsampling factor. This downsampling process is completely decoupled form the processing channel downsampling. RECORD LENGTH Number of samples to acquire during data acquisi- tion.
  • Page 22 5.3 Display Panels Devices Opens the control panel for the integrated devices. Drive Opens the drive control panel. Waveforms Opens the data acquisition and display panel. Environment Opens the environmental monitoring panel. Config S/R Configuration save/restore panel. Clock missing RF clock missing indicator.

  • Page 23: Coefficients Panel

    5.3 Display Panels 5.3.3 Coefficients Panel Figure 7: Coefficients panel Coefficients control panel allows the user to manipulate the loaded coef- ficients sets and verify that the hardware is in sync with the panel display. The panel is split into three functional groups: new coefficients vector, coef- ficient set 0, and coefficient set 1.

  • Page 24: Coefficient Generator Panel

    5.3 Display Panels 5.3.4 Coefficient Generator Panel Figure 8: Coefficient generator panel Coefficient generator panel shown in Figure 8 allows the user to generate feedback processing controllers and explore different delay/gain/bandwidth tradeoffs. This tool generates a coefficient set based on sampling a sine wave.

  • Page 25: Timing Panel

    DCM RESET Pushbutton for resetting feedback processing DCM (DCM1) and data acquisition DCM (DCM2). Push this button if DCM unlocked indicators are red and the RF clock is present at the iGp-5120F front panel. On rare occasions due to intermittent RF clock loss DCM might need to be reset even though lock indicators are green.
  • Page 26 5.3 Display Panels DCM PHASE ADC data acquisition phasing. This parameter is config- ured at the factory and does not need to be adjusted in operation. FID CLOCK OFFSET Offset between the ADC clock and the fiducial clock. This parameter is configured at the factory and does not need to be adjusted in operation.

  • Page 27: Drive Panel

    5.3 Display Panels 5.3.6 Drive Panel Figure 10: Drive panel Drive panel shown in Figure 10 provides the means to generate an ar- bitrary waveform on a bunch-by-bunch basis. The drive output has many applications: ˆ Back-end timing;...
  • Page 28 5.3 Display Panels updated every turn. Consequently, the highest output frequency is 2 with significantly better frequency resolution. FREQUENCY Drive frequency in Hz. AMPLITUDE Drive amplitude in the range from 0 to 1. WAVEFORM SELECTION Waveform selector allows the user to drive the beam with sine, square, sawtooth, and arbitrary signals.

  • Page 29: Waveforms Panel

    5.3 Display Panels 5.3.7 Waveforms Panel Figure 11: Waveforms panel A set of IOC subroutines postprocesses the data in the real-time and pro- vides four concise plots displayed in the waveform panel shown in Figure 11. The four plots are: bunch-by-bunch mean and root mean square (RMS) of bunch oscillations, time-domain signal of a bunch with the largest RMS.

  • Page 30: Environmental Monitoring Panel

    The environmental monitoring panel shown in Figure 12 provides instanta- neous readouts and five minute histories of three supply voltages and five temperatures in the iGp-5120F system. It also monitors IOC CPU temper- ature and two cooling fan speeds: one mounted on the IOC CPU and the main chassis fan.

  • Page 31: Device Controls Panel

    Device Controls Panel Device controls panel provides control interface to several peripherals inte- grated in the iGp-5120F. There are four adjustable delay units for controlling the high-speed ADC, DAC, and fiducial timing. WARNING: While these delay controls can be used to adjust var- ious clock timings, one is strongly advised to perform the adjust- ments via the timing panel.
  • Page 32 5.3 Display Panels Figure 13: Device controls panel connector. Channel 7 is used to trim the output offset of the high-speed DAC. That setting is preconfigured at the factory and should not be changed. From the device control panel one can open four other panels: MAX1202 ADC (section 5.3.10), GPIO (section 5.3.11), TIMING (section 5.3.5), and...

  • Page 33: 8-Channel Adc Panel

    5.3 Display Panels 5.3.10 8-channel ADC Panel Figure 14: 8-channel ADC panel This panel provides readouts of the eight 12-bit ADC channels updated at 1 Hz. The input signals are low-pass filtered to 1 kHz before sampling. 5.3.11 GPIO Panels General-purpose I/O control panel in practice consists of two different panels,...
  • Page 34 5.3 Display Panels Figure 15: General-purpose I/O panel: bit-by-bit driver Figure 16 shows the front/back-end panel. This panel is split into two portions: front/back-end registers and the phase servo loop. The register con- trols include front and back-end phase and attenuation. Front-end phase reg- ister setting is provided as a readout labeled FRONT-END PHASE DAC SET- TING.
  • Page 35 5.3 Display Panels Figure 16: General-purpose I/O panel: front/back-end driver buttons. Depending on which zero crossing the phase shifter is centered dif- ferent loop polarities need to be selected using LOOP SIGN. LOOP GAIN parameter must be adjusted to optimize the loop response in terms of noise, bandwidth, and overshoot.

  • Page 36: Power Amplifier Panel

    MATLAB ® and use LabCA package for communicating with EPICS. iGp read Top-level data acquisition tool. This script will read out data from the iGp-5120F, create a timestamped directory, and save the data in a file called gd.mat. This file is in a format, compatible with MAT- LAB ®...
  • Page 37 A single argument is the PV root name, e.g. IGPF:TEST:. adctest This function extracts the iGp-5120F data and fits a sinewave to it. It accepts the IOC device name and the number of times to repeat the acquisition/fitting cycle.

  • Page 38: Specifications

    Specifications Specifications Table 1: General specifications Parameter Definition Operating frequency 509 MHz RF input level 9 to 3 dBm, -3 dBm nominal Number of FIR taps Harmonic number 5120 Fiducial signal Falling edge trigger, NIM level Minimum fiducial pulse width 1.96 ns...
  • Page 39 Specifications Table 2: High-speed ADC and DAC specifications Parameter Definition ADC inputs 2 complementary ADC input full scale sensitivity 200 mV peak-to-peak ( 10 dBm) ADC resolution 8 bits ADC input bandwidth 1.26 GHz DAC outputs 2 complementary...
  • Page 40 Specifications Table 5: Data acquisition controls Parameter Definition Recording memory selection FPGA internal blockRAM or external SRAM Measurement trigger Internal or external External trigger arming Single or after every beam data read- Recorded growth length Adjustable in units of 4 samples, up to full memory length Hold-off...
  • Page 41 Specifications Table 7: Drive pattern generator Parameter Definition Output waveform Sine, sawtooth, square, or arbitrary Amplitude 0–1 Bunch selectability Bunch-by-bunch drive enable mask. Allows any subset of bunches to be driven Frequency range, bunch-by-bunch 0– mode Frequency range, turn-by-turn 0–...

  • Page 42: Warranty And Support

    Warranty and Support Warranty Dimtel Inc. warranties this product for a period of one year from the date of shipment against defective workmanship or materials. This warranty ex- cludes any defects, failures or damage caused by improper use or inadequate maintenance, installation or repair performed by Customer or a third party not authorized by Dimtel, Inc.

  • Page 43: Appendix A: Address Map

    Registers 9.1.1 Overall Layout The general register layout for the iGp-5120F reserves space below 0x100 for FIR coefficients. This allows for a maximum of 128 coefficients in two sets. Control and status registers are placed starting at 0x100. Table 9: FPGA registers: FIR...

  • Page 44: Gateware Config Register

    9.1 Registers Table 9 – continued from previous page Address Bits Definition 15:0 FIR coefficient 12, set 0 0x000018 15:0 FIR coefficient 12, set 1 0x000019 15:0 FIR coefficient 13, set 0 0x00001a 15:0 FIR coefficient 13, set 1...
  • Page 45 9.1 Registers Table 10 – continued from previous page Address Bits Definition DAC drive phase: 0 - 0 degrees, 1 - 180 degrees Turn-by-turn mode of the arbitrary waveform gen- erator Arbitrary waveform generator enable GPIO driver select, 0 - bit-by-bit, 1 - FBE...

  • Page 46: Drive Pattern Memory

    9.2 Drive pattern memory Table 10 – continued from previous page Address Bits Definition Hold-off length 0x000106 31:0 Number of samples to hold setsel inverted before data acquisition Gateware config register (read-only) 0x000107 12:0 Harmonic number 14:13 Demux mode, 0 - by4, 1 - by6, 2 - by8, 3 - reserved...

  • Page 47: Environmental Monitor

    MAX104 ADC. The ADC provides two current sources for temperature measurement. ADC temperature is given by ptat pconst 273. In the iGp-5120F the two sources are loaded by 5.1 kΩ ptat pconst resistors and connected to AIN2 and AIN3.

  • Page 48: Max1202 8-Channel Adc

    Device 2, AIN5-AIN5 differential measurement 0x00011f MAX1202 8-channel ADC iGp-5120F includes 8-channel 12-bit serial-interface ADC. The SPI controller for the ADC uses 8 consecutive addresses, as shown in Table 13. ADC is continuously polled by the controller. Reading one of the channel registers returns the result of the last conversion.

  • Page 49: Ad8842 8-Channel Dac

    0x000127 AD8842 8-channel DAC iGp-5120F includes 8-channel 8-bit serial-interface DAC. The SPI controller for the DAC uses 8 consecutive addresses, as shown in Table 14. Writing to one of the registers starts an SPI writing cycle which loads the new value into the DAC.

  • Page 50: Ecl Delay Lines

    9.7 General-purpose digital I/O ECL delay lines Several MC100EP195 ECL delay lines are used on the iGp-5120F to line up the received RF clock and the fiducial signal. These lines are controlled by registers described in Table 15. Delay line 0 controls the delay of the ADC clock. Relative delay between lines 1 and 2 is used to achieve reliable detection of the fiducial falling edge...

  • Page 51: Memory

    Front-end attenuation 0x00013e Back-end attenuation 0x00013f Memory iGp-5120F is configured with two data acquisition memory spaces: block- RAM internal to the FPGA and external SRAM. Memory address mapping is provided in Table 18. Table 18: Data acquisition memory Address range Definition...

  • Page 52: Appendix B: Connector Pinouts

    Appendix B: Connector Pinouts Appendix B: Connector Pinouts 12 10 8 6 4 2 Figure 18: Pin numbering for 16-pin header-type front-panel connectors Pin numbering scheme for the 16-pin front-panel connectors is shown in Figure 18. Pin definitions for the 7-channel DAC are given in Table 19 and for the 8-channel DAC - in Table 20.
  • Page 53 Appendix B: Connector Pinouts Table 20: 8-channel ADC pinout Pin number Definition Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 35 36 Figure 19: Pin numbering for general-purpose digital I/O connector Figure 19 shows the pin numbering for the general-purpose digital I/O connector.
  • Page 54 Appendix B: Connector Pinouts Table 21: General-purpose digital I/O pinout Pin number Definition Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19...
  • Page 55 Appendix B: Connector Pinouts Table 21 – continued from previous page Pin number Definition Bit N/C 53 of 58...
  • Page 56 Appendix B: Connector Pinouts 54 of 58...

  • Page 57: Glossary

    Glossary Glossary Glossary analog-to-digital converter (ADC) An electronic circuit that converts continuous analog signals to discrete digital numbers. 5, 6, 9, 13, 15, 23, 24, 29, 31, 32, 34, 36, 42, 43, 45, 46, 48 blockRAM ® Random access memory integrated in Xilinx FPGA in a form of mul- tiple 18 kbit blocks.
  • Page 58 Glossary emitter coupled logic (ECL) A logic device family in which current is steered through bipolar tran- sistors to compute logical functions. The chief characteristic of ECL is that the transistors are always in the active region and can thus change state very rapidly, allowing ECL circuits to operate at very high speed.
  • Page 59 Glossary input/output (I/O) An interface for transferring analog or digital signals to or from the device. 5, 13, 15, 31, 48, 51 input-output controller (IOC) An embedded computer used to interface the hardware to the control system. 5, 9–13, 15, 16, 19, 27, 28, 34, 35 Linux A Unix-like open-source operating system.
  • Page 60 Glossary transistor-transistor logic (TTL) A class of digital circuits built from bipolar junction transistors and resistors. TTL defining signal levels: = 2 4 = 0 4 = 2 V, and = 0 8 V 57 universal serial bus (USB) A serial bus standard to interface a wide variety of devices.

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