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Summary of Contents for Intel X38
- Page 1 ® Intel X38 Express Chipset Memory Technology and Configuration Guide White Paper January 2008 Document Number: 318469-002...
- Page 2 Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
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Page 3: Table Of Contents
Table 3-2. DDR2 and DDR3 DRAM Device Timing Support ........10 ® Table 3-3. Intel X38 Valid FSB/Memory Speed Configurations ......11 Table 4-1. Sample Dual Channel Symmetric Organization Mode ......13 Table 4-2. Sample Dual Channel Stacked Asymmetric Organization Mode....13 Table 4-3. Sample Dual Channel L-Shaped Asymmetric Organization Mode....14... -
Page 4: Revision History
Revision History Revision Description Revision Number Date Initial release -001 October 2007 Corrected DDR3 DIMM Module Support -002 January 2008 Added Configuration details § White Paper... -
Page 5: Introduction
® enhancements and simplified population rules offered by Intel Fast Memory Access ® and Intel Flex Memory Technology in the platforms based on the Intel X38 Express Chipset. White Paper... -
Page 6: Technology Enhancements Of (Intel Fast Memory Access ((Intel Fma)
Scheduling, Command Overlap, Out of Order Scheduling, and Opportunistic Writes. Just in Time Command Scheduling The Intel X38 Express Chipset has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next. -
Page 7: Out Of Order Scheduling
Intel X38 Express Chipset monitors system memory requests and issues pending write requests to memory at times when they will not impact memory read requests. -
Page 8: Supported Memory Technologies And Configurations
Supported Memory Technologies and Configurations Supported Memory Technologies and Configurations Memory Technology Supported The X38 Express Chipset supports the following DDR2 and DDR3 Data Transfer Rates, DIMM Modules, and DRAM Device Technologies: DDR2 Data Transfer Rates: • ⎯ 667 (PC2-5300) and 800 (PC2-6400) DDR3 Data Transfer Rates: •... -
Page 9: Table 3-1. Memory Technology Support Details
Supported Memory Technologies and Configurations Table 3-1. Memory Technology Support Details Mem. DIMM DRAM DRAM # of # of # of # of Page Type Card Cap. Device Org. DRAM Physical Row /Col Banks Size Ver. Tech. Devices Device Address Inside Ranks Bits... -
Page 10: Dram Device Timing Support
1333 MT/s 1333 MT/s ECC Support For DDR3 the X38 Express Chipset does NOT support ECC, does not support ECC un- buffered DIMMs, and it does not support any memory configuration that mixes non- ECC with ECC un-buffered DIMMs. For DDR2 the X38 Express Chipset does support ECC and ECC un-buffered DIMMs but it does NOT support any memory configuration that mixes non-ECC with ECC un- buffered DIMMs. -
Page 11: Valid Front Side Bus And Memory Speeds
FSB is populated, the memory will be under-clocked to align with the FSB. System Memory DIMM Configuration Support The X38 Express Chipset directly supports one or two channels of DDR2 or DDR3 memory with the following DIMM configurations: ⎯... -
Page 12: Memory Organization And Operating Modes
Memory Organization and Operating Modes ® The Intel X38 Express Chipset memory interface is designed with Intel Flex Memory Technology so that it can be can be configured to support single-channel or dual- channel DDR2 or DDR3 memory configurations. Depending upon how the DIMMs are populated in each memory channel, a number of different configurations can exist for DDR2 or DDR3. -
Page 13: Dual Channel Asymmetric Modes
Memory Organization and Operating Modes Table 4-1. Sample Dual Channel Symmetric Organization Mode Cumulative Channel 0 Cumulative Top Channel 1 Rank Top Address Population Address in Channel 0 Population in Channel 1 Rank 3 0 MB 2560 MB 0 MB 2560 MB Rank 2 256 MB... -
Page 14: Table 4-3. Sample Dual Channel L-Shaped Asymmetric Organization Mode
Memory Organization and Operating Modes 4.2.2.2 L-shaped Asymmetric Mode In this addressing mode the lowest DRAM memory is mapped to dual channel operation and the top most DRAM memory is mapped to single channel operation. In this mode the system can run at one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array.
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