Summary of Contents for Altera timequest
- Page 1 TimeQuest Timing Analyzer Quick Start Tutorial 101 Innovation Drive Software Version: San Jose, CA 95134 Document Version: www.altera.com Document Date: © December 2009 UG-TMQSTANZR-1.1...
- Page 2 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation.
-
Page 3: Table Of Contents
Step 12. Verify Timing in the TimeQuest Timing Analyzer ....... . - Page 4 TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation...
-
Page 5: Chapter 1. About This Tutorial
1. About this Tutorial This tutorial describes the steps to constrain and perform static timing analysis with the TimeQuest Timing Analyzer. For this tutorial, use the fir_filter design that ships with the Quartus ® II software. Figure 1–1 shows the fir_filter design schematic. - Page 6 1–2 Chapter 1: About this Tutorial TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation...
-
Page 7: Chapter 2. Quick Start Tutorial
6.0. APEX, FLEX, and Mercury device families are not supported. Procedures Use the following steps to constrain and analyze a design with the TimeQuest Timing Analyzer. Each step includes the GUI procedure and the command-line equivalent. Step 1: Open and Setup Your Design in the Quartus II Software In the Quartus II software, browse to and open the fir_filter located in the <qdesign folder>/fir_filter/ folder. -
Page 8: Step 3: Perform Initial Compilation
You can also create a post-fit netlist for the initial database. However, creating a post-map is less time consuming and is sufficient for this tutorial example. Step 4: Launch the TimeQuest Timing Analyzer Launch the TimeQuest Timing Analyzer to create and verify all timing constraints and exceptions with the procedures in Table 2–4. -
Page 9: Step 5: Create A Post-Map Timing Netlist
Create the clocks in the fir_filter design and assign the proper clock ports with the procedures in Table 2–7. For more information about constraints supported by the TimeQuest Timing Analyzer, refer to the TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook. -
Page 10: Step 7: Update The Timing Netlist
Table 2–9. Constraints that have been specified with the TimeQuest Timing Analyzer GUI or in the console are not automatically saved. If you inadvertently overwrite any of your constraints later in the design flow, use this initial SDC file to restore all of your constraints. -
Page 11: Step 9: Generate Timing Reports For The Initial Timing Netlist
Table 2–10. The TimeQuest Timing Analyzer provides easy to use report generation commands that allow you to verify all timing requirements in the design. Table 2–10. Report SDC Command... - Page 12 Declare the paths from clk to clkx2 as false paths with the procedures in Table 2–13. When you complete this procedure, the TimeQuest Timing Analyzer indicates that the Clock Transfers report is outdated. Table 2–13. Declaring False Paths...
-
Page 13: Step 10: Save Constraints To An Sdc File
After you enter the set_false_path in the GUI, all generated report panels are labeled “Out of Date,” indicating that the report panels do not contain results that reflects the current state of constraints or exceptions in the TimeQuest Timing Analyzer. To update the report panels, you must regenerate all of the reports. -
Page 14: Step 11. Perform Timing-Driven Compilation
Step 12. Verify Timing in the TimeQuest Timing Analyzer To obtain detailed timing analysis data on specific paths, view timing analysis results in the TimeQuest Timing Analyzer. After a full place-and-route is performed, launch the TimeQuest Timing Analyzer as described in “Step 4: Launch the TimeQuest Timing Analyzer”. - Page 15 For the fir_filter design, the Slack column equals the End Point TNS, indicating that there is only one failing path for the clk clock domain. © December 2009 Altera Corporation TimeQuest Timing Analyzer Quick Start Tutorial...
- Page 16 To fully constrain the fir_filter design, constrain all input and output ports. Use the Set Input Delay and Set Output Delay dialog boxes, or the set_input_delay and set_output_delay constraints to specify the input and output delay values. TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation...
- Page 17 2–24. The procedures in Table 2–24 generate a report where clk clocks the destination register to the design destination register bus acc:inst3|result and reports the top 10 worst paths. © December 2009 Altera Corporation TimeQuest Timing Analyzer Quick Start Tutorial...
-
Page 18: Conclusion
As you create new constraints or exceptions, rerun the Quartus II Fitter to optimize the design based on your new constraints or exceptions. Multiple iterations on the design may be necessary to achieve the desired results. TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation... -
Page 19: Commands And Tcl Scripts
Example 3–2 shows the content of the timequest_setup.tcl script. Use this script to specify the TimeQuest Timing Analyzer as the default timing analysis tool. The Classic Timing Analyzer is the default timing analyzer in the Quartus II software. Example 3–2. The timeqest_setup.tcl Script... - Page 20 Use this script to create a post-fit database, set up the timing netlist, read in the golden.sdc and io_cons.sdc files, and generate reports for the design. TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation...
- Page 21 -clock clk 1.0 [get_ports {d[*] reset newt}] #set the output delays for the design set_output_delay -clock clk 1.5 [get_ports {yn_out[0] yn_out[1] \ yn_out[2] yn_out[3] yn_out[4] yn_out[5] yn_out[6] yn_out[7] yvalid follow}] © December 2009 Altera Corporation TimeQuest Timing Analyzer Quick Start Tutorial...
- Page 22 3–4 Chapter 3: Script Examples Commands and Tcl Scripts TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation...
-
Page 23: Additional Information
(Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital Let-... - Page 24 A warning calls attention to a condition or possible situation that can cause injury to the user. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. TimeQuest Timing Analyzer Quick Start Tutorial © December 2009 Altera Corporation...